computer-organization2-292883412 (1).ppt

Tty

1. Computer Organization

2. 3 Fundamental Components of
Computer
The CPU (ALU, Control Unit, Registers)
The Memory Subsystem (Stored Data)
The I/O subsystem(I/O devices)
I/O Device
Subsystem
Address Bus
Data Bus
Control Bus
CPU
Memory
Subsystem
2

3. Each of these Components are
connected through Buses.
BUS -Physically a set of wires. The
components of the Computer are
connected to these buses.
Address Bus
Data Bus
Control Bus
3

4. Address Bus
Used to specify the address of the
memory location to access.
Each I/O devices has a unique address.
(monitor, mouse, cd-rom)
CPU reads data or instructions from
other locations by specifying the
address of its location.
CPU always outputs to the address bus
and never reads from it.
4

5. Data Bus
Actual data is transferred via the data
bus.
When the cpu sends an address to
memory, the memory will send data via
the data bus in return to the cpu.
5

6. Control Bus
Collection of individual control signals.
Whether the cpu will read or write data.
CPU is accessing memory or an I/O
device
Memory or I/O is ready to transfer data
6

7. I/O Bus or Local Bus
In today’s computers the the I/O
controller will have an extra bus called
the I/O bus.
The I/O bus will be used to access all
other I/O devices connected to the
system.
Example: PCI bus
7

8. Instruction Cycles
Procedure the CPU goes through to
process an instruction.
1. Fetch -get instruction
2. Decode -interperate the instruction
3. Execute -run the instruction.
8

9. CPU organization
CPU controls the Computer
The CPU will fetch, decode and execute
instructions.
The CPU has three internal sections:
register section, ALU and Control Unit
9

10. Register Section
Includes collection of registers and a
bus.
Processor’s instruction set architecture
are found in this section.
Non accessible registers by the
programmer. These are to be used for
registers to latch the address being
accessed and a temp storage register.
10

11. Arithmetic/Logic Unit (ALU)
Performs most Arithmetic and logical
operations.
Retrieves and stores its information
with the register section of the CPU.
11

12. MEMORY ORGANIZATION
•Memory Hierarchy
•Main Memory
•Auxiliary Memory
•Associative Memory
•Cache Memory
•Virtual Memory
•Memory Management Hardware`
12

13. Memory
Main memory consists of a number of
storage locations, each of which is
identified by a unique address
The ability of the CPU to identify each
location is known as its addressability
Each location stores a word i.e. the
number of bits that can be processed by
the CPU in a single operation. Word
length may be typically 16, 24, 32 or as
many as 64 bits.
A large word length improves system
performance, though may be less efficient on
occasions when the full word length is not
used
13

14. MEMORY HIERARCHY
Magnetic
tapes
Magnetic
disks
I/O
processor
CPU
Main
memory
Cache
memory
Auxiliary memory
Register
Cache
Main Memory
Magnetic Disk
Magnetic Tape
Memory Hierarchy is to obtain the highest possible
access speed while minimizing the total cost of the memory system
Memory Hierarchy
14

15. Memory Subsystem
2 Types of Memory:
–ROM : Read Only Memory
Program that is loaded into memory and
cannot be changed also retains its data even
without power.
–RAM : Random Access Memory
Also called read/write memory. This type of
memory can have a program loaded and then
reloaded. It also loses its data with no power.
15

16. Different ROM Chips
Masked ROM :
ROM that is programmed with data when
fabricated. Data will not change once installed.
Hardwired.
Programmable ROM (PROM) :
Capable of being programmed by the user with
a ROM programmer. Not hardwired.
Erasable PROM (EPROM) :
Much like the PROM this EPROM can be
programmed and then erased by light.
EEPROM :
Another form of EPROM but is reprogammable
electrically.
16

17. Different RAM Chips
Dynamic RAM (DRAM) :
Leaky capacitors. Caps are charged and slowly
leak until they are refreshed to there original
data locations. Ex. Computer RAM
Static RAM (SRAM) :
Much like a register. The contents stay valid
and does not have to be refreshed. SRAM is
faster than DRAM but cost more Ex. Cache
–Each RAM chip has 2^n * m. n address
inputs and m bidirectional data pins
17

18. The operation of cache memory
1.Cachefetchesdatafrom
nexttocurrentaddressesin
mainmemory
2.CPUcheckstosee
whetherthenextinstruction
itrequiresisincache
3.Ifitis,thenthe
instructionisfetchedfrom
thecache–averyfast
position
4.Ifnot,theCPUhasto
fetchnextinstructionfrom
mainmemory-amuch
slowerprocess
Main
Memory
(DRAM)
CPU
Cache
Memory
(SRAM)
= Bus connections 18

19. Addressing Modes
Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Stack
19

20. Immediate Addressing
Operand is part of instruction
Operand = address field
e.g. ADD 5
–Add 5 to contents of accumulator
–5 is operand
No memory reference to fetch data
Fast
Limited range
20

21. Immediate Addressing
Diagram
OperandOpcode
Instruction
21

22. Direct Addressing
Address field contains address of
operand
Effective address (EA) = address field
(A)
e.g. ADD A
–Add contents of cell A to accumulator
–Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out
effective address
Limited address space
22

23. Direct Addressing Diagram
Address AOpcode
Instruction
Memory
Operand
23

24. Direct Addressing Diagram
Address AOpcode
Instruction
Memory
Operand
24

25. Indirect Addressing (1)
Memory cell pointed to by address field
contains the address of (pointer to) the
operand
EA = (A)
–Look in A, find address (A) and look there
for operand
e.g. ADD (A)
–Add contents of cell pointed to by contents
of A to accumulator
25

26. Indirect Addressing (2)
Large address space
2
n
where n = word length
May be nested, multilevel, cascaded
–e.g. EA = (((A)))
Draw the diagram yourself
Multiple memory accesses to find
operand
Hence slower
26

27. Indirect Addressing Diagram
Address AOpcode
Instruction
Memory
Operand
Pointer to operand
27

28. Register Addressing (1)
Operand is held in register named in
address filed
EA = R
Limited number of registers
Very small address field needed
–Shorter instructions
–Faster instruction fetch
28

29. Register Addressing (2)
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
–Requires good assembly programming or
compiler writing
–N.B. C programming
register int a;
c.f. Direct addressing
29

30. Register Addressing Diagram
Register Address ROpcode
Instruction
Registers
Operand
30

31. Register Indirect Addressing
C.f. indirect addressing
EA = (R)
Operand is in memory cell pointed to by
contents of register R
Large address space (2
n
)
One fewer memory access than indirect
addressing
31

32. Register Indirect Addressing Diagram
Register Address ROpcode
Instruction
Memory
OperandPointer to Operand
Registers
32

33. Displacement Addressing
EA = A + (R)
Address field hold two values
–A = base value
–R = register that holds displacement
–or vice versa
33

34. Displacement Addressing Diagram
Register ROpcode
Instruction
Memory
Operand
Pointer to Operand
Registers
Address A
+
34

35. Relative Addressing
A version of displacement addressing
R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from
current location pointed to by PC
c.f locality of reference & cache usage
35

36. Base-Register Addressing
A holds displacement
R holds pointer to base address
R may be explicit or implicit
e.g. segment registers in 80x86
36

37. Indexed Addressing
A = base
R = displacement
EA = A + (R)
Good for accessing arrays
–EA = A + (R)
–R++
37

38. Stack Addressing
Operand is (implicitly) on top of stack
e.g.
–ADDPop top two items from stack
and add
38

39. Input-Output Organization
11-1 Peripheral Devices
–I/O Subsystem
Provides an efficient mode of communication
between the central system and the outside
environment
–Peripheral (orI/O Device)
Input or Output devices attached to the
computer
11-2 Input-Output Interface
1) A conversion of signal values may be
required
39

40. 2) A synchronization mechanism may be needed
–The data transfer rate of peripherals is usually slower than the
transfer rate of the CPU
3) Data codes and formats in peripherals differ from the
word format in the CPU and Memory
4) The operating modes of peripherals are different from
each other
–Each peripherals must be controlled so as not to disturb the
operation of other peripherals connected to the CPU
–Interface
Special hardware components between the CPU and
peripherals
Supervise and Synchronize all input and output transfersInterface
Keyboard
and
display
terminal
Interface
Magnetic
tape
Interface
Magnetic
disk
Interface
Printer
Processor
Data
Control
Address
I/O bus
40

41. –Transfer
–Synchronous Data Transfer
All data transfers occur
simultaneously during the
occurrence of a clock pulse
Registers in the interface
share a common clock with
CPUregisters
–Asynchronous Data Transfer
Internal timing in each unit
(CPU and Interface) is
independent
Each unit uses its own private
clock for internal registers
41

42. Source
unit
Destination
unit
(a) Block diagram
Valid data
Data
Strobe
(b) Timing diagram
Data bus
Strobe Source
unit
Destination
unit
(a) Block diagram
Valid data
Data
Strobe
(b) Timing diagram
Data bus
Strobe Fig. 11-3 Source-
initiated strobe
Fig. 11-4 Destination-
initiated strobe

 

42

43. –Handshake : Agreement betweeSource
unit
Destination
unit
(a) Block diagram
Valid data
Data
(b) Timing diagram
Data bus
Data valid
Data accepted
Data valid
Data accepted
Place data on bus
Enable data valid.
Disable data valid
Invalidate data on bus
Accept data from bus
Enable data accepted
Disable data accepted
Ready to accept data
(initial state)
(c) Sequence of events
Source unit Destination unit
Fig. 11-5 Source-initiated handshakeSource
unit
Destination
unit
(a) Block diagram
Valid data
(b) Timing diagram
Data bus
Data valid
Ready for data
Data valid
Data bus
Place data on bus
Enable data valid.
Disable data valid
Invalidate data on bus
(initial state)
Accept data from bus
Disable reday for data
Ready to accept
data.
Enable ready for data
(c) Sequence of events
Ready for data
Source unit Destination unit Fig. 11-6 Destination-initiated handshake






43

44. 11-4 Modes of Transfer
–Data transfer to and from peripherals
1) Programmed I/O
2) Interrupt-initiated I/O
3) Direct Memory Access (DMA)
4) I/O Processor (IOP)
Interrupt-initiated I/O
1) Non-vectored : fixed branch
address
2) Vectored : interrupt source
supplies the branch address
(interrupt vector)Read status register
Check flag bit
Read data register
Transfer data to memory
Continue
with
program
Flag
Operation
complete ?
= 0
= 1
yes
no
44

45. –Polling
Identify the highest-priority source by software
means
–One common branch address is used for all
interrupts
–Program polls the interrupt sources in sequence
–The highest-priority source is tested first
Polling priority interrupt
–If there are many interrupt sources, the time
required to poll them can exceed the time available
to service the I/O device
–따라서Hardware priority interrupt
–Daisy-Chaining :Device 1
PI PO
Device 3
PI PO
Device 2
PI PO
To next
Device
CPU
INT
INTACK
Interrupt request
Interrupt acknowledge
Processor data bus
VAD 1 VAD 3VAD 2
“1” “1” “0”
45

46. One stage of the daisy-chain priority
arrangement : Fig. 11-13
No interrupt request
Invalid : interrupt request, but no acknowledge
No interrupt request : Pass to other device
(other device requested interrupt)
Interrupt requestS Q
R
Vector address
Delay
Enable
RF
PI
Priority in
Interrupt
request
from device
Open-collector
inverter
Interrupt request to CPU
Priority out
PO
VAD
RFPI POEnable
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1




INTACK
INT
46

47. Direct Memory Access (DMA)
–DMA
DMA controller takes over the buses to manage
the transfer directlybetween the I/O device
and memoryCPU
BR
BG
DBUS
WR
ABUS
RD
Bus request
Bus grant
Address bus
Write
Read
Data bus
High-impedance
(disable)
when BG is
enabled
DMA
Controller
BR
BG




47

48. –Transfer Modes
1) Burst transfer :
2) Cycle stealing transfer
–DMA Controller ( Intel 8237 DMAC)
DMA Initialization Process
–1)Set Address register :
memory address for read/write
–2)Set Word count register :
the number of words to transfer
–3)Set transfer mode :
4) DMA transfer start :
–5) EOT (End of Transfer) : Control
logic
CS
Data bus
buffers
Control register
Data bus
DMA select
Internal bus
RS
Interrupt
BG
BR
RD
WR
Register select
Read
Write
Bus request
Bus grant
Interrupt
Address register
Word count register
Address bus
buffers
Address bus
DMA request
DMA Acknowledge
to I/O device
48

49. –DMA Transfer (I/O to Memory)
1) I/O Device sends a DMA request
2) DMAC activates the BRline
3) CPU responds with BGline
4) DMAC sends a DMA acknowledge
to the I/O device
5) I/O device puts a word in the data
bus (for memory write)
6) DMAC write a data to the address
specified by Address register
7) Decrement Word count register
8) Word count
9) Word count registerI/O
Peripheral
device
DMA acknowledge
Address
select
CPU
Interrupt
Address Data
BG
BR
RDWR
Random access
memory (RAM)
Address DataRDWR
Direct memory
access (DAM)
controller
Interrupt
Address DataRDWR
BG
RS
DS
BR
DMA request
Read control
Write control
Address bus
Data bus
49

50. Input-Output Processor (IOP)
–IOP
Communicate directly with all I/O devices
Fetch and execute its own instruction
–IOP instructions are specifically designed to facilitate
I/O transfer
–DMAC must be set up entirely by the CPU
Designed to handle the details of I/O
processingMemory unit
Central Processing
unit (CPU)
Input-output
processor (IOP)
Memory bus
PD PDPDPD
Peripheral devices
I/O bus
50

51. –CPU -IOP Communication
Memory units acts as a message center :
–each processor leaves information for the other CPU operations IOP operations
Send instruction
to test IOP path
Transfer status word
to memory location
If status OK. , send
start I/O instruction
to IOP
Access memory for
IOP program
CPU continues with
another program
Conduct I/O transfer
using DMA ; prepare
status report
I/O transfer completed
interrupt CPU
Request IOP status
Transfer status word
to memory location
Check status word
for correct transfer
Continue
51

52. Input/output Devices
Input/output devices are required for
users to communicate with the
computer.
In simple terms, input devices bring
information INTO the computer and
output devices bring information OUT of
a computer system. These input/output
devices are also known as peripherals.
52

53. Input Devices are:
Keyboard
Mouse
Joystick
Scanner
Light Pen
Touch Screen
53

54. Output devices are:
Printers
Plotters
Monitor
LCD
54

55. 55
Intel 8086/8088 Microprocessors
Intel 8086 and 8088 Microprocessors are
the basis of all IBM-PC compatible
computers
(8086 introduced in 1978, first IBM-PC released in 1981)
All Intel, AMD and other advanced
microprocessors are based on and are
compatible with the original 8086/8
At Power Up and Reset time, Pentiums,
Athlonsetc all look like 8086 processors

56. 56
Intel 8086/8088 Microprocessors
Intel 8086 is a 16b microprocessor:
–16b data registers, 16b ALU
Width of external data bus:
–8086: 16b
–8088: 8b
Width of external address bus: 16b+4b=20b
Some techniques to optimise the CPU
performance when it’s executing programs
Segment: Offset memory model
Little-EndianData Format

57. 57
8086/8088
Original IBM PC used 8088 microprocessor
8088 is similar to the 8086, but it has an
external 8b data bus & only 4B-deep queue
–For cost reduction reasons
We can consider 8086 and 8088 together
PC clones often used 8086 for better
performance
8-bit bus reduces performance, but meant
cheaper computers

58. 58
8086/8088 Functional UnitsExecution Unit
(EU)
Bus Interface
Unit(BIU)
Fetches Opcodes,
Reads Operands,
Writes Data
8086/8088 MPU

59. 59
8086/8088
8086/8088 consists of two internal units
–The execution unit (EU) -executes the
instructions
–The bus interface unit (BIU) -fetches
instructions, reads operands and writes results
The 8086 has a 6B prefetch queue
The 8088 has a 4B prefetch queue

60. 60
8086/8088 Internal OrganisationTemporary
Registers
ALU
Flags
EU
Control
AH AL
BH BL
CH CL
DH DL
SP
BP
DI
BI
CS
DS
SS
ES
IO
Internal
Communications
Registers
SUMMATION
Address Bus 20 bits
Data Bus
Bus
Control
1234
Instruction Queue
8088
Bus
EU BIU

61. BIU Elements
Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing
the current instruction
–The memory interface is slower than the processor execution
time so this speeds up overall performance
Segment Registers:
–CS, DS, SS and ES are 16b registers
–Used with the 16b Base registers to generate the 20b address
–Allow the 8086/8088 to address 1MB of memory
–Changed under program control to point to different segments
as a program executes
Instruction Pointer (IP) contains the Offset Address of
the next instruction, the distance in bytes from the
address given by the current CS register
61

62. 62
8086/8088 20-bit Addresses16-bit Segnment Base Address 0000
16-bit Offset Address
20-bit Physical Address
CS
IP

63. BIU Elements
Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing
the current instruction
–The memory interface is slower than the processor execution
time so this speeds up overall performance
Segment Registers:
–CS, DS, SS and ES are 16b registers
–Used with the 16b Base registers to generate the 20b address
–Allow the 8086/8088 to address 1MB of memory
–Changed under program control to point to different segments
as a program executes
Instruction Pointer (IP) contains the Offset Address of
the next instruction, the distance in bytes from the
address given by the current CS register
63

64. 64MAXIMUM
MODE
MINIMUM
MODE
1 40
20 21
8086
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
Vcc
AD15
A16,S3
A17,S4
A18,S5
A19,S6
/BHE,S7
MN,/MX
/RD
/RQ,/GT0
/LOCK
/S2
/S1
/S0
QS0
QS1
/TEST
READY
RESET
/RQ,/GT1
HOLD
/WR
IO/M
DT/R
/DEN
ALE
/INTA
HLDA

65. 65
8086/8088 Summary
First Generation (introduced June 1978)
One of the first 16b processors on the
market
16b internal registers
16/8b external data bus
20b address bus (1MB addressable)
Used in 1
st
generation IBM PCs (1981)

66.  Thanks
66