Copy of AXI4_uploading_advanced_extended_interconnect.pptx

AXI protocol

1. AMBA – AXI 4 Protocol

2. What is AMBA? A dvanced M icrocontroller B us A rchitecture On-chip bus protocol from ARM On-chip interconnect specification for the connection and management of functional blocks including processor and peripheral devices. AMBA is an open standard

3. Advanced Peripheral Bus (APB) Low Bandwidth peripherals Low Power Non-Pipelined Latched address & control Simple interface Single master to multiple slaves Advanced High performance Bus (AHB) Higher Bandwidth peripherals Pipelined operation Burst transfers Split transactions multiple masters and multiple slaves

4. What is AXI 3? A dvanced e X tensible I nterface Latest version of AMBA -Industry standard on-chip communication Enables higher performance vs. existing bus architectures Comes under the category of AMBA 4. Most commonly used Bus architecture in modern complex SOC’s and FPGA’s.

5. About the AXI Protocol is suitable for high-bandwidth. provides high-frequency operation without using complex bridges meets the interface requirements of a wide range of components is suitable for memory controllers with high initial access latency provides flexibility in the implementation of interconnect architectures is backward-compatible with existing AHB and APB interfaces.

6. Features of AXI 3 separate address/control and data phases (spread over 5 independent channels) support for unaligned data transfers, using byte strobes uses burst-based transactions with only the start address issued separate read and write data channels, that can provide low-cost Direct Memory Access (DMA) support for issuing multiple outstanding addresses support for out-of-order transaction completion

7. AXI Master AXI Slave Write Address/control Channel Write Data Channel Write Response Channel Channel Architecture Read Address / Control Channel Read Data & Response Channel

8. AXI Master AXI Slave Write Address/control Channel AWREADY Write Data Channel WREADY Write Response Channel B READY Write Transaction Master issues Address & control and holds this control info till the occurrence of “AWREADY” Master sends the data and holds this data till the occurrence of “WREADY” Slave acknowledges the completion of write transaction and holds this info till the occurrence of “BREADY”

9. AXI Master AXI Slave Read Address / Control Channel ARREADY Read Data & Response Channel RREADY Read Transaction Master Issues address and control info for read transaction and holds this info till the occurrence of “ARREADY” Slave returns the data and acknowledgement signals and holds this info till the occurrence of “RREADY”

10. Burst transactions Reduces address channel utilization which permits effective utilization Specifying the starting the starting address for a transaction is sufficient. Data and address linked together

11. Outstanding Transactions Out of Order Transactions Enable Parallel processing of transactions. Avoid a high initial latency slave blocking the channel. Fast slaves may return the data before the slow slaves. Effectively reduce the transaction latency.

12. Channel Handshaking Two-way handshaking ( VALID  READY ) in all 5 channels. Source uses VALID to indicate when valid data is available. Destination uses READY signal to indicate the data is accepted. For read and write data channel LAST signal is used to indicate the last data transfer in a burst is taking place.

13. Signals of Write Address Channel

14. Signals of Write Data Channel

15. Signals of Write Response Channel

16. Signals of Read Address & Control Channel

17. Signals of Read Data & Response Channel

18. ARVALID ARREADY RVALID RREADY Dependency in Read Transaction Dependency in Write Transaction AWVALID AWREADY WVALID WREADY BVALID BREADY Can Wait Must Wait

19. Handshaking Timing

20. Burst in AXI Master provides the start address of a burst. It is the duty of the slave to calculate the addresses of subsequent transfers in a burst. In order to simplify the design address generator in the slave, the address is allocated to a slave in 4KB unit (i.e., Busrts can not cross 4KB boundary). No early burst termination is supported. Write strobes can be made ‘0’ to make the remaining write beats ignored by the slave. Master just ignores the read data.

21. Burst Types Fixed Burst Address remains constant within a burst. Suited for FIFO – like designs Incrementing Burst Increment value depends on the transfer seize. Suited for sequential memory - like devices. Wrapping Burst Wrap boundary = transfer_size * number_transfer . start address must be aligned & burst length is to be 2,4,8, 16. Suited for cache line refill.

22. Responses OKAY Everything is OK. EX - OKAY Exclusive access is successful. SALVE ERROR FIFO overflow or underflow. Unsupported transfer size & try to read – only region. DECODE ERROR No slave presented at that address. nly region.

23. Narrow Transfers Unaligned Transfers

24. Verification Environment

25. Verification Scenarios Constraint randomization (to cover the following scenarios) All the possible burst types. All the possible burst sizes (narrow and unaligned transfers). All the possible types of responses. Out of order transactions. Outstanding transactions. Maximum burst length. Different Handshaking timings.

26. Thank U