D Flip Flop D flip-flop is Modified form of SR flip-flop In the basic SR flip flop circuit the indeterminate input condition of "SET" = logic "0" and "RESET" = logic "0" is forbidden. In SR Flip Flop when R=S=0 or R=S=1 , the outputs Q and Q' either don't change or they are indeterminate(Invalid) Clk S R Qn +1 X X Qn 1 Qn 1 1 1 1 1 1 1 1 invalid Truth Table of SR Flip-Flop
Construction In order to overcome the shortcomings of RS flip flop , the D flip flop was designed . The D flip-flop is the most important of the clocked flip-flops as it ensures that inputs S and R are never equal to one at the same time. D-type flip-flops are constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a single D (data) input .
Symbol &Circuit Diagram (using Nand Gates)
Truth table Of D Flip Flop Clk D Qn +1 x Qn 1 1 1 1