DC transfer characteristics of a CMOS inverter

These explains us the detailed operation and behavior of a CMOS inverter

1. Courtesy : Prof Andrew Mason
CMOS Inverter: DC Analysis
By
Dr.S.Rajaram,
Thiagarajar College of Engineering

2. Courtesy : Prof Andrew Mason
CMOS Inverter: DC Analysis
•Analyze DC Characteristics of CMOS Gates
by studying an Inverter
•DC Analysis
–DC value of a signal in static conditions
•DC Analysis of CMOS Inverter
–Vin, input voltage
–Vout, output voltage
–single power supply, VDD
–Ground reference
–find Vout = f(Vin)
•Voltage Transfer Characteristic (VTC)
–plot of Vout as a function of Vin
–vary Vin from 0 to VDD
–find Vout at each value of Vin

3. Courtesy : Prof Andrew Mason
Inverter Voltage Transfer Characteristics
•Output High Voltage, V
OH
–maximum output voltage
•occurs when input is low (Vin = 0V)
•pMOS is ON, nMOS is OFF
•pMOS pulls Vout to VDD
–V
OH = VDD
•Output Low Voltage, V
OL
–minimum output voltage
•occurs when input is high (Vin = VDD)
•pMOS is OFF, nMOS is ON
•nMOS pulls Vout to Ground
–V
OL = 0 V
•Logic Swing
–Max swing of output signal
•V
L = V
OH - V
OL
•V
L = VDD

4. Courtesy : Prof Andrew Mason
Inverter Voltage Transfer Characteristics
•Gate Voltage, f(Vin)
–V
GSn=Vin, V
SGp=VDD-Vin
•Transition Region (between V
OH and V
OL)
–Vin low
•Vin < Vtn
–Mn in Cutoff, OFF
–Mp in Triode, Vout pulled to VDD
•Vin > Vtn < ~Vout
–Mn in Saturation, strong current
–Mp in Triode, V
SG
& current reducing
–Vout decreases via current through Mn
–Vin = Vout (mid point) ≈ ½ VDD
–Mn and Mp both in Saturation
–maximum current at Vin = Vout
–Vin high
•Vin > ~Vout, Vin < VDD - |Vtp|
–Mn in Triode, Mp in Saturation
•Vin > VDD - |Vtp|
–Mn in Triode, Mp in Cutoff
Error in Fig : Replace V
OH to
V
OL
+
V
GSn
-
+
V
SGp
-
Vin < V
IL
input logic LOW
Vin > V
IH
input logic HIGH
•Drain Voltage, f(Vout)
–V
DSn=Vout, V
SDp=VDD-Vout

5. Courtesy : Prof Andrew Mason
Transistor operating regions
RegionnMOS pMOS
A Cutoff Linear
B SaturationLinear
C SaturationSaturation
D Linear Saturation
E Linear Cutoff
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp

6. Courtesy : Prof Andrew Mason
Noise Margin
•Input Low Voltage, V
IL
–Vin such that Vin < V
IL = logic 0
–point ‘a’ on the plot
•where slope,
•Input High Voltage, V
IH
–Vin such that Vin > V
IH
= logic 1
–point ‘b’ on the plot
•where slope =-1
•Voltage Noise Margins Error in Fig : Replace V
OH to V
OL
–measure of how stable inputs are with respect to signal interference
–VNM
H = V
OH - V
IH = VDD - V
IH
–VNM
L
= V
IL
- V
OL
= V
IL
–desire large VNM
H and VNM
L for best noise immunity
1


Vout
Vin

7. Courtesy : Prof Andrew Mason
Switching Threshold
•Switching threshold = point on VTC where Vout = Vin
–also called midpoint voltage, V
M
–here, Vin = Vout = V
M
•Calculating V
M
–at V
M, both nMOS and pMOS in Saturation
–in an inverter, I
Dn
= I
Dp
, always!
–solve equation for V
M
–express in terms of V
M
Error in Fig : Replace V
OH to
V
OL
–solve for V
M
DptpSGp
p
tnGSn
n
tnGSn
OXn
Dn IVVVVVV
L
WC
I 
222
)(
2
)(
2
)(
2

22
)(
2
)(
2
tpMDD
p
tnM
n
VVVVV 


tpMDDtnM
p
n
VVVVV )(


p
n
p
n
tntp
M
VVVDD
V







1

8. Courtesy : Prof Andrew Mason
Effect of Transistor Size on VTC
•Recall
•If nMOS and pMOS are same size
–(W/L)n = (W/L)p
–Coxn = Coxp (always)
•If
•Effect on switching threshold
–if 
n
 
p
and Vtn = |Vtp|, V
M
= VDD/2, exactly in the middle
•Effect on noise margin
–if 
n
 
p
, V
IH
and V
IL
both close to V
M
and noise margin is good
L
W
k
nn
'
p
p
n
n
p
n
L
W
k
L
W
k













'
'


p
n
p
n
tntp
M
VVVDD
V







1
32or
L
W
C
L
W
C
p
n
p
oxpp
n
oxnn
p
n




















1, 













p
n
n
p
p
n
then
L
W
L
W




since L normally min. size for all tx,
can get betas equal by making Wp larger than Wn