dcpe (1).pdf central university of Karnataka gulbarga

Briefing about FPGA board

1. r
CENTRAL UNIVERSITY OF
KARNATAKA
DIGITAL CONTROL OF POWER
ELECTRONICS
PRESENTATION TITLE:
EDGE Spartan 7
FPGA Development
Board

2. Field-Programmable Gate
Array (FPGA)
Comprehensive Overview and Insights

3. What is FPGA?
• FPGA stands for Field-Programmable Gate Array.
• It is an integrated circuit configured by the user after manufacturing.
• Enables hardware customization for specific digital logic applications.
• Bridges gap between fixed ASICs and programmable processors.

4. Why FPGA?
•Reconfigurable Hardware – Unlike ASICs (fixed) and CPUs/GPUs (predefined), FPGAs
can be programmed and reprogrammed anytime.
•Parallel Processing – FPGAs can execute many operations simultaneously, giving
higher performance for certain tasks.
•Customization – Designers can tailor the hardware to the exact application (signal
processing, control, AI, etc.).
•Rapid Prototyping – Useful for testing designs before committing to costly ASIC
fabrication.
•Low Latency – Direct hardware execution reduces delay, important in real-time
applications.
•Energy Efficiency – Custom logic can be optimized for lower power compared to
running the same task on a CPU/GPU.
•Long Product Life – Hardware can be updated in the field without changing the physical
chip.

5. FPGA APPLICATIONS

7. •TYPES OF FPGA
LOW-END FPGAs
Focus: Low power, low cost, simple applications
Examples:
Intel Cyclone series
AMD Spartan series
Lattice ICE40/Mach XO
Use Cases: Consumer electronics, basic control systems
MID-RANGE FPGAs
Focus: Balanced performance vs. cost
Examples:
Intel Arria series
AMD Artix-7/Kintex-7
Lattice ECP3/ECP5
Use Cases: Industrial automation, automotive, video processing
HIGH-END FPGAs
Focus: Maximum performance and logic density
Examples:
Intel Stratix series
AMD Virtex series
Achronix Speedster
Use Cases: Data centers, aerospace, 5G infrastructure

8. - Why Spartan-7?
•Cost-Effective – Provides good performance at a low cost, ideal for students, researchers, and
entry-level industrial applications.
•Low Power Consumption – Optimized for power efficiency, making it suitable for battery-
powered and portable applications.
•Small Form Factor – Available in compact packages, useful for space-constrained designs.
•High Performance-to-Cost Ratio – Balances speed, logic resources, and affordability.
•Broad I/O Support – Supports multiple I/O standards for flexible interfacing with external
devices.
•On-Chip Resources – Includes DSP slices, block RAM, clock management, and rich logic
blocks.
•Vivado Design Suite Support – Fully compatible with Xilinx Vivado, enabling modern toolchain
usage.
•Ideal for Learning & Prototyping – Popular in academic projects, labs, and proof-of-concept
developments.
•Scalability – Part of the Xilinx 7-series family, making it easier to migrate designs to larger
devices (Artix-7, Kintex-7, Virtex-7) if needed.
•Applications – Embedded systems, motor control, DSP applications, IoT devices, and
communication systems.

9. - Why EDGE board?
•Educational Focus – Specially designed for students, researchers, and developers to learn
FPGA/embedded system concepts.
•Spartan-7 Based – Many EDGE boards come with Xilinx Spartan-7 FPGA, balancing performance and
affordability.
•All-in-One Development Platform – Integrates multiple peripherals (switches, LEDs, seven-segment
displays, VGA, audio, sensors, etc.) on a single board for quick prototyping.
•Plug-and-Play Design – Ready-to-use hardware eliminates the need for extensive wiring or external
modules.
•I/O Expansion – Provides headers/pins to connect external devices, motors, sensors, or communication
modules.
•USB/JTAG Support – Easy programming and debugging directly from Vivado or other tools.
•Onboard Memory – Often includes SRAM/SDRAM/Flash for data storage and advanced applications.
•Connectivity Options – May feature UART, HDMI, Ethernet, or Wi-Fi depending on the version.
•Documentation & Community Support – Comes with tutorials, example projects, and wide adoption in
academics.

10. Comparison: FPGA vs ASIC

11. Edge Spartan 7
FPGA Development Board
A comprehensive exploration of features, specifications, applications, and programming of this versatile
FPGA development platform
Powered by Xilinx XC7S15 FTGB196-1 Spartan-7 FPGA

12. FPGA Architecture
•Main Components of FPGA Architecture
•Configurable Logic Blocks (CLBs)
•Heart of FPGA.
•Made up of slices containing Look-Up Tables (LUTs), multiplexers, and flip-flops.
•Implement combinational and sequential logic.
•Interconnects / Routing
•Programmable wiring channels that connect CLBs, I/O blocks, and other resources.
•Provide flexibility to implement any digital circuit.
•I/O Blocks (IOBs)
•Interface between internal FPGA logic and external pins.
•Support multiple voltage and signaling standards (LVTTL, LVCMOS, etc.).
•Switch Matrix
•Allows configurable paths between logic blocks and interconnects.

13. •DSP Slices
•Dedicated blocks for high-speed arithmetic (multipliers, accumulators, filters).
•Used in DSP, AI, image/video processing.
•Block RAM (BRAM)
•On-chip memory blocks for data storage.
•Can be configured as single-port, dual-port, or FIFO memory.
•Clock Management (CMT: PLL/MMCM)
•Provides clock distribution, frequency synthesis, and phase alignment.
•Configuration Memory
•Stores the FPGA programming (bitstream).
•Loaded on power-up from external flash or directly via JTAG/USB.

14. Key Features:
•Xilinx XC7S15 FTGB196-1 Spartan-7 FPGA with 12,800 logic elements
•8MB SPI FLASH Memory for configuration storage
•On-board USB JTAG programmer & USB-UART interface
•Integrated WiFi (ESP-12F) & Bluetooth connectivity
•Comprehensive I/O: VGA, ADC/DAC, LCD, 7-segment display, switches,
buttons, LEDs
•Expansion capability for CMOS camera & TFT display

15. Reconfigurable Hardware
•Reconfigurable Hardware refers to digital hardware whose functionality can be changed
(configured and reconfigured) after manufacturing.
•Unlike fixed hardware (ASICs, CPUs, GPUs), it allows adaptation to different tasks without
fabricating a new chip.
Key Features
•Programmability – User defines hardware functionality using HDL (VHDL/Verilog).
•Flexibility – Can implement different digital circuits on the same device.
•Field Reconfiguration – Can be updated/reprogrammed in real time even after deployment.
•Parallelism – Executes multiple operations simultaneously at the hardware level.
•Scalability – Can be upgraded or modified as system requirements grow.

16. FPGA Architecture
Configurable Logic Blocks (CLBs):The core of FPGA functionality, these blockscontainlogic gates
and a small amount of memory that can be programmed to perform various logical functions. They
are the building blocks for creating more complex digital circuits.

17. I/O Blocks (Input/Output Blocks):Locatednext to every physical input or output pin, these blocks connect
the internal logic of the FPGA to the external environment. They can be programmed to act as
inputs,outputsor tri-states, enabling the FPGA to communicate with external devices and systems.

18. Programmable Interconnects:A network of programmable wiring that connects the logic blocks. These interconnects
can be configured to route signals between different logic blocks, allowing the creation of complex digital circuits by
defining how data flows through the FPGA.
PROGRAMMABLE INTERCONNECTS

32. Power Supply
EDGE Spartan 7 development board can get 5V power from either USB JTAG Port U6 or External Power Supply connector J1.
Switch SW3 can be used to select the source of power from USB or External Power Supply.
Board consist of 3 Voltage regulators (3.3v, 1.8v and 1v). The Kit requires 3.3v supply for FPGA I/O, Clock, USB, ADC, DAC,
FLASH, and so on. The 1.8v Voltage is for FPGA Auxiliary supply. The 1v power supply is dedicated for FPGA Core and Block
RAM voltage.
Caution: Only 5v Supply must be provided to the board from external source or USB connector.
Programming hardware
FPGA can be configured either from USB JTAG using Xilinx software or by on-board SPI FLASH Memory.
FPGA configured through JTAG gets erased when the power supply is removed or by pressing reset button SW1.
To store the data permanently on FPGA, we have to store the configuration bit file to SPI FLASH Memory. It automatically
reconfigures the FPGA after reset or Power on.
The EDGE Spartan 7 FPGA Development board is fully compatible with Xilinx Vivado design suite with on-board USB JTAG
Interface.

33. USB UART
The EDGE Board includes FT2232 IC acts as USB UART Bridge to communicate board with windows PC COM port
interface.
The UART Transmitter and Receiver lines of FTDI chip is directly connected to the Spartan 7 FPGA I/O pins for USB UART
Communication.

34. WIFI Communication
The EDGE Board contains On-board ESP8266 12F WIFI Module connected with Spartan 7 FPGA through serial interface.
The ESP WIFI Modem helps to communicate FPGA with cloud. The Data can be stored and retrieved from the cloud with
the help of AT Commands. The range of communication for WIFI modem is 50 – 100 meter distance.
Note: To enable power supply to the WIFI Modem, place jumper at Enable and centre pin of J11. To disable power, place
jumper at Disable and centre pin of J11.
J10 connector got TX, RX and GPIO0 Line of ESP12F WIFI module for testing and firmware update.

35. Bluetooth Communication
The EDGE contains low power Bluetooth 4.0 BLE interface on-board. The Bluetooth Module CC2541 is serially interfaced
with FPGA with Transmit and Receive lines.
Note: To enable power supply to the Bluetooth Modem, place jumper at Enable and centre pin of J13. To disable power,
place jumper at Disable and centre pin of J13.
J15 connector got TX, RX and Key Line of Bluetooth module for testing and firmware update.

36. Slide Switches
The EDGE board includes 16 SPDT slide switches for digital input. These digital inputs are connected to Spartan 7 FPGA
through resistors for protection against short circuit. Slide switch outputs constant high or constant low based on the
user changing its position.

37. Push Button
The Board contains 5 Push buttons for providing momentary digital inputs. They are
connected to FPGA lines through resistors to prevent short circuit. By default the switch is in
Active low. When the user pressed the push button they are driven high.

38. LEDs
The Kit consists of 16 LEDs for displaying digital outputs. These LED’s are connected with FPGA through a series resistor.
Logic High signal turns ON LED and Logic Low signal turns OFF LED to demonstrate the digital output.
Note: To enable LEDs, Jumper needs to be placed at ground position at J4 and J9.
The J4 connector enables LEDs D2 to D9.
The J9 connector enables LEDs D10 to D17.

39. Seven segment Display
The EDGE Board consist of 4 digit 7 segment displays with common anode. Each of the seven segment contains LEDs
can be turned on by sending active low signal.
For example, to display digit 8 in the seven segments display. All the segments are enabled using active low ‘0’ signal.

40. 2×16 LCD
The EDGE board consist of 2×16 LCD interface at the female connector J2. LCD displays is interfaced in the 8
bit data mode, RS pin are used to select data/command mode and En are used to enable the LCD.
Note: R/W pin is connected to ground to keep LCD in always write mode.

41. SPI ADC
The EDGE board contains Microchip MCP3208 8-channel 12-bit SPI ADC. ADC is connected to FPGA
through 4 SPI lines. The SPI signals are Serial Clock, Data in, Data out, chip select.
Input Analog signal to ADC channel Ch0 – Ch5 are provided at male connector J7.
Light Detect Resistor LDR is connected at the ADC channel Ch6. LDR provides variable resistance based on
the light intensity that falls upon it.
Temperature Sensor LM35 is connected at the ADC channel Ch7.
Refer MCP3208 Datasheet to learn more about its working.

42. SPI DAC
The EDGE Board consist of Microchip MCP4921 SPI DAC to perform digital to analog conversion. The
output is available at 2nd row 1st pin of the connector J7.
SPI interface provides Serial clock, Data input and chip select to FPGA with DAC. Spartan6 FPGA act as
master and MCP4921 act as slave device.

43. VGA
The EDGE Board contains 12 bit VGA interface to generate VGA signals from FPGA
and display the output in the VGA monitor. The 12 bit VGA output the depth of 4096
colours in the Monitor. Series resistors are used to construct DAC to implement VGA
interface.

44. PS2
The EDGE board contains PS2 interface connected with FPGA through clock and data lines. PS2 interface is directly
provided in the USB connector. Only USB keyboard reverse compatible with ps2 connector work on this port.

45. Stereo Jack
Stereo Audio Jack with low pass filter is connected on the FPGA I/O lines on the EDGE Board. Stereo Jack provides
delta sigma audio output.

46. Buzzer
The Edge board contains piezo buzzer interface with FPGA through transistor. 5v Buzzer is used provide alert
tone. Buzzer’s resonant frequency is 3.8 kHz (where you can expect its best performance).
Note: To enable Buzzer, place jumper at Enable and centre pin of J6. To disable power, place jumper at Disable
and centre pin of J6.

47. SPI ADC
The EDGE board contains Microchip MCP3208 8-channel 12-bit SPI ADC. ADC is connected to FPGA through 4 SPI lines.
The SPI signals are Serial Clock, Data in, Data out, chip select.
Input Analog signal to ADC channel Ch0 – Ch5 are provided at male connector J7.
Light Detect Resistor LDR is connected at the ADC channel Ch6. LDR provides variable resistance based on the light
intensity that falls upon it.
Temperature Sensor LM35 is connected at the ADC channel Ch7.
Refer MCP3208 Datasheet to learn more about its working.

48. SPI DAC
The EDGE Board consist of Microchip MCP4921 SPI DAC to perform digital to analog conversion. The output
is available at 2nd row 1st pin of the connector J7.
SPI interface provides Serial clock, Data input and chip select to FPGA with DAC. Spartan6 FPGA act as
master and MCP4921 act as slave device.

49. VGA
The EDGE Board contains 12 bit VGA interface to generate VGA signals from FPGA and display the output in the VGA
monitor. The 12 bit VGA output the depth of 4096 colours in the Monitor. Series resistors are used to construct DAC to
implement VGA interface.

50. PS2
The EDGE board contains PS2 interface connected with FPGA through clock and data lines. PS2 interface is directly
provided in the USB connector. Only USB keyboard reverse compatible with ps2 connector work on this port.

51. Stereo Jack
Stereo Audio Jack with low pass filter is connected on the FPGA I/O lines on the EDGE
Board. Stereo Jack provides delta sigma audio output.

52. Buzzer
The Edge board contains piezo buzzer interface with FPGA through transistor. 5v Buzzer is used provide alert tone.
Buzzer’s resonant frequency is 3.8 kHz (where you can expect its best performance).
Note: To enable Buzzer, place jumper at Enable and centre pin of J6. To disable power, place jumper at Disable and
centre pin of J6.

53. Clock
The Edge board contains 50 MHz Oscillator to provide clock input to the FPGA. The input clock can drive
MMCMs or PLL to generate clocks of various frequencies and with known phase relationships that may be
needed throughout a design.

54. TFT Display
The EDGE Board contains TFT display interface at the J14 connector. TFT display communicates with
FPGA through SPI protocol. SPI TFT is made of ST7735 SPI controller with 160×128 Display.

55. 20 Pin Expansion Connector / CMOS Camera Interface
Expansion connector J5 provides 16 I/O lines from Spartan 7 FPGA to the external interface.
Note: To interface OV7670 CMOS Camera with EDGE Board. Leave pin1 and pin2 unconnected. Connect pin3
of expansion connector to pin1 of CMOS Camera.

56. Major FPGA Design Software Suites
•Intel Quartus Prime:
A comprehensive tool for designing with Intel (formerly Altera) FPGAs, offering features
for design entry, simulation, synthesis, and place-and-route.
•AMD/Xilinx Vivado:
Provides an integrated development environment (IDE) for Xilinx FPGAs, featuring robust
capabilities for design, synthesis, simulation, and verification.
•Microchip Libero SoC:
Microchip Technology's development environment for its FPGAs and SoCs, integrating
tools for simulation, synthesis, and programming within a single platform.
•Lattice Radiant:
The software suite tailored for Lattice Semiconductor FPGAs, offering a user-friendly
interface with powerful design and verification features.

57. Key Supporting Software & Languages
•Hardware Description Languages (HDLs):
The core languages for defining FPGA logic include:
•Verilog:A widely used HDL that allows for hardware design and simulation.
•VHDL:Another powerful HDL used for describing hardware circuits, supporting
complex designs.
•SystemVerilog:An extension of Verilog that adds advanced features for design and
verification.
•SynthesisTools:
•Synplify:An industry-standard synthesis tool fromSynopsys, supporting multiple
HDL formats and FPGA vendors.
•SimulationTools:
•ModelSim:A popular simulation tool for modeling and verifying Verilog and VHDL
code.

58. Other Approaches:
•High-Level Synthesis (HLS):
Allows designers to use C, C++, or SystemC to describe
hardware, which is then synthesized into HDL, simplifying the
design process for certain applications.
•Python Frameworks:
Some vendors offer Python-based frameworks to program
FPGAs, especially for specific tasks like image processing.

59. Verilog Code for 4-Digit 7-Segment Display
module seven_segment_display(
input clk, // 50MHz clock
input reset, // Reset signal
input [15:0] data_in, // 16-bit input data (4 digits of 4-bits each)
output reg [6:0] seg, // 7-segment pattern (a-g)
output reg [3:0] digit // Digit select (active low for common anode) ); // Internal registers and wires
reg [1:0] digit_sel; // Digit selector counter
reg [3:0] bcd_data; // Current digit data
reg [19:0] refresh_counter; // Refresh counter for multiplexing
wire [3:0] digit_enable; // Digit enable signals // Clock divider for display refresh (approximately 1kHz
refresh rate)
always @(posedge clk or posedge reset)
begin if (reset) refresh_counter <= 0;
else refresh_counter <= refresh_counter + 1;
end

60. // Digit selector
(cycles through 0-3)
always @(posedge clk or posedge reset)
begin if (reset) digit_sel <= 0;
else if (refresh_counter == 0) // Update digit every refresh cycle
digit_sel <= digit_sel + 1; end // Multiplex the digit selection
assign digit_enable = ~(1 << digit_sel); // Active low for common anode // Digit
selection output
always @(*) begin digit = digit_enable;
end
// BCD data multiplexer - select which digit to display
always @(*) begin case (digit_sel) 2'b00:
bcd_data = data_in[3:0]; // Digit 0 (LSB)
2'b01: bcd_data = data_in[7:4]; // Digit 1
2'b10: bcd_data = data_in[11:8]; // Digit 2
2'b11: bcd_data = data_in[15:12]; // Digit 3 (MSB)
default: bcd_data = 4'b0000; endcase
end

61. // 7-segment decoder (active low for common anode)
always @(*) begin case (bcd_data) 4'b0000:
seg = 7'b1000000; // 0
4'b0001: seg = 7'b1111001; // 1
4'b0010: seg = 7'b0100100; // 2
4'b0011: seg = 7'b0110000; // 3
4'b0100: seg = 7'b0011001; // 4
4'b0101: seg = 7'b0010010; // 5
4'b0110: seg = 7'b0000010; // 6
4'b0111: seg = 7'b1111000; // 7
4'b1000: seg = 7'b0000000; // 8
4'b1001: seg = 7'b0010000; // 9
4'b1010: seg = 7'b0001000; // A
4'b1011: seg = 7'b0000011; // b
4'b1100: seg = 7'b1000110; // C
4'b1101: seg = 7'b0100001; // d
4'b1110: seg = 7'b0000110; // E
4'b1111: seg = 7'b0001110; // F
default: seg = 7'b1111111; // All off
Endcase
end
endmodule

62. Advantages of FPGAs
•Flexibility:FPGAs can be reprogrammed to perform different tasks or update the functionality of a device
after it has been deployed. This allows for modifications and improvements without needing to redesign the
hardware.
•Rapid Prototyping:Designers can quickly implement and test their designs on FPGAs, making them ideal for
prototyping and iterative development processes.
•Lower Initial Costs:For low to medium-volume productions, FPGAs generally have lower upfront costs
compared to developing an ASIC, as there are no expensive fabrication costs involved.
•Shorter Time to Market:Since FPGAs do not require a manufacturing process after design, they can
significantly reduce the time to market for new devices.

63. Advantages of FPGA
•• Parallel hardware execution for high performance.
•• Reconfigurable after deployment for updates and bug fixes.
•• Lower cost for prototypes and low volume production.
•• Accelerates time-to-market.

64. Challenges and Limitations
•• Higher power consumption compared to ASICs.
•• Larger physical size for equivalent logic.
•• Complex design and debugging process.
•• Security concerns with configuration bitstream exposure.

65. THANK YOU