Design of Superscalar Dual-Issue RISC-V Processor

This presentation introduces the Super RISC-V processor, created within my master's thesis at the Faculty of Information Technology of Brno University of Technology. It is a brand-new processor with clear ideas, created from scratch.

Processor source code: https://github.com/dominiksalvet/super-riscv
Full thesis text: https://www.vut.cz/en/students/final-thesis/detail/155087

1. Design of Superscalar
RISC-V Processor
Bc. Dominik Salvet
Supervisor: doc. Ing. Jiˇr´ı Jaroˇs, Ph.D.
June 20, 2024

2. Objectives of the Thesis
1Design and implement a 32-bit superscalar RISC-V
processor from scratch in
2Introduce the reader to the created microarchitecture and
its approaches
3Test and evaluate the implemented solutionIF1 IF2
IFU DEC
EXU 1
EXU 2
LSU
ID EX1 EX2 EX3 WB
ALU
ALU
Branch
Result
Design of Superscalar RISC-V Processor 2 / 10

3. Created Microarchitecture
•Dual-issue 7-stage pipeline with in-order execution
•Able to execute
•Partial support for AMBA 3
•Deterministic issue slot scheduling — why?ALU
PC
Instruction
Memory
+8
Decoder
AGU
Data
Memory
WB
Branch
Unit
F
o
r
w
a
r
d
EX3EX2EX1
Register
File
Forward
Control
ID
IFB
IF2IF1
ForwardForward Forward
Design of Superscalar RISC-V Processor 3 / 10

4. Used Resources by Instructions
•A processor issue slot must be able to execute
instruction per cycle→dedicated resources
Design of Superscalar RISC-V Processor 4 / 10

5. Instruction Fetch BufferInstruction
Memory
Two IFB Items
Instruction Packet
Write
Pointer
Read
Pointer
Push LogicPop Logic
Flush
Stall
Valid
Empty
Flag
Fetch
Enable
IF2 ID
•Store instructions while further stages stall
•Clean memory paths
Design of Superscalar RISC-V Processor 5 / 10

6. Two-Stage Operand Forwarding
•Processor supports complete operand forwarding
•It might be expensive→two-stage approachID EX1
EX2 EX3 WB
Control Paths
Data Paths
Register File
Second Phase
First Phase
value value value
addraddr
addr
Example instruction sequence:
•sub, x15, x21
or x12, x12,
Design of Superscalar RISC-V Processor 6 / 10

7. Created Testing EnvironmentVerilog/SV
Code
Verilator C++ Code
C++
Compiler
Executable
Simulator
•Make-based
•Uses Verilator, GTKWave, RISC-V GCC
•10 custom self-check RISC-V assembly programs
•Several assertion statements ensure more reliable processor
behavior
Design of Superscalar RISC-V Processor 7 / 10

8. Measured Average IPC Values
•The sumfast
the maximum processor performance potential
Design of Superscalar RISC-V Processor 8 / 10

9. Superscalar vs. Scalar Performance
Design of Superscalar RISC-V Processor 9 / 10

10. Thank You for Your Attention!
The main output of the work:
•Superscalar 32-bit RISC-V processor written in SystemVerilog
•Dual-issue 7-stage pipeline with in-order executionALU
PC
Instruction
Memory
+8
Decoder
AGU
Data
Memory
WB
Branch
Unit
F
o
r
w
a
r
d
EX3EX2EX1
Register
File
Forward
Control
ID
IFB
IF2IF1
ForwardForward Forward
Design of Superscalar RISC-V Processor 10 / 10

11. Opponent’s Questions (in Czech)
1V tabulce 5.2 na stranˇe 41 je coby jeden z prov´adˇen´ych
test˚u uvedena poloˇzka ”hazards”. M˚uˇzete pros´ım ve
struˇcnosti nast´ınit pozad´ı tohoto testu?
Design of Superscalar RISC-V Processor 1 / 7

12. Opponent’s Questions (in Czech)
2M˚uˇzete struˇcnˇe srovnat vlastnosti v´ami vytvoˇren´ehoˇreˇsen´ı
s architekturamiˇci j´adry jako Noel-Vˇci CVA6?
•Noel-V
•Highly configurable (32/64-bit, single/dual-issue, etc.)
•Always uses IMA extensions, user and machine modes
Design of Superscalar RISC-V Processor 2 / 7

13. Opponent’s Questions (in Czech)
2M˚uˇzete struˇcnˇe srovnat vlastnosti v´ami vytvoˇren´ehoˇreˇsen´ı
s architekturamiˇci j´adry jako Noel-Vˇci CVA6?
•CVA6
•Contains extensions and features to run operating systems
Design of Superscalar RISC-V Processor 3 / 7

14. Opponent’s Questions (in Czech)
3Lzeˇr´ıci,ˇze je v´ami vytvoˇren´eˇreˇsen´ı plnˇe pˇripraveno pro
synt´ezu do c´ılov´eho obvodu FPGA? Jak´e dodateˇcn´e
´upravy by eventu´alnˇe bylo nutn´e prov´est?RAM
DUAL PORT
Port A Port B
Instruction
Interface
Data
Interface
Design of Superscalar RISC-V Processor 4 / 7

15. Execution of Instructions in PipelineIF1 IF2
IFU DEC
EXU 1
EXU 2
LSU
ID EX1 EX2 EX3 WB
ALU
Branch
Result
1
2
3
4
5
6
7
8
9
10
11
12
1
24
3
5
7,89,1011,12
beqz x10, done (12)
lw x21, 0(x11)
lw x22, 0(x12)
addi x11, x11, 4
addi x12, x12, 4
slli x21, x21, 1
addi x10, x10, -1
add x23, x21, x22
sw x23, 0(x13)
addi x13, x13, 4
j next_loop (1)
...
ALU
6
Design of Superscalar RISC-V Processor 5 / 7

16. Example RISC-V Assembly Program
Design of Superscalar RISC-V Processor 6 / 7

17. Processor Simulation Open in GTKWave
Design of Superscalar RISC-V Processor 7 / 7