Device isolation Techniques

In MOS, source-drain regions of adjacent MOS transistors together with interconnection metal lines may constitute parasitic MOS transistors unless they are isolated from each other. Hence, each MOSFET must be electrically isolated from each other. Device Isolation Techniques in VLSI microfabrication of MOS are discussed.

1. Device Isolation Techniques Sudhanshu Janwadkar TA, ECED, SVNIT

2. Objectives To understand what is device isolation To appreciate the need for device isolation in micro-fabrication To study the various device isolation techniques, and To identify merits and demerits of each

3. Device Isolation Techniques VLSI consists of several active and passive components interconnected within a monolithic block of semiconductor material. Each component must be electrically isolated from each other to allow design flexibility . In MOS, source-drain regions of adjacent MOS transistors together with interconnection metal lines may constitute parasitic MOS transistors unless they are isolated from each other. What is the need for Device Isolation?

4. 4 Device Isolation is also necessary: To prevent undesired conducting paths; To avoid creation of inversion layers outside the channels; To reduce leakage currents. Device Isolation Techniques What is the need for Device Isolation?

5. Device Isolation Techniques Junction Isolation Technique Dielectric Isolation Technique – Etched Field oxide Isolation LOCOS Trench Isolation Technique – STI

6. Junction Isolation Technique In older day bipolar junction transistor technology, the isolation was provided by a deep PN junctions <= Junction isolation technique The reverse biased pn junction would act as the electrical isolation between adjacent devices.

7. Junction Isolation Technique Demerits: As the device dimensions were reduced and as we wanted faster and faster devices, junction isolation became non-viable technology, because : the diffusion will always have some lateral spread; therefore, as the device dimensions become smaller, it becomes more difficult to control the isolation tub width and the capacitance associated with these junction s, hinders the speed of the transistors

8. Dielectric Isolation Technique The most common dielectric, silicon dioxide is used for isolation. Etched Field oxide Isolation LOCOS

9. Etched Field oxide Isolation Devices are created in dedicated regions called active areas. Each active area is surrounded by thick oxide barrier called field oxide . Thick oxide is grown on complete surface of the chip and then selectively etched to define active areas. Thickness of oxide leads to large oxide steps at the boundaries of active areas and isolation region .

10. LOCOS Technique LOCOS = local oxidation of Silicon Local oxidation that is oxidation is carried out at some regions of the semiconductor; the other regions are prevented from getting oxidized by using a silicon nitride mask. Silicon nitride has an interesting behavior that it does not allow oxidation to proceed underneath. This has been used in LOCOS.

11. The active region is protected by a depositing a layer of silicon nitride -> Acts as oxide barrier Underneath, there is a layer of thin oxide called pad oxide. Pad oxide is needed because otherwise silicon nitride will not adhere very well to the silicon. There will be lot of stress induced. By depositing the silicon nitride on top of the pad oxide, the stress will be reduced. LOCOS Technique 1

12. The pattern transfer is performed by photolithography. After lithography the pattern is etched into the nitride. The active areas for the oxidation process are thus defined LOCOS Technique 2

13. The next step is the main part of the LOCOS process, the growth of the thermal oxide. 3 LOCOS Technique

14. After the oxidation process is finished, the last step is the removal of the nitride layer. 4 LOCOS Technique

15. The advantages of LOCOS fabrication are: the simple process flow and the high oxide quality, because the whole LOCOS structure is thermally grown. LOCOS Technique - Merits

16. But, as the device dimensions went on becoming smaller, the LOCOS technique also started to show its limitation and what are these limitations? Bird’s Beak Problem LOCOS Technique - Demerits

17. There will be a little bit of encroachment of oxide underneath silicon nitride. This is because oxidation is proceeding not merely in the, on the horizontal surface , but also at the vertical side walls. The slight encroachment under the silicon nitride is shaped like a bird’s beak., hence this is called bird's beak problem. As we reduce the device dimensions i.e If this entire active transistor area itself is very small, then even a small encroachment will be a considerable percentage of the total active area. LOCOS Technique - Demerits

18. Trench Isolation Technique In a trench isolation, A trench is cut in the semiconductor and then the trench is filled with non-conducting material. In shallow trench isolation, instead of thermally growing oxide layer, the silicon dioxide layer is deposited by CVD.

19. Shallow Trench Isolation Technique Step 1: Nitride deposition In the shallow trench isolation process, at first a thin layer of oxide is grown by thermal process and subsequently a thin layer of silicon nitride is deposited by CVD .

20. Step 2. Create a Trench Using photo lithography and etching, wherever electrical isolation is needed, a trench is made in silicon (i.e. the silicon nitride, silicon dioxide and then Si are removed by dry etching in those areas). Shallow Trench Isolation Technique

21. Step 3: Trench Oxide Deposition Then silicon dioxide of sufficient thickness is deposited by CVD. Usually this is done under high density plasma (HDP) conditions.  Shallow Trench Isolation Technique

22. Step 4: Chemical Mechanical Planarisation In the next step, the excess oxide is removed by chemical mechanical planarization. Here, care must be taken to ensure that only the oxide is removed and the nitride is not removed. Shallow Trench Isolation Technique

23. Step 5:Nitride removal Then the nitride is removed by wet etching using phosphoric acid . Shallow Trench Isolation Technique

24. Shallow Trench Isolation Technique