dien-tu-tuong-tu_pham-nguyen-thanh-loan_chapter-3-_fet - [cuuduongthancong.com].pdf

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1. CHAPTER 3:
TRANSISTOR MOSFET
DR. PHAM NGUYENTHANHLOAN
Hà Nội, 9/24/2012
1

2. Chapter 3: MOSFET
Introduction
Classifications
JFET
D-FET (Depletion MOS)
MOSFET (Enhancement E-FET)
DC biasing
Small signal analysis
Equivalent small signal circuit
2

3. FET Introduction
High input impedance, nMΩ-n100MΩ
Controlled by voltage (≠ BJT)
Low power consumption
Low noise, suitable for small signal
Low impact of temperature
Using as switch for low power application
Small size and adapt for integrated circuit
3

4. Classification
JFET-Junction Field Effect Transistor
N and P channels
MOSFET-Metal Oxide Semiconductor FET
Depletion MOS
N and P channels
Enhancement MOS
N and P channels
4

5. Classification (cont’d)
JFET D-FET E-FET (MOSFET)
5

6. JFET
Structure and Operation
Characteristic Curve
Compare with BJT
Examples, datasheets
6

7. JFET –Structure
7

8. JFET –Operation
V
GS = 0, V
DS>0 increase gradually, I
Dincreases and then saturates
8

9. JFET –Operation
V
GS = 0, V
DS = V
P, I
D= I
DSS
V
P: pinch off voltage (pinch-off)
I
D = I
DSS(1 -V
GS/V
P)
2
9

10. JFET –Operation
V
GS < 0, V
DS > 0, Saturation current reduces when V
GS V
pinch-off
V
GS= V
P, I
D= 0
10

11. JFET –Characteristic Curves
I
D= f(V
GS) Shockley equation:
I
G ≈ 0A (gate current)
I
D = I
S (I
D drain current, I
Ssource current)
11
I
D = I
DSS(1 -V
GS/V
P)
2

12. JFET –Characteristic Curves
P-channel, I
DSS = 6mA, V
P = 6V
N-channel, I
DSS = 8mA, V
P = -4V
12

13. JFET –Symbol
13

14. JFET
2N5457
14

15. Datasheet-2N5457
Rating Symbol ValueUnit
Drain-Source voltage V
DS 25 Vdc
Drain-Gate voltage V
DG 25 Vdc
Reverse G-S voltage V
GSR -25 Vdc
Gate current I
G 10 nAdc
Device dissipation 25
0
C
Derate above 25
0
C
P
D 310
2.82
mW
mW/
0
C
Junction temp range T
J 125
0
C
Storage channel temp rangeT
stg -60 to
+150
0
C
15

16. Datasheet-2N5457-characteristics
Characteristic SymbolMinTypMaxUnit
V
G-S breakdown V
(BR)GSS-25 Vdc
I
gate reverse(Vgs=-15, Vds=0)I
GSS -1.0nAdc
V
G-S cutoff V
GS(off)-0.5 -1.0Vdc
V
G-S V
GS -2.5-6.0Vdc
I
D-zero gate volage I
DSS 1.03.05.0mAdc
C
in C
iss 4.57.0pF
C
reverse transfer C
rss 1.53.0pF
16

17. MOSFET
Structures
Operation
Characteristic Curves
17

18. MOSFET –Structure
N-channel Enhancement EMOSN-channel Depletion DMOS
18

19. MOSFET –Operation
N-channel EMOS
V
GS > V
TH, V
DS > 0
N-channel DMOS
V
GS = 0, V
DS > 0
19

20. DMOS–Transfer characteristic curves
Similar to JFET, transfer characteristic curve I
D= f(V
GS)
follows Shockley equation: I
D= I
DSS(1 -V
GS/V
P)
2
Can work at: V
GS> 0, I
D> 0
20

21. EMOS–Transfer characteristic curve
Transfer characteristic curve:
I
D= k(V
GS–V
T)
2
with V
T > 0 (for NMOS) and Vt< 0 for PMOS)
When V
GS< V
T, I
D= 0
21

22. MOSFET –Transfer characteristic curve
P-channel depletion
22

23. MOSFET –Transfer characteristic curve
P-channel enhancement
23

24. MOSFET –Symbol
EMOSDMOS
24

25. EMOS
2N4351
25

26. Datasheet-2N4351-EMOS
Characteristic SymbolMinMax Unit
V
DS breakdown V
(BR)DSX25 Vdc
I
D-zero gate volage,
Vds=10V,Vgs=0, 25C –150C
I
DSS 10
10
nAdc
µAdc
I
gate reverse(Vgs=+-15, Vds=0) I
GSS +-10nAdc
V
DS on Voltage V
DS(on) 1.0 V
C
in(Vds=10V,Id=2mA,f=140kHz) C
iss 5.0 pF
C
DS(Vdsub=10V,f=140KHz) C
rss 5.0 pF
R
DS(Vgs=10V,Id=0,f=1KHz) R
ds(on) 300ohms
26

27. VMOS
VMOS –Vertical MOSFET, increase channel lenght
Increase drain current thanks to large space of heat release
High switching speed
27

28. CMOS
CMOS=Complementary MOSFET
pMOS và nMOS: fabricated on same wafer
Reduce size and power consumption, increase switching speed
Analog/Digital IC design
28

29. Resume
JFET
DFET
MOSFET
29

30. Biasing types
Fixed bias
Self-biasing
Voltage divider biasing
Feedback biasing
30

31. Some noted
With all kinds of FET:
I
G= 0A
I
D= I
S
For JFET& D-MOSFET:
I
D= I
DSS(1 –V
GS/V
P)
2
For E-MOSFET(MOSFET):
I
D= k(V
GS–V
T)
2
(saturation mode)
Determine Q-point (DC operating point) and DC load line
31

32. Fix biasing (ex: JFET)
I
G= 0A
V
S= 0
V
GS= V
G= -V
GG
I
D = I
DSS(1-V
GS/V
p)
2
V
Gis fixed at V
GG
32

33. Fix biasing
I
D = I
DSS(1-V
GS/V
P)
2
Build transfer characteristic
curve from this table:
V
GS I
D
0 I
DSS
0.3V
P I
DSS/2
0.5Vp I
DSS/4
V
P 0mA
DC load line:
V
GS= -V
GG
Intersection between DC load
line and trans. Charact. Curve
Q point
33

34. Temperature effect
Leakage current I
GSSincreases
when t0 increases cannot
neglect RGat mentioned
previouslyso:
Q will move from :
V
GS= V
GG+ I
GSS*R
G
new Q-point
34

35. Impact of temperature
Question: If V
GG=-1V& R
G=1 MΩ. I
GSS=1nA at 25°C and increase
double when temperature increases 10
o
C. Determine V
GSat 125
o
C ?
35

36. new Q-point
Answer:
At 25
o
C, I
GSS×R
G=10
-9
×10
6
= 1mV, can
be neglected when compare with V
GG= -
1V (or new V
GS= -999mV).
Q point at 125
0
C is shifted to a new
point and it is far from the initial Q
point at room temperature
36
Question: If V
GG=-1V& R
G=1 MΩ.
I
GSS=1nA at 25°C and increase double when
temperature increases 10
o
C. Determine V
GS
at 125
o
C ?
When Temp. increases to 125
o
C, current
I
GSSincreases to 2
10
times ( ≈10
3
)
I
GSS= 10
3
×1nA =1µA
I
GSS×R
G=1µA* 1MOhm = 1V
New Q point: V
GS= 0V & I
D = I
DSS
Impact of temperature

37. Self biasing
What is the main difference compared to fixed biasing?
Role of R
S?
Remove R
Gto reduce impact of temperature?
38

38. Self-biasing
Loop at input:
I
G= 0 => V
G= 0V V
GS= -I
SR
S (1)
I
D = I
DSS(1-V
GS/V
p)
2
(2)
To determine Q point:
Sole the equation system: (1) + (2)
Or by using curve method as
shown in the paragraph (intersection
point)
Consider the impact of Temp.?
39

39. Voltage divider biasing (ex: JFET)
I
G= 0, output current I
D is controlled by V
GS
This biasing method is usually used for FET
40

40. Voltage divider biasing (ex: JFET)
V
G = V
DDR
2/(R
1+R
2)
DC load line is: V
GS = V
G-I
DR
S(1)
R
Svaries shift of Q point and DC
load line
Characteristic curve of FET
I
D = I
DSS(1-V
GS/V
P)
2
, (2)
To determine Q point:
Sole the equation system: (1)+(2)
Or by using curve method as
shown in the paragraph (intersection
point)
41

41. V
G= V
DD* 10MΩ/(110MΩ+10MΩ)
DC load line: V
GS= V
G–I
S*750Ω(1)
I
Dcurrent of DMOS:
I
D = I
DSS(1-V
GS/V
P)
2
(2)
To determine Q point:
Sole the equation system: (1) +
(2)
Or by using curve method as
shown in the paragraph (intersection
point)
42
Voltage divider biasing (ex: DMOSFET)

42. With DMOS: I
D = I
DSS(1-V
GS/V
P)
2
V
GScan be positive
43
Voltage divider biasing (ex: DMOSFET)

43. With EMOS:
I
D = k(V
GS-V
T)
2
k=I
Don/(V
GSon-V
T)
2
44
Voltage divider biasing (E-MOSFET)

44. With EMOS: I
D = k(V
GS-V
T)
2
where k = I
D-on/(V
GSon-V
T)
2
Draw transfer characteristic
curve of E-MOSFET
45
Voltage divider biasing (ex: E-MOSFET)

45. Feedback biasing (ex: E-MOSFET)
At the node G:
I
G= 0 V
G= V
D
46


46. At the node G: I
G= 0 => V
G=
V
D
DC load line
V
GS= V
DS= V
DD -R
DI
D (1)
Transfer char. equation:
I
D = k(V
GS -V
T)
2
, (2)
k = I
Don/(V
GSon-V
T)
2
Solve equ. Sys. (1,2) or use
paragraph method
47
Feedback biasing (ex: E-MOSFET)

47. Example
Question: Determine Q (I
D, V
GS) point Q of these circuits?
48

48. Example
49
Question: Determine Q (I
D, V
GS) point Q of these circuits?

49. Example
50
Question:DetermineV
GSand
V
DSfortheE-MOSFETcircuit
above.Giventhatthis
MOSFEThasminimumvalues
ofI
D(on)=200mAatV
GS=4V
andV
th=2V.
Question:DetermineI
Dwith
V
th=3V.

50. Analyze the circuit for AC signal
(small signal)
51

51. Small signal model
52

52. Transconductance
g
m= ∆I
D/ ∆V
GS= d(I
D(V
GS))
Derivation of current I
Das
function of V
GS
Slope of I
D(V
GS) at Q point
53

53. Transconductance g
m (JFET & DMOS)






P
GS
P
DSS
m
V
V
1
V
2I
g
For E-MOS; gm is defined from Shockley equation:
When V
GS= 0:
g
mdetermined at Q point: P
DSS
m0
V
2I
g 






P
GS
m0m
V
V
1gg
54

54. Transconductance g
m (E-MOSFET)
For JFET & DMOS, gm is defined from:
g
mdetermined at Q point:
55

55. Notes:
V
GSshould be positive for NMOS and negative for PMOS
g
m= 2k(V
GS–V
T)
AC equivalent circuit (EMOS)
56

56. 3 types of MOSFET amplifier
57
CS –CD -CG

57. EMOS –CS with fixed bias voltage
58Cout
Vout
Vin
Cin
+
V1
10V
VDD
RG
RD
N-EMOS
Input at G terminal, output at D
terminal Common Source
Fixed biasing (S grounded)
To draw AC equivalent circuit
Short circuit all capacitors
Short circuit power supply
AC equivalent
circuit

58. Z
i= R
G
Z
o= r
d//R
D ≈ R
D if r
d> 10R
D
A
V= -g
m(r
D//R
D) ≈ -g
mR
Dif r
d> 10R
D
Input and output voltage are out of phase
EMOS –CS with fixed bias voltage
59

59. EMOS –CS with voltage divider
60
Input at G terminal, output at D
terminal Common Source
Voltage divider
S terminal is connected to Rs and Cs
in parralelG
D
S
C1
1uF
R1
Cs
RS
Cout
Vout
Vin
VDD
R2
RD
N-EMOS
AC equivalent
circuit

60. EMOS –CS with voltage divider
Z
i= R
1// R
2
Z
o= r
d//R
D ≈ R
D nếur
d> 10R
D
A
V= -g
m(r
D//R
D) ≈ g
mR
D nếur
d> 10R
D
Input and output voltage are out of phase
61

61. EMOS –CS with voltage divider and wo. Cs
62
Input at G terminal, output at D
terminal Common Source
Voltage divider
S terminal is connected to ONLY Rs
and REMOVE bypass-capacitor C
SG
D
S
C1
1uF
R1
Cs
RS
Cout
Vout
Vin
VDD
R2
RD
N-EMOS
AC equivalent
circuit
X
?????

62. EMOS –CS with voltage divider and wo. Cs
63
Input at G terminal, output at D
terminal Common Source
Voltage divider
S terminal is connected to ONLY Rs
and REMOVE bypass-capacitor C
SG
D
S
C1
1uF
R1
Cs
RS
Cout
Vout
Vin
VDD
R2
RD
N-EMOS
AC equivalent
circuit
X

63. EMOS –CS with voltage divider and wo. Cs
Z
i= R
G (or R1//R2)
Z
o= R
D/[1+g
mR
S+(R
D+R
S)/r
d]
A
V= -g
mR
D/[1+g
mR
S+(R
D+R
S)/r
d]
Input and output voltage are out of phase
64

64. EMOS –CS with feedback bias
Input at G terminal, output at D
terminal: Common Source
Feedback biasing
To draw AC equivalent circuit
Short circuit all capacitors
Short circuit power supply
65

65. EMOS –CS with feedback bias
66
AC equivalent circuit
Short circuit all capacitors
Short circuit power supply


66. EMOS –CS with feedback bias
Z
i=(R
F+r
d//R
D)/[1+g
m(r
d//R
D)]
≈ R
F/(1+g
mR
D)with r
d>10R
D, R
F>>r
d//R
D
Z
o= R
F//r
d//R
D ≈ R
D with r
d>10R
D, R
F>>r
d//R
D
A
V = g
mR
F//r
d//R
D≈ g
mR
Dwith r
d>10R
D, R
F>>r
d//R
D
Output and input voltage are out of phase
67

67. EMOS –CS with feedback bias
68

68. 69
EMOS –CS with feedback bias

69. 70
EMOS –CS with feedback bias

70. JFET –CD with fixed biasing
Input at G terminal, output at
S terminal: Common Drain
Fixed biasing
71

71. Z
i= R
G
Z
o= r
d//R
S//(1/g
m) ≈ R
S//(1/g
m) if r
d> 10R
S
A
V= -g
m(r
d//R
S)/[1+g
m(r
d//R
S)] ≈ g
mR
S/[1+g
mR
S)] if r
d> 10R
S
≈ 1 if g
mR
S>> 1
72
JFET –CD with fixed biasing

72. JFET –CG with fixed biasing
Input at S terminal, output at D terminal:
Common GATE
Fixed biasing
73

73. JFET –CG with fixed biasing
Z
i = R
s//[(r
d+R
D)/(1+g
mr
d)]≈ R
S//(1/g
m)nếu r
d>10R
D
Z
o = r
d//R
D ≈ R
D nếu r
d>10R
D
A
V = [g
mR
D+ (R
D/r
d)]/[1+ R
D/r
d] ≈ g
mR
D nếu r
d>10R
D
Input and output voltage are IN-PHASE
74

74. Equivalent circuit for DMOS
Similar to JFET and E-MOSFET
For DMOS:
V
GScan be positive for Nchannel and negative for P channel
g
mcan be higher than g
m0
76

75. Resume
77

76. Resume
78

77. Exercises
Chapter 5: 3, 5, 6, 9, 26, 34, 37
Chapter 6: 1, 6, 12, 17, 19, 21, 23
Chapter 9: 1, 5, 12, 17, 19, 23, 27, 32, 33, 37, 38,
43, 44
79