Digital IC TTL AND CMOS voltage level and power Consumption.pptx

Digital ic notes

1. TTL (Transistor-Transistor Logic) TTL 74xx Series ICs Characteristics: Technology: Based on bipolar junction transistors (BJTs). Voltage Levels: Typically operate at a 5V power supply. Speed: Generally faster switching times compared to CMOS, with propagation delays in the range of a few nanoseconds. Power Consumption: Higher power consumption, especially when switching states. Noise Margin: Lower noise margin, making them less immune to electrical noise.

2. Popular Sub-Families in TTL 74LSxx (Low Power Schottky ): Lower power consumption and faster than standard TTL. 74ALSxx (Advanced Low Power Schottky ): Even lower power consumption and faster switching than 74LSxx. 74Fxx (Fast): Optimized for speed, with very low propagation delays.

3. Example ICs: 74LS00: Quad 2-input NAND gate. 74LS74: Dual D-type positive edge-triggered flip-flop. 74LS138: 3-to-8 line decoder.

4. CMOS 40xx Series ICs Characteristics: Technology: Based on MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Voltage Levels: Can operate over a wide range of supply voltages (3V to 15V). Speed: Slower switching times compared to TTL, with propagation delays in the range of tens to hundreds of nanoseconds. Power Consumption: Very low power consumption, especially in static conditions (when not switching states). Noise Margin: Higher noise margin, making them more immune to electrical noise.

5. Example ICs: CD4011: Quad 2-input NAND gate. CD4020: 14-stage binary ripple counter. CD4060: 14-stage ripple-carry binary counter/divider and oscillator. Popular Sub-Families in CMOS CD4000 series: Standard CMOS logic family. 74HCxx (High-Speed CMOS): Combines the low power consumption of CMOS with the speed of TTL.

6. Comparison Power Consumption: TTL: Higher, due to continuous current flow in the transistor junctions. CMOS: Lower, with negligible power consumption in the static state. Speed: TTL: Generally faster due to lower propagation delays. CMOS: Slower, but high-speed CMOS variants (like 74HCxx) can be competitive. Voltage Range: TTL: Typically fixed at 5V. CMOS: Flexible, ranging from 3V to 15V, making it suitable for a variety of applications. Noise Immunity: TTL: Lower, more susceptible to noise. CMOS: Higher, making them suitable for noisy environments.

7. Feature TTL 74xx CMOS 40xx Power Consumption Higher Lower Speed Faster Slower Voltage Range Typically 5V 3V to 15V Noise Immunity Lower Higher able:

8. 74LS138 Pin Configuration Pin1 (A): Address input pin Pin2 (B): Address input pin Pin3 (C): Address input pin Pin4 (G2A): Active low enable pin Pin5 (G2B): Active low enable pin Pin6 (G1): Active high enable pin Pin7 (Y7): Output pin Pin8 (GND): Ground pin Pin9 (Y6): Output pin 6 Pin10 (Y5): Output pin 5 Pin11 (Y4): Output pin 4 Pin12 (Y3): Output pin 3 Pin13 (Y2): Output pin 2 Pin14 (Y1): Output pin 1 Pin15 (Y0): Output pin 0 Pin16 (VCC): Power supply pin IC 74 LS 138 (3 to 8 decoder with active low outputs)

9. 74LS138(3 to 8 decoder)

10. 74LS138(3 to 8 decoder)

11. 4 to 16 decoder using 3 to 8 decoder(74 LS138 IC)

12. 5 to decoder using 2 to 4 decoder(74 LS139 IC) and 3:8 decoder(74 LS 138 IC)

13. Full adder using 3 to 8 decoder

14. 2 to 4 Decoder IC

15. 4 to 16 Decoder

16. 4 to 16 Decoder

17. 4 to 16 Decoder

18. 74 LS 47/74 LS 46 BCD to Seven Segment Decoder /Driver

19. BCD to Common cathode 7 segment decoder

20. Segment (LED) a

21. Segment (LED) b

22. Segment (LED) c

23. Segment (LED) d

24. Segment (LED) e

25. Segment (LED) g

26. Segment (LED) f

27. Common Cathode seven segment Decoder

28. BCD to Seven Segment Decoder /Driver

29. 4-to-2 Bit Binary Encoder

30. 4 to 2 priority encoder

31. 74 LS 148 priority encoder

32. 74 LS 148 priority encoder

33. 74 LS 151( 8 to 1 Multiplexer)

34. 74 LS 151( 8 to 1 Multiplexer)

35. De-multiplexer A De-multiplexer is a combinational circuit that has only 1 input line and 2 N  output lines. On the basis of the values of the selection lines, the input will be connected to one of these outputs.  There are n selection lines and 2 n  outputs. 

36. 1×2 De-multiplexer

37. 1×4 De-multiplexer

38. 1×4 De-multiplexer

39. 1×8 De-multiplexer

40. 1×8 De-multiplexer

41. 1×8 De-multiplexer

42. 1 x 16 De-multiplexer

43. 1 x 16 De-multiplexer

44. 1 x 16 De-multiplexer

45. 1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer

46. 74 LS 154 (1 to 16 demultiplexer )

47. 74 LS 154 (1 to 16 demultiplexer ) Truth table

48. 74 LS 154 (1 to 16 demultiplexer )

49. Full Adder

50. Full Adder

51. Full Adder using Half Adders

52. Full Adder using Half Adders

53. Full Adder using Half Adders P i  = A i  ⊕ B i Gi = Ai Bi Si = Pi ⊕ Ci C i +1 = Gi + Pi Ci

54. Using the Gi and Pi terms the Sum Si and Carry Ci+1 are given as below – Si = Pi ⊕ Ci . Ci+1 = Ci.Pi + Gi . Therefore, the carry bits C1, C2, C3, and C4 can be calculated as C1 = C0.P0+G0. C2 = C1.P1+G1 = ( C0.P0+G0).P1+G1. C3 = C2.P2+G2 = (C1.P1+G1).P2+G2. C4 = C3.P3+G3 = C0.P0.P1.P2.P3 + P3.P2.P1.G0 + P3.P2.G1 + G2.P3 + G3. Carry Look Ahead Adder

55. Carry Look Ahead Adder

56. Carry-Output-Generation-Circuit-of-Carry-Look-ahead-Adder

57. Carry-Output-Generation-Circuit-of-Carry-Look-ahead-Adder

58. IC 74182 Carry look Generator The IC for carry lookahead generator is IC 74182 where it accepts Po, P1, P2, and P3 as carry propagate bits in active low condition and Go, G1, G2, and G3 as carry generate bits and Cn bit as active high input. The active high input pin generates high carriers ( Cn+x , Cn+y , Cn+z ) at all the stages of  binary adders .

59. 4 bit Carry Look ahead adder

60. 4 bit Carry Look ahead adder

61. 4 bit Carry Look ahead adder

62. 4 bit parallel Binary adder(Carry look ahead adder)

63. 4 bit parallel Binary adder(Carry look ahead adder)

64. 4 bit parallel Binary adder(Carry look ahead adder)

65. Magnitude Comparator in Digital Logic

66. 1-bit Comparator

67. 4-Bit Magnitude Comparator In a 4-bit comparator, the condition of A>B can be possible in the following four cases. If A3 = 1 and B3 = 0 If A3 = B3 and A2 = 1 and B2 = 0 If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0 If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0

68. Similarly, the condition for A<B can be possible in the following four cases. If A3 = 0 and B3 = 1 If A3 = B3 and A2 = 0 and B2 = 1 If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1 If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1 4-Bit Magnitude Comparator

69. 4 Bit Magnetude Comparator

70. 4 Bit Magnetude Comparator

71. 4 Bit Magnetude Comparator

72. 4 Bit Magnetude Comparator(74 LS85)

73. Pin No Pin Name Description 1 B3 Data Input B3 2 I (A<B) Cascading Input (A<B) 3 I (A=B) Cascading Input (A=B) 4 I (A>B) Cascading Input (A>B) 5 O (A<B) Output pin (A<B) 6 O(A=B) Output pin (A=B) 7 O(A>B) Output pin (A>B) 8 GND Ground Pin 9 B0 Data Input B0 10 A0 Data Input A0 11 B1 Data Input B1 12 A1 Data Input A1 13 A2 Data Input A2 14 B2 Data Input B2 15 A3 Data Input A3 16 VCC Supply Voltage

74. D Flip Flop (IC 7474)

75. IC 7476(Dual JK master slave flip flop

76. Flip-flop is a 1 bit memory cell which can be used for storing the digital data. Group of flip-flop is known as a  Register . The  n-bit register  will consist of  n  number of flip-flop and it is capable of storing an  n-bit  word . The binary data in a register can be moved within the register from one flip-flop to another. The registers that allow such data transfers are called as  shift registers . There are four mode of operations of a shift register .

77. Serial Input Serial Output Serial Input Parallel Output Parallel Input Serial Output Parallel Input Parallel Output

78. Serial Input Serial Output

79. Serial Input Parallel Output

80. Parallel Input Serial Output (PISO) When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active. Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus the parallel in serial out operation takes place.

81. Parallel Input Parallel Output (PIPO)

82. Bidirectional Shift Register If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2. Hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction. There are two serial inputs namely the serial right shift data input DR, and the serial left shift data input DL along with a mode select input (M).

83. Bidirectional Shift Register

84. . Condition Operation 1 With M = 1 − Shift right operation If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the remaining AND gates 2, 4, 6 and 8 will be disabled. The data at D R  is shifted to right bit by bit from FF-3 to FF-0 on the application of clock pulses. Thus with M = 1 we get the serial right shift operation. 2 With M = 0 − Shift left operation When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7 are disabled. The data at D L  is shifted left bit by bit from FF-0 to FF-3 on the application of clock pulses. Thus with M = 0 we get the serial right shift operation. Bidirectional Shift Register

85. A shift register which can shift the data in both directions as well as load it parallely , is known as a universal shift register. The shift register is capable of performing the following operation − Parallel loading Left Shifting Right shifting Universal Shift Register

86. The mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0 for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bi-directional register. For serial left operation, the input is applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right operation, the serial input is applied to D input. Universal Shift Register

87. Universal Shift Register

88. Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter. Counters are of two types. Asynchronous or ripple counters. Synchronous counters. Counters

89. Asynchronous or ripple counters

90. 4 bit synchronous up/down counter:  This counter has two modes of counting i.e. up counting and down counting. There is a mode switch which switches between the two modes of the counter. When the mode M = 0 it counts up & when mode M = 1 then it counts down.

91. 4 bit synchronous up/down counter:  This counter has two modes of counting i.e. up counting and down counting. There is a mode switch which switches between the two modes of the counter. When the mode M = 0 it counts up & when mode M = 1 then it counts down.