DIGITAL PRINCIPLES AND SYSTEM DESIGN LAB MANUAL

DSD Lab Manual

1. DIGITAL
PRINCIPLES AND
SYSTEM DESIGN

LAB MANUAL


Prepared by
S. CAROLINE,
AP/ ECE

3. Ex.No:1 Date:__/__/____


VERIFICATION OF BOOLEAN THEOREMS USING BASIC GATES

AIM:

To study the operation of the given logic gates and to verify the truth table.

COMPONENTS REQUIRED:


SL.NO

NAME OF THE COMPONENT

RANGE

QUANTITY
1 NAND gate IC 7400 1
2 NOR gate IC 7402 1
3 AND gate IC 7408 1
4 OR gate IC 7432 1
5 NOT gate IC 7404 1
6 EX-OR gate IC 7486 1
7 Breadboard 1
8 Power supply +5v 1
9 Connecting wires As required


THEORY:

(i) AND gate(IC 7408):

AND gate has two or more inputs and only one output. The output is high if all inputs
are high. Its logic equation Y=A.B


(ii) OR gate(IC 7432):

OR gate has two or more inputs and one output. The output is high if any one input is high.
Its logic equation is Y=A+B

4. (iii) NOT gate(IC 7404):

NOT gate has only one input and one output. The output is the complement of input. Its
logic equation is Y=A’



(iv) NOR gate(IC 7402):

NOR gate has two or more inputs and one output. If any input is high output is low. It is a
combination of NOT and OR gate. Its logic equation is Y=(A+B)’

(v) NAND gate(IC 7400):

NAND gate has two or more inputs and single output. If any input is low the output is
high. It is a combination of AND and NOT gate. Its logic equation is Y= (A.B)’

5. (vi) EX-OR (Exclusive OR) gate (IC7486):

EX-OR gate has two or more inputs and single output. If two inputs are different, then the
output is high. Its logic equation is Y = A’B+AB’== A B


(vii) De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual complements.

(A+B)’ = A’.B’

6. 2. The complement of the product is equal to the sum of the individual complements.

(A.B)’ = A’+B’

PROCEDURE:
(i) Connection are made as per circuit diagram.
(ii) The high state is indicated by connecting input to Vcc and low to ground.
(iii) Different combination of input are given and corresponding outputs are noted
on the LED display.
(iv) When LED is ON it indicates one and when it is OFF it indicates zero.


RESULT:

Thus the operations of basic logic gates were studied successfully.

7. Ex.No:2 Date:__/__/ ____


CODE CONVERTERS


AIM:

To design and setup the following circuits.
(i) A four bit binary to gray code converter.
(ii) A four bit Gray to binary code converter.

COMPONENTS REQUIRED :


SL.NO

NAME OF THE COMPONENT

RANGE

QUANTITY
1 EX-OR gate IC 7486 3
2 Digital lab trainer 1
3 Power supply +5v 1
4 Connecting wires As required

THEORY:

Any discrete element of information distinct among a group of quantities can be
represented by a binary code. Binary codes play an important role in digital computers. The
codes must be in binary as computers can hold only 0’s and 1’s.If the bits of the computer are
inspected in random, they represent some binary coded information rather than binary numbers.

Digital systems can process data in discrete form only, but many physical systems
supply continuous data output, which must be converted to digital form before they are applied
to digital systems. In such a situation it is convenient to use gray code to represent digital data.
The advantage of Gray code over binary numbers is that only one bit in the code group changes
when going from one number to the next.

11. PROCEDURE:

1) Connections are made as per the circuit diagram.
2) Verify truth table by feeding various input bit combinations.




RESULT:
Thus the circuits are designed and outputs are verified successfully.

12. Ex.No:3 Date:__/__/ ____


HALF ADDER AND FULL ADDER


AIM:

To construct and verify the adder circuit using logic gates.

COMPONENTS REQUIRED :


SL.NO

NAME OF THE COMPONENT

RANGE

QUANTITY
1 EX-OR gate IC 7486 1
2 AND gate IC 7408 1
3 OR gate IC 7432 1
4 Digital lab trainer 1
5 Power supply +5v 1
6 Connecting wires

As required
Characteristic equation:

For Half adder,
Sum, S= x’y + xy’=x y

Carry, C= xy
For Full adder,
Sum, S = x’y’z + x’yz’ + xy’z +xyz
= x y z

Carry, C= x’yz + xy’z + xyz’ +xyz
=z(x y) +xy

THEORY:

The most basic arithmetic equation is the addition of two binary digits, when it
involves digital computers. The simple addition consists of four possible elementary operations
namely,0+0=0,0+1=1,1+0=1 and 1+1=10.The first three operations produce a sum with one digit
but when augend and addend bits are equal to one, the binary sum consists of two digits , of
which the higher significant bit is called carry.
The combinational circuit that performs the addition of two bits is called a half-adder. One
that performs the addition of three bits (two significant bits and previous carry) is called a full-
adder. Two half-adders can be employed to implement a full-adder.

13. Half-adder:

It has two binary inputs and two binary outputs. The input variable designates the augend
and addend bits, the output variables produce the sum and carry. It is necessary to
specify two outputs because result may contain two binary digits. The simplified Boolean
functions for the two outputs can be obtained from the truth table as,
s= x’y+xy’= x

c= xy

Full adder:

It consists of three inputs and two outputs. Two of the input variables are denoted by x
and y .They represent the two significant bits to be added. The third input z represents the carry
from the previous lower significant position. Two outputs are needed as the sum of three bits
ranges in value from 0 to 3, and binary 2 or 3 needs two digits. The two outputs are designated
by the symbols S for sum and C for carry. S gives the value of the least significant bit of the sum,
while C gives the output carry. Then,
S= x y z

C= (x y) z+xy


PROCEDURE:

1. Connections are made as per the circuit diagram.
2. The high state is indicated by connecting the input to Vcc and low to ground.
3. Different combinations of input are carried out and the corresponding outputs are
noted on the LED display.

14. RESULT:
Thus the circuits are designed and outputs are verified successfully.

15. Ex.No:4 Date:__/__/ ____


HALF SUBTRACTOR AND FULL SUBTRACTOR


AIM:

To construct and verify the subtractor circuit using logic gates.

COMPONENTS REQUIRED :


SL.NO

NAME OF THE COMPONENT

RANGE

QUANTITY
1 OR gate IC 7432 1
2 AND gate IC 7408 1
3 EX-OR gate IC 7486 1
4 NOT gate IC 7404 1
5 Digital lab trainer 1
6 Power supply +5v 1
7 Connecting wires As required


Characteristic Equation:

For Half subtractor,

Difference, D= x’y + xy’
= x y

Borrow, B= x’y

For Full subtractor,

Difference, D = x’y’z + xy’z’ + xy’z + xyz
= x y z

Borrow, B = x’y’z + x’yz’ + x’yz +xyz
= z(x


THEORY:

16. It is possible to implement subtraction with logic circuits. Each subtrahend bit of the
number is subtracted from its corresponding significant minuend bit to form a difference bit. If
the minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the next significant
position. The fact that a 1 has been borrowed must be conveyed to the next higher pair of bits
by means of a binary signal coming out (output) of a given stage and going into (input) of the
next higher stage.

Half Subtractor:

A half-subtractor is a combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if a 1 has been borrowed. To perform
x-y we have to check the relative magnitudes of x and y. If x>=y we have three possibilities, 0-
0=0; 1-0 =1; 1-1=0. The result is called the difference bit. If x<y, we have 0-1 and it is needed
to borrow a 1 from the higher significant stage, which adds 2 to the minuend bit ,so that
difference is 1.The half-subtractor needs two outputs difference D and borrow B. From the
truth table,
D= x’y + xy’= x
B= x’y

Full Subtractor:

A full subtractor is a combinational circuit that performs a subtraction between two bits,
taking into account that a 1 may have been borrowed by a lower significant stage .This circuit
has three inputs and two outputs. The three inputs x,y,z denote the minuend, subtrahend and
previous borrow respectively. The outputs D and B represent difference and borrow
respectively. The combinations having input borrow z=0 reduce to the same four conditions of
the half-adder. For x=0, y=0, z=1 . we have to borrow a 1 from the next stage, which makes
B=1 and adds 2 to x. Since 2-0-1=1, D=1, for x=2.Since 2-1-1=0,D=0, for x=1 and yz=01, we
have x-y-z=0, which makes B=0 and D=0. Finally x=1,y=1,z=1, we have to borrow 1,making
B=1 and x=3, 3-1-1=1 making D=1.

The simplified Boolean functions for the outputs are,

D= x y z
B= z(x

17. PROCEDURE:

1. The connections are made as per the circuit diagram .

2. High state is indicated by connecting the input to vcc and low to ground.

3. Different combinations of input are given and the corresponding outputs are noted
on LED display.

4. when LED is ON ,it indicates 1 and when it is OFF, it indicates 0



RESULT:
Thus the circuits are designed and outputs are verified successfully.

18. Ex.No:5 Date:__/__/ ____


MULTIPLEXER AND DEMULTIPLEXER


AIM:

To design and study the operation of multiplexer and de-multiplexer circuits.


COMPONENTS REQUIRED :


SL.NO

NAME OF THE COMPONENT

RANGE

QUANTITY
1 NOT gate IC 7404 1
2 3 input AND gate IC 7411 2
3 OR gate IC 7432 1
4 Digital lab trainer 1
5 Power supply +5v 1
6 Connecting wires

As required


THEORY:

A multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2
n
input lines and n selection lines
whose bit combinations determine which input is selected. The multiplexer acts as an electronic
switch that selects one of the two sources. The multiplexer is often labeled as MUX. It is also
called data selector, since it selects one of the many inputs and stores the binary information to
the output line. The AND gates and inverters resemble to decoder circuit and indeed, they
decode the input selection lines.
The demultiplexer routes the input value to one of the output connectors. The selected
output connector depends on the address read from the address inputs.

19. PROCEDURE:

1. Connections are made as per the circuit diagram.

20. 2. High state is indicated by connecting input to Vcc and low to ground.

3. Different combinations of input are given and corresponding outputs are noted on
the LED display.

4. When LED is ON, it indicates 1 and when it is OFF, it indicates 0.


























RESULT:
Thus the circuits are designed and outputs are verified successfully.

21. Ex.No:6 Date:__/__/ ____


MAGNITUDE COMPARATOR


AIM:

To design a two bit comparator using the digital logic gates and to verify its operation.

COMPONENTS REQUIRED :


SL.NO

NAME OF THE COMPONENT

RANGE

QUANTITY
1 NOR gate IC 7402 1
2 EX-OR gate IC 7486 1
3 AND gate IC 7408 1
4 NOT gate IC 7404 1
5 NAND gate IC 7400 1
6 3 input NAND gate IC 7410 1
7 Digital lab trainer 1
8 Power supply +5v 1
9 Connecting wires As required


THEORY:

The comparison of two numbers is an operation that determines if one number is greater
than, less than or equal to the other number. A magnitude comparator is a combinational circuit
that compares two numbers A and B and determines the relative magnitudes. The outcome of the
comparison is specified by three binary variables that indicate whether A>B, A=B or A<B.
Consider the two numbers with digits,
A=A1A0
B=B1B0
The two numbers will be equal if both the digits are equal. This can be displayed as,
Xi = (Ai Bi)’
A=B: (A1B1 + A1
1
B1
1
).(AoBo +Ao
1
Bo
1
)

= X1X0

To determine if A>B we inspect the relative magnitudes of the pairs of significant digits starting
from the most significant position. If two digits are equal, we compare the next lower significant
pairs of digits. This comparison is continued until a pair of unequal digits is reached. If the
condition A=B and A>B is not satisfied then A<B should be satisfied.

22. The characteristic equations of the outputs are,

A=B: X1X0
A>B: A1B1
1
+X1A0B0
1

A<B: A1
1
B1+X1A0
1
B0



PROCEDURE:


1 .Connections are made as per the circuit diagram.

2. Supply the two bit words A1Ao and B1Bo.

3. First Ao is compared with Bo and then A1 is compared with B1.

4. When LED is ON, it indicates high state and when it is OFF, it indicates low state.

23. RESULT:
Thus the circuits are designed and outputs are verified successfully.