DSD using Verilog Hardware description Language

DSD using Verilog Introduction

1. HKBK College of Engineering OPP.MANYATA TECH PARK, NAGAWARA, BANGALORE-560045 Department of Electronics and Communication Engineering Course: DSD using Verilog Course Code: BEC302 Module 4 Introduction to Verilog & Verilog Data flow description By: Dr. Suhas A R Assoc. Professor Dept . of ECE HKBKCE , Bengaluru-45 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 1

2. Syllabus Introduction to Verilog : Structure of Verilog module, Operators, Data Types, Styles of Description . (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3 ). Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description .(Section2.1to2.2(only Verilog) of Text3) 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 2

3. Hardware description language (HDL) HDL is a computer aided design (CAD) tool for the modern digital design and synthesis of digital systems. Need for HDL The advancement in the semiconductor technology, the power and complexity of digital systems has increased. Due to this, such digital systems cannot be realized using discrete integrated circuits (IC’s). Complex digital systems can be realized using high-density programmable chips such as application specific integrated circuits (ASIC’s) and field programmable gate arrays (FPGA’s). To design such systems, we require sophisticated CAD tool such as HDL. HDL is used by designer to describe the system in a computer language that is similar to other software Language like C. Debugging the design is easy, since HDL package implement simulators and test benches. The two widely used Hardware description languages are VHDL and Verilog . 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 3

4. Evolution of Verilog In 1983, a company called Gateway design Automation developed a hardware-description language for its newly introduced logic simulator verilog_XL . Gateway was bought by cadence in 1989 & cadence made Verilog available as public domain. In December 1995, Verilog HDL became IEEE standard 1364-1995. The language presently is maintained by the Open Verilog international (OVI) organization. Verilog code structure is based on C software language. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 4

5. Structure of Verilog Module The Verilog module has a declaration and a body. In the declaration, name, input and outputs of the modules are listed. The body shows the relationship between the input and the outputs with help of signal assignment statements. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 5

6. Example: AND gate Verilog code- AND gate Module and2( a,b,y ); I nput a, b; Output y; Assign y= a&b ; endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 6

7. Example: Half adder 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 7

8. Contd … Verilog is case sensitive. Halfadder and halfadder are two different modules in verilog . The declaration starts with predefined word module . The name of the module should start with alphabetical letter and can include special character underscore (_). It is user selected. Semicolon (;) is a line separator. The order in which the inputs, &outputs and their declarations are written is irrelevant. “=” is assignment operator, and symbols ^ and & are used for: “ xor ” and “and” respectively. The doubles slashes (//) signal a comment command or /*…………*/ the pair is used to write a comment of any length. The program ends with predefined word endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 8

9. Verilog ports input: the port is only an input port. In any assignment statement, the port should appear only on the right hand side of the assignment statement.(i.e., port is read.) output: the port is an output port. In contrast to VHDL, the Verilog output port can appear on either side of the assignment statement. inout : this port can be used as both an input and output. The inout port represents a bidirectional bus. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 9

10. Operators Operator performs a wide variety of functions. Functions classified as: 1. Logical operators: such as and, or, nand , nor, xor , xnor and not 2. Relational operators: to express the relation between objects. The operators include =, /=, <, <=, >and >=. 3. Arithmetic operators: such as +, -, * and division. 4. Shifts operators: To move the bits of an objects in a certain direction such as right or left sll , srl , sla , sra , rol and ror . 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 10

11. Logical operators These operator performs Logical operations, such as and, or, nand , nor, xor , xnor , and not. The operation can be on two operands or on a single operand. The operand can be single bit or multiple bits. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 11

12. Contd … Other types of logical operators include the Boolean logical operators. These operators operate on two operands, and the result is in Boolean: 0 (false ) or 1 (true). For example: consider the statement Z = X && Y where && is the Boolean logical AND operator. If X = 1011 and Y = 0001, then Z = 1. If X = 1010 and Y = 0101, then Z = 0. Table 1.4 shows the Boolean logical operators . 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 12

13. Verilog Boolean Logical Operators 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 13

14. Verilog Reduction operators Reduction operators operate on a single operand. The result is in Boolean. For example : in the statement Y = &X, where & is the reduction AND operator, and assuming X = 1010, then Y = (1 & 0 & 1 & 0) = 0. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 14

15. Contd … 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 15

16. Relational Operators Relational operators are implemented to compare the values of two objects. The result returned by these operators is in Boolean : false (0) or true (1). 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 16

17. Contd … 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 17

18. A = 3; B = 0; A && B // Evaluates to 0. Equivalent to (logical-1 && logical-0) A || B // Evaluates to 1. Equivalent to (logical-1 || logical-0) !A // Evaluates to 0. Equivalent to not(logical-1) !B // Evaluates to 1. Equivalent to not(logical-0) Example // Unknowns A = 2'b0x; B = 2'b10; A && B // Evaluates to x. Equivalent to (x && logical 1) // Expressions (a == 2) && (b == 3) // Evaluates to 1 if both a == 2 and b == 3 are true. // Evaluates to if either is false. If there are any unknown or z bits in the operands, the expression takes a value x . // A = 4, B = 3 // X = 4'b1010, Y = 4'b1101, Z = 4'b1xxx A <= B // Evaluates to a logical A > B // Evaluates to a logical 1 Y >= X // Evaluates to a logical 1 Y < Z // Evaluates to an x

19. Arithmetic Operators Arithmetic operators can perform a wide variety of operations, such as addition, subtraction, multiplication, and division . Example: the statement Y = (A + B) calculates the value of Y as the sum of A and B. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 19

20. Contd … 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 20

21. Example If i1 = 4'h6; i2 = 4'h2; i1 + i2= 8 i1 - i2= 4 i1 * i2= c i1 / i2= 3 i2 ** 3= 8 i1 % i2= 0 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 21

22. A D = = 4'b0011; B = 4'b0100; // A and B are register 6; E = 4; F=2// D and E are integers vectors A * B // Multiply A and B. Evaluates to 4'b1100 D / E // Divide D by E. Evaluates to 1. Truncates any fractional part. A + B // Add A and B. Evaluates to 4'b0111 B - A // Subtract A from B. Evaluates to 4'b0001 F = E ** F; //E to the power F, yields 16 Note :If any operand bit has a value x, then the result of the entire expression is x. in1 = 4'b101x; in2 = 4'b1010; sum = in1 + in2; // sum will be evaluated to the value 4'bx Example

23. Modulus operators produce the remainder from the division of two numbers. They operate similarly to the modulus operator in the C programming language. 13 % 3 // Evaluat e s to 1 16 % 4 // Evaluat es to Unary operators They are used to specify the positive or negative sign of the operand. -4 // Negative 4 +5 // Positive 5 -10 / 5 // Evaluates to -2 x mod y = r x (dividend) y (divisor) r (remainder)

24. Shift and Rotate Operators Shift and rotate operators are implemented in many applications, such as in multiplication and division . A shift left represents multiplication by two , and a shift right represents division by two . Shift operators are unary operators; they operate on a single operand. To understand the function of these operators , assume operand A is the four-bit vector 1110. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 24

25. Contd … 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 25

26. Data Types The primary intent of data-types in the Verilog language is to represent data storage elements like bits in a flip-flop and transmission elements like wires that connect between logic gates and sequential structures . There are different types of Verilog data types. Namely 1. Nets 2. Registers 3. Vectors 4. Integer 5. Real 6. Parameters 7. Array 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 26

27. Nets Nets are declared by the predefined word wire. Nets have values that change continuously by the circuits that are driving them . The first statement declares a net by the name sum. The second statement declares a net by the name of S1; its initial value is 1’b0, which represents 1 bit with value 0. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 27

28. Register Register, in contrast to nets, stores values until they are updated. Register, as its name suggests, represents data-storage elements. Register is declared by the predefined word reg . The below statement declares a register by the name Sum_total . 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 28

29. Vectors Vectors are multiple bits. A register or a net can be declared as a vector. Vectors are declared by brackets [ ]. The first statement declares a net a. It has four bits, and its initial value is 1010 (b stands for bit). The second statement declares a register total. Its size is eight bits, and its value is decimal 12 (d stands for decimal). 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 29

30. Integers Integers are declared by the predefined word integer. The below statement declares no_bits as an integer. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 30

31. Real Real (floating-point) numbers are declared with the predefined word real . Examples of real values are 2.4, 56.3, and 5e12. The value 5e12 is equal to 5 × 10 12 . 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 31

32. Parameter Parameter represents a global constant. It is declared by the predefined word parameter . To change the size of the inputs x and y, the size of the nets sum, and the size of net Yb to eight bits, the value of N is changed to seven as: 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 32

33. Arrays Verilog, in contrast to VHDL, does not have a predefined word for array. Registers and integers can be written as arrays . The below statements declare an array by the name carry. The array carry has five elements, and each element is four bits. The four bits are in two’s complement form. For example, if the value of a certain element is 1001 , then it is equivalent to decimal –7. Arrays can be multidimensional. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 33

34. Four different levels of abstraction  Behavioral or Algorithmic level Dataflow level Gate level or Structural level Switch level 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 34

35. Behavioral level This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. It specifies the circuit in terms of its expected behavior. It is the closest to a natural language description of the circuit functionality, but also the most difficult to synthesize. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 35

36. Example1: Half adder 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 36

37. Verilog code: Behavioral method module ha( a,b,sum,carry ); input a,b ; output sum , carry ; reg sum , carry ; always@( a,b ) begin case ({ a,b }) // Concatenating ( a,b ) 2'b00:{ carry ,sum }=2'b00; 2 'b01:{ carry ,sum }=2'b01; 2 'b10:{ carry ,sum }=2'b01; 2 'b11:{ carry ,sum }=2'b10; endcase end endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 37

38. Example2: Full adder 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 38

39. Verilog code: Behavioral method module fa ( a,b,cin,sum,cout ); input a,b,cin ; output sum,cout ; reg sum,cout ; always@( a,b,cin ) begin case ({ a,b,cin }) // Concatenating ( a,b,cin ) 3'b000:{ cout,sum }=2'b00; 3'b001:{ cout,sum }=2'b01; 3'b010:{ cout,sum }=2'b01; 3'b011:{ cout,sum }=2'b10; 3'b100:{ cout,sum }=2'b01; 3'b101:{ cout,sum }=2'b10; 3'b110:{ cout,sum }=2'b10; 3'b111:{ cout,sum }=2'b11; endcase end endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 39

40. Example3: Half subtractor 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 40

41. Verilog code: Behavioral method module hs ( a,b,diff,barrow ); input a,b ; output diff, barrow; reg diff, barrow; always @( a,b ) begin case ({ a,b }) 2'b00:{ diff, barrow}= 2'b00; 2'b01 :{ diff, barrow }=2'b11 ; 2'b10 :{ diff, barrow }=2'b10; 2'b11 :{ diff, barrow }=2'b00 ; endcase end endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 41

42. Dataflow level At this level, the module is designed by specifying the data flow. Looking towards this design, one can realize how data flows between hardware registers and how the data is processed in the design. This style is similar to logical equations. The specification is comprised of expressions made up of input signals and assigned to outputs. In most cases, such an approach can be quite easily translated into a structure and then implemented. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 42

43. Verilog code: Dataflow method module fa ( a, b, cin,sum,cout ); input a, b,cin ; output sum, cout ; assign sum= a ^ b ^ cin ; assign cout = (a & b) | (b & cin ) | ( cin & a); endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 43

44. Gate/ structure level The module is implemented in terms of logic gates and interconnections between these gates. It resembles a schematic drawing with components connected with signals. A structural system representation is closer to the physical implementation than behavioral one but it is more involved because of large number of details. Since logic gate is most popular component, Verilog has a predefined set of logic gates known as  primitives . 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 44

45. Example1: Half adder 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 45

46. Verilog code: Structural method module ha( a,b,sum,carry ); input a, b; output sum, carry; xor ( sum,a,b ); and ( carry,a,b ); endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 46

47. Example2: Full adder 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 47

48. Verilog code: Structural method module fa ( a,b,cin,s,cout ); input a, b,cin ; output s, cout ; wire w1,w2,w3; x or (w1,a,b); xor (s,w1,cin); a nd (w2,w1,cin); and ( w3,a,b); or (cout,w2,w3); endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 48

49. Switch level It describes the interconnection of transmission gates, which are abstractions of individual MOS and CMOS transistors . Verilog uses a 4 value logic value system, so Verilog switch input and output signals can take any of the four  0, 1, Z,   and   X  logic values. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 49

50. Example: Inverter 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 50

51. Verilog code: Switch level Module not1(in, out); Input in; Output out; Supply0 gnd ; Supply1 pwr ; Pmos ( out,in,pwr ); Nmos ( out,in,gnd ); endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 51

52. Highlights Of Data-Flow Description Data-flow description simulates the system to be described by showing how the signal flows from the system inputs to its outputs. For example: the Boolean function of the output or the logical structure of the system shows such signal flow. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 52

53. Signal Declaration And Assignment Statement Figure 2.1 shows an AND-OR circuit. Signals a, b, c, and d are the inputs , signal y is the output, and signals s1 and s2 are intermediates. The Boolean function of the output y can be written as: 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 53

54. Contd …. 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 54

55. Simulation result 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 55

56. Constant Declaration and Constant Assignment Statements A constant in HDL is treated as it is in C language; its value is constant within the segment of the program where it is visible. In Verilog, a constant can be declared by its type such as time or integer. For example, the following statements declare period as a constant of type time : time period; // Verilog period = 100; // Verilog 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 56

57. Assigning a Delay Time to the Signal-Assignment Statement To assign a delay time to a signal-assignment statement, the predefined word after # in Verilog is used. For example, the following statement assigns a 10 ns delay time to signal S1 : assign #10 S1 = a & b // Verilog 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 57

58. Example module and_or ( a,b,c,d , y ); input a,b,c,d ; output y; time dly = 10; wire s1, s2; //wire above is not necessarily needed since s1 and s2 are single bit assign # dly s1 = a & b; //statement 1. assign # dly s2 = c & d; //statement 2. assign # dly y = s1 | s2; //statement 3. endmodule 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 58

59. Simulation Result 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 59

60. Problem 1: If A and B are two unsigned variables, with A = 1100 and B = 1001, find the value of the following expressions: a . (A AND B) b. (A ^ B) c. (A XNOR B) d. (A & B) e. (A && B) f. !(A) g. ~( B) h. A << 1 i . A >> 1 j. B ror 2 k. B >>> 2 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 60

61. Problem 2: If P and Q are two unsigned variables, with P = 1101 and Q = 0101, find the value of the following expressions: a. (P NAND Q) b. (P ^ Q) c. (P NOR Q) d. (P & Q) e. (P | Q) f. !(P) g. ~(Q) h.P << 1 i . P >> 2 j. Q rol 2 k. Q >>> 2 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 61

62. Write a Verilog code for the following logic diagram in gate level modelling style. 03-03-2024 Prof. Suhas A R, Asst. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 62

63. Write a Verilog code for the following logic diagram in structural method. 03-03-2024 Prof. Suhas A R, Asst. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 63

64. Write a Verilog code for the following Boolean expression in data flow modelling style. S= ab + cd + ( a+b ) T= abcd + ( ab+cd ) 03-03-2024 Prof. Suhas A R, Asst. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 64

65. Write a Verilog code for the following Boolean expression in data flow modelling style. P= abc +( a+b+c )+ cd Q= ( a+b+c + d )( c+d ) 03-03-2024 Prof. Suhas A R, Asst. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 65

66. Reference HDL Programming VHDL and Verilog by Nazeih M Botros , 2009 reprint, Dream techpress . 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 66

67. Thank You… 03-03-2024 Dr. Suhas A R, Assoc. Prof., Dept. of ECE, HKBKCE, Bengaluru-45 67