E-Note_19681_Content_Document_20240512114009AM.pdf
gowdapriya678
27 views
145 slides
Jun 09, 2024
Slide 1 of 145
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
About This Presentation
E notes containing all the beneficiary document to pass all the subjects of 1 semestes of engineering
Slide Content
1
UNIT – II
EMBEDDED SYSTEM HARDWARE DESIGN
Text book: K.V. Shibu,” Introduction to Embedded Systems”,
2
nd
Edition, McGraw Hill Education, 2017
UNIT – II
EMBEDDED SYSTEM HARDWARE DESIGN
Text book: K.V. Shibu,” Introduction to Embedded Systems”,
2
nd
Edition, McGraw Hill Education, 2017
❖Contents
Embedded System Core: General Purpose and Domain Specific Processors, Application Specific
Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), Commercial off-the-shelf Components
(COTS)
Memory: Overview on Various Types of memory sub systems used in Embedded systems and their selection
Sensors and Actuators: interfacing of LEDs, 7-segment LED Displays, Piezo Buzzer, Stepper Motor,
Relays, Optocouplers, Matrix keyboard, Push button switches, Programmable Peripheral Interface Device
(e.g. 8255 PPI), etc. with the I/O subsystem of the embedded system
Communication Interface: I2C, SPI, CAN, UART,1-wire, parallel bus, etc. RS-232C, RS-485, Parallel Port,
USB, IEEE 1394, Infrared (IrDA), Bluetooth, Wi-Fi, ZigBee, GPRS, etc.
Other System Components: Reset Circuit, Brown-out protection circuit, Oscillator Unit, Real-Time Clock
(RTC), Analog to Digital Converter (ADC), Timers and Watchdog Timer unit
Arm Cortex Mx Processor family Overview: Features, Architecture, Memory System, Exception and
Interrupts, Low Power Features.
2
Embedded System Core: General Purpose and Domain Specific Processors, Application Specific
Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), Commercial off-the-shelf Components
(COTS)
Memory: Overview on Various Types of memory sub systems used in Embedded systems and their selection
Sensors and Actuators: interfacing of LEDs, 7-segment LED Displays, Piezo Buzzer, Stepper Motor,
Relays, Optocouplers, Matrix keyboard, Push button switches, Programmable Peripheral Interface Device
(e.g. 8255 PPI), etc. with the I/O subsystem of the embedded system
Communication Interface: I2C, SPI, CAN, UART,1-wire, parallel bus, etc. RS-232C, RS-485, Parallel Port,
USB, IEEE 1394, Infrared (IrDA), Bluetooth, Wi-Fi, ZigBee, GPRS, etc.
Other System Components: Reset Circuit, Brown-out protection circuit, Oscillator Unit, Real-Time Clock
(RTC), Analog to Digital Converter (ADC), Timers and Watchdog Timer unit
Arm Cortex Mx Processor family Overview: Features, Architecture, Memory System, Exception and
Interrupts, Low Power Features.
2
❖Elements of an embedded system 3
❖Elements of an embedded system 4
❖Core of the Embedded System
The core of the embedded system falls into any one of the following categories:
1. General Purpose and Domain Specific Processors
➢1.1 Microprocessors
➢1.2 Microcontrollers
➢1.3 Digital Signal Processors
5
ATMEGA328P
microcontroller
Microprocessor
Digital Signal Processor
The core of the embedded system falls into any one of the following categories:
1. General Purpose and Domain Specific Processors
➢1.1 Microprocessors
➢1.2 Microcontrollers
➢1.3 Digital Signal Processors
5
ATMEGA328P
microcontroller
Microprocessor
Digital Signal Processor
❖Core of the Embedded System (cont.)
2. Application Specific Integrated Circuits (ASICs)
3. Programmable Logic Devices (PLDs)
4. Commercial off-the-shelf Components (COTS)
6
Example: ASIC interface with
ECG sensor to monitor health
2. Application Specific Integrated Circuits (ASICs)
3. Programmable Logic Devices (PLDs)
4. Commercial off-the-shelf Components (COTS)
6
Example: ASIC interface with
ECG sensor to monitor health
❖Microprocessor Vs Microcontroller
Microcontrollers are designed to perform specific tasks. However, Microprocessors are
designed to perform unspecific tasks like developing software, games, website, photo editing,
creating documents, etc.
Depending on the input, some processing for microcontroller needs to be done and output is
defined. However, the relationship between input and output formicroprocessor is not defined.
Since the applications of microcontroller are very specific, they need small resources like RAM,
ROM, I/O ports etc. and hence can be embedded on a single chip. Microprocessors need high
amount of resources like RAM, ROM, I/O ports etc.
The clock speed of Microprocessor is quite high as compared to the microcontroller. Whereas the
microcontrollers operate from a few MHz from (30 to 50 MHz), today's microprocessor operate
above 1 GHz as they perform complex tasks.
7
❑Merits, Drawbacks and Application Areas
Microcontrollers are designed to perform specific tasks. However, Microprocessors are
designed to perform unspecific tasks like developing software, games, website, photo editing,
creating documents, etc.
Depending on the input, some processing for microcontroller needs to be done and output is
defined. However, the relationship between input and output formicroprocessor is not defined.
Since the applications of microcontroller are very specific, they need small resources like RAM,
ROM, I/O ports etc. and hence can be embedded on a single chip. Microprocessors need high
amount of resources like RAM, ROM, I/O ports etc.
The clock speed of Microprocessor is quite high as compared to the microcontroller. Whereas the
microcontrollers operate from a few MHz from (30 to 50 MHz), today's microprocessor operate
above 1 GHz as they perform complex tasks.
7
❑Merits, Drawbacks and Application Areas
❖Microprocessor Vs Microcontroller
Microprocessor cannot be used stand alone. They need
other peripherals like RAM, ROM, buffer, I/O ports etc., and
hence a system designed around a microprocessor is quite
costly.
Application areas of microcontroller: Mobile Phones,
CD/DVD players, Washing machines, cameras, security
alarms, Microwave oven, etc.
Application areas of microprocessor: Calculators, Accounting
Systems, Games Machine, Complex Industrial Controllers,
Data Acquisition Systems, Military applications,
Communication systems, etc.
8
❑Merits, Drawbacks and Applications Areas (cont.)
Microprocessor cannot be used stand alone. They need
other peripherals like RAM, ROM, buffer, I/O ports etc., and
hence a system designed around a microprocessor is quite
costly.
Application areas of microcontroller: Mobile Phones,
CD/DVD players, Washing machines, cameras, security
alarms, Microwave oven, etc.
Application areas of microprocessor: Calculators, Accounting
Systems, Games Machine, Complex Industrial Controllers,
Data Acquisition Systems, Military applications,
Communication systems, etc.
8
❑Merits, Drawbacks and Applications Areas (cont.)
9
Microprocessor Microcontroller
Microprocessor is heart of computer system. Microcontroller is a heart of embedded system.
It is just a processor, Memory and I/O components
have to be connected externally.
Microcontroller has external processor along with
internal memory and I/O components.
Since memory and I/O has to be connected
externally, the circuit becomes large.
Since memory and I/O are present internally, the
circuit is small.
Cannot be used in compact systems and hence
inefficient.
Can be used in compact systems and hence it is an
efficient technique.
Cost of the entire system increase. Cost of the entire system is low.
❖Difference B/W Microprocessor Vs Microcontroller
Microprocessor Microcontroller
Microprocessor is heart of computer system. Microcontroller is a heart of embedded system.
It is just a processor, Memory and I/O components
have to be connected externally.
Microcontroller has external processor along with
internal memory and I/O components.
Since memory and I/O has to be connected
externally, the circuit becomes large.
Since memory and I/O are present internally, the
circuit is small.
Cannot be used in compact systems and hence
inefficient.
Can be used in compact systems and hence it is an
efficient technique.
Cost of the entire system increase. Cost of the entire system is low.
❖Difference B/W Microprocessor Vs Microcontroller
10
Microprocessor Microcontroller
Due to external components, the entire power
consumption is high. Hence it is not suitable to
used with devices running on stored power like
batteries.
Since external components are low, total power
consumption is less and can be used with devices
running on stored power like batteries.
Most of the microprocessors do not have power
saving features.
Most of the microcontrollers have power saving
modes like idle mode and power saving mode. This
helps to reduce power consumption even further.
Since memory and I/O components are all external,
each instruction will need external operation, hence
it is relatively slower.
Since components are internal, most of the
operations are internal instruction, hence speed is
fast.
Microprocessor have less number of registers,
hence more operations are memory based.
Micro controller have more number of registers,
hence the programs are easier to write.
Microprocessors based on Von Neumann
architecture where program and data are stored in
same memory module.
Microcontrollers are based on Harvard
architecture where program memory and Data
memory are separate.
Mainly used in Personal Computers Used mainly in washing machines, MP3 players
❖Difference B/W Microprocessor Vs Microcontroller
Microprocessor Microcontroller
Due to external components, the entire power
consumption is high. Hence it is not suitable to
used with devices running on stored power like
batteries.
Since external components are low, total power
consumption is less and can be used with devices
running on stored power like batteries.
Most of the microprocessors do not have power
saving features.
Most of the microcontrollers have power saving
modes like idle mode and power saving mode. This
helps to reduce power consumption even further.
Since memory and I/O components are all external,
each instruction will need external operation, hence
it is relatively slower.
Since components are internal, most of the
operations are internal instruction, hence speed is
fast.
Microprocessor have less number of registers,
hence more operations are memory based.
Micro controller have more number of registers,
hence the programs are easier to write.
Microprocessors based on Von Neumann
architecture where program and data are stored in
same memory module.
Microcontrollers are based on Harvard
architecture where program memory and Data
memory are separate.
Mainly used in Personal Computers Used mainly in washing machines, MP3 players
❖Difference B/W Microprocessor Vs Microcontroller
❖Digital Signal Processors (DSPs)
DSPs are powerful special purpose 8/16/32 bit microprocessors designed
specifically to meet the computational demands and power constraints of today’s
embedded audio, video, and communications applications.
DSPs are 2 to 3 times faster than the general purpose microprocessors in signal
processing applications.
A typical digital signal processor incorporates the following key units:
i. Program Memory: Memory for storing the program required by DSP to process the data.
ii. Data Memory: Working memory for storing temporary variables and data/signal to be
processed.
iii. Computational Engine: Performs the signal/math processing, accessing the program
from the program memory and the data from the data memory.
iv. I/O Unit: Acts as an interface between the outside world and DSP. It is responsible for
capturing signals to be processed and delivering the processed signals.
11
DSPs are powerful special purpose 8/16/32 bit microprocessors designed
specifically to meet the computational demands and power constraints of today’s
embedded audio, video, and communications applications.
DSPs are 2 to 3 times faster than the general purpose microprocessors in signal
processing applications.
A typical digital signal processor incorporates the following key units:
i. Program Memory: Memory for storing the program required by DSP to process the data.
ii. Data Memory: Working memory for storing temporary variables and data/signal to be
processed.
iii. Computational Engine: Performs the signal/math processing, accessing the program
from the program memory and the data from the data memory.
iv. I/O Unit: Acts as an interface between the outside world and DSP. It is responsible for
capturing signals to be processed and delivering the processed signals.
11
❖Digital Signal Processors (cont.)
Application areas:
▪Audio video signal processing
▪Telecommunication
▪Multimedia applications
DSP employs a large amount of real-time calculations,
Sum of products (SOP) calculation, convolution, fast
Fourier transform (FFT), Discrete Fourier Transform
(DFT), etc, are some of the operations performed by
digital signal processors.
12
Application areas:
▪Audio video signal processing
▪Telecommunication
▪Multimedia applications
DSP employs a large amount of real-time calculations,
Sum of products (SOP) calculation, convolution, fast
Fourier transform (FFT), Discrete Fourier Transform
(DFT), etc, are some of the operations performed by
digital signal processors.
12
❖RISC Vs CISC processors/controllers 13
RISC CISC
RISC stands for Reduced Instruction Set
Computing
CISC stands for Complex Instruction Set
Computing
Lesser number of instructions Greater number of instructions
Instruction pipelining and increased execution
speed
Generally no instruction pipelining feature
Orthogonal instruction set (Allows each instruction to operate
on any register and use any addressing mode)
Non-orthogonal instruction set (All instructions are not
allowed to operate on any register and use any addressing
mode. It is instruction-specific)
Operations are performed on registers only, the only
memory operations are load and store
Operations are performed on registers or memory
depending on the instruction
A large number of registers are available Limited number of general purpose registers
Programmer needs to write more code to execute a
task since the instructions are simpler ones.
Instructions are like macros in C language. A
programmer can achieve the desired functionality with
a single instruction which in turn provides the effect of
using more simpler single instructions in RISC
RISC CISC
RISC stands for Reduced Instruction Set
Computing
CISC stands for Complex Instruction Set
Computing
Lesser number of instructions Greater number of instructions
Instruction pipelining and increased execution
speed
Generally no instruction pipelining feature
Orthogonal instruction set (Allows each instruction to operate
on any register and use any addressing mode)
Non-orthogonal instruction set (All instructions are not
allowed to operate on any register and use any addressing
mode. It is instruction-specific)
Operations are performed on registers only, the only
memory operations are load and store
Operations are performed on registers or memory
depending on the instruction
A large number of registers are available Limited number of general purpose registers
Programmer needs to write more code to execute a
task since the instructions are simpler ones.
Instructions are like macros in C language. A
programmer can achieve the desired functionality with
a single instruction which in turn provides the effect of
using more simpler single instructions in RISC
RISC Vs CISC processors/controllers (cont.) 14
RISC CISC
Single, fixed length instructions Variable length instructions
Less silicon usage and pin count More silicon usage since more additional decoder
logic is required to implement the complex
instruction decoding
With Harvard Architecture Can be Harvard or Von-Neumann Architecture
Example: Atmel AVR microcontroller Example: 8051 microcontroller
RISC CISC
Single, fixed length instructions Variable length instructions
Less silicon usage and pin count More silicon usage since more additional decoder
logic is required to implement the complex
instruction decoding
With Harvard Architecture Can be Harvard or Von-Neumann Architecture
Example: Atmel AVR microcontroller Example: 8051 microcontroller
❖Harvard vs. Von-Neumann Processor/Controller Architecture15
Harvard Architecture Von-Neumann Architecture
Separate buses for instruction and data fetchingSingle shared bus for instruction and data
fetching
Easier to pipeline, so high performance can be
achieved
Low performance compared to Harvard
architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self modifying codes
Since data memory and program memory are
stored physically in different locations, no
chances for accidental corruption of program
memory
Since data memory and program memory are
stored physically in the same chip, chances for
accidental corruption of program memory
Harvard Architecture Von-Neumann Architecture
Separate buses for instruction and data fetchingSingle shared bus for instruction and data
fetching
Easier to pipeline, so high performance can be
achieved
Low performance compared to Harvard
architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self modifying codes
Since data memory and program memory are
stored physically in different locations, no
chances for accidental corruption of program
memory
Since data memory and program memory are
stored physically in the same chip, chances for
accidental corruption of program memory
Big-Endian vs. Little-Endian Processors/Controllers
Endianness specifies the order in which a sequence of bytes are stored in computer memory.
There are two ways of ordering the data while storing it into the memory.
▪Little-endian
▪Big-endian
Little-endian is an order in which the “ little end “,/ the lower-order byte of the data (least
significant value in the sequence) is stored in memory at the lowest address. (The little end
comes first.)
Big-endian is an order in which the “ Big end ”,/ the higher-order byte of the data (most
significant value in the sequence) is stored in memory at the lowest address. (The big end
comes first.)
16
Endianness specifies the order in which a sequence of bytes are stored in computer memory.
There are two ways of ordering the data while storing it into the memory.
▪Little-endian
▪Big-endian
Little-endian is an order in which the “ little end “,/ the lower-order byte of the data (least
significant value in the sequence) is stored in memory at the lowest address. (The little end
comes first.)
Big-endian is an order in which the “ Big end ”,/ the higher-order byte of the data (most
significant value in the sequence) is stored in memory at the lowest address. (The big end
comes first.)
16
17Big-Endian vs. Little-Endian Processors/Controllers
❖Load Store Operation 18
The memory access related operations are performed by the special instructions load and store.
If the operand is specified as memory location, the content of it is loaded to a register using the load
instruction. The instruction store stores data from a specified register to a specified memory location.
The first instruction load R1, x loads the register R1 with the content of memory location x,
the second instruction load R2,y loads the register R2 with the content of memory location y
The instruction add R3, R1, R2 adds the content of registers R1 and R2 and stores the result in register R3.
The next instruction store R3,z stores the content of register R3 in memory location z.
Instruction pipelining is assignment for you ?
Load
Store
Memory
The memory access related operations are performed by the special instructions load and store.
If the operand is specified as memory location, the content of it is loaded to a register using the load
instruction. The instruction store stores data from a specified register to a specified memory location.
The first instruction load R1, x loads the register R1 with the content of memory location x,
the second instruction load R2,y loads the register R2 with the content of memory location y
The instruction add R3, R1, R2 adds the content of registers R1 and R2 and stores the result in register R3.
The next instruction store R3,z stores the content of register R3 in memory location z.
Instruction pipelining is assignment for you ?
Load
Store
Memory
2. Application Specific Integrated Circuits (ASICs)
ASIC is a microchip designed to perform a specific or unique application.
It integrates several functions into a single chip and there by reduces the
system development cost.
Most of the ASICs are proprietary (which having some trade name) products,
it is referred as Application Specific Standard Products (ASSP).
ASIC consumes a very small area in the total system. Thereby helps in
the design of smaller systems with high capabilities and functionalities.
The developers of such chip may not be interested in revealing the internal
details of it.
19
Example: ASIC interface
with ECG sensor to monitor
health
ASIC is a microchip designed to perform a specific or unique application.
It integrates several functions into a single chip and there by reduces the
system development cost.
Most of the ASICs are proprietary (which having some trade name) products,
it is referred as Application Specific Standard Products (ASSP).
ASIC consumes a very small area in the total system. Thereby helps in
the design of smaller systems with high capabilities and functionalities.
The developers of such chip may not be interested in revealing the internal
details of it.
19
Example: ASIC interface
with ECG sensor to monitor
health
3. Programmable Logic Devices (PLDs)
Logic devices provide specific functions, including device-to-device interfacing, data
communication, signal processing, data display, timing and control operations, and almost
every other function a system must perform.
Logic devices
Fixed logic device are permanent, they perform one function or set of functions once
manufactured, they cannot be changed.
Programmable Logic Devices (PLDs) offer customers a wide range of logic capacity,
features, speed, and voltage characteristics and these devices can be re-configured to
perform any number of functions at any time.
20
fixed Logic devices
Programmable Logic devices
Logic devices provide specific functions, including device-to-device interfacing, data
communication, signal processing, data display, timing and control operations, and almost
every other function a system must perform.
Logic devices
Fixed logic device are permanent, they perform one function or set of functions once
manufactured, they cannot be changed.
Programmable Logic Devices (PLDs) offer customers a wide range of logic capacity,
features, speed, and voltage characteristics and these devices can be re-configured to
perform any number of functions at any time.
20
fixed Logic devices
Programmable Logic devices
3. Programmable Logic Devices (cont.)
The two major types of programmable logic devices:
1. Field Programmable Gate Arrays ( FPGAs):
FPGAs offer the highest amount of logic density (8 million
system gates), the most features, and the highest performance.
FPGAs are used in a wide variety of applications ranging from data
processing and storage, to instrumentation, telecommunications,
and digital signal processing.
2. Complex Programmable Logic Devices (CPLDs):
CPLDs, by contrast, offer much smaller amounts of logic–up to
about 10,000 gates.
CPLDs are used battery-operated, portable applications such as
mobile phones and digital handheld assistants.
21
The two major types of programmable logic devices:
1. Field Programmable Gate Arrays ( FPGAs):
FPGAs offer the highest amount of logic density (8 million
system gates), the most features, and the highest performance.
FPGAs are used in a wide variety of applications ranging from data
processing and storage, to instrumentation, telecommunications,
and digital signal processing.
2. Complex Programmable Logic Devices (CPLDs):
CPLDs, by contrast, offer much smaller amounts of logic–up to
about 10,000 gates.
CPLDs are used battery-operated, portable applications such as
mobile phones and digital handheld assistants.
21
Advantages of PLDs
➢PLDs offer customers much more flexibility during the design cycle.
➢PLDs do not require long lead times for prototypes or production parts.
➢Because PLDs are already on a distributor’s shelf and ready for shipment.
➢PLDs can be reprogrammed even after a piece of equipment is shipped to a customer
22
➢PLDs offer customers much more flexibility during the design cycle.
➢PLDs do not require long lead times for prototypes or production parts.
➢Because PLDs are already on a distributor’s shelf and ready for shipment.
➢PLDs can be reprogrammed even after a piece of equipment is shipped to a customer
22
4. Commercial Off-the-Shelf Components (COTS)
COTS product is one which is used ‘as-is’.
The COTS component itself may be developed around a general
purpose or domain specific processor or an ASICs or a PLDs.
The major advantage of using COTS is that they are readily
available in the market, are cheap and a developer can cut down
his/her development time to a great extent.
The major drawback of using COTS components in embedded design
is that the manufacturer of the COTS component may withdraw the
product or discontinue the production of the COTS at any time if a
rapid change in technology occurs.
23
An example of a COTS product
for TCP/IP plug-in from WIZnet
COTS product is one which is used ‘as-is’.
The COTS component itself may be developed around a general
purpose or domain specific processor or an ASICs or a PLDs.
The major advantage of using COTS is that they are readily
available in the market, are cheap and a developer can cut down
his/her development time to a great extent.
The major drawback of using COTS components in embedded design
is that the manufacturer of the COTS component may withdraw the
product or discontinue the production of the COTS at any time if a
rapid change in technology occurs.
23
An example of a COTS product
for TCP/IP plug-in from WIZnet
Advantages and Disadvantages of COTS
Advantages of COTS
▪Ready to use
▪Easy to integrate
▪Reduces development time
Disadvantages of COTS
▪No operational or manufacturing standard (all proprietary)
▪Vendor or manufacturer may discontinue production of a particular COTS product
24
Advantages of COTS
▪Ready to use
▪Easy to integrate
▪Reduces development time
Disadvantages of COTS
▪No operational or manufacturing standard (all proprietary)
▪Vendor or manufacturer may discontinue production of a particular COTS product
24
25❖Elements of an embedded system
MEMORY
On-chip memory- built-in memory
Off-chip memory- external memory to be connected
1) Program Storage Memory (ROM)
▪Stores the program instructions
▪Non-volatile memory (retains contents even after power is turned off)
2) Read-Write Memory/ Random Access Memory (RAM)
▪Data memory or working memory
▪Volatile memory (power is turned off, contents are destroyed)
26
On-chip memory- built-in memory
Off-chip memory- external memory to be connected
1) Program Storage Memory (ROM)
▪Stores the program instructions
▪Non-volatile memory (retains contents even after power is turned off)
2) Read-Write Memory/ Random Access Memory (RAM)
▪Data memory or working memory
▪Volatile memory (power is turned off, contents are destroyed)
26
Classification of ROM 27
Masked ROM (MROM)
One-time programmable device
Factory programmed by masking and metallization during production (hardwired technology for storing
data)
Different mechanisms used for the masking process of ROM are
1.Creating enhancement or depletion mode transistor through channel implant
2.Creating a memory cell using a standard or high threshold transistor (high threshold mode the supply voltage
required to turn on the transistor is above the normal ROM IC operating voltage. This ensures the transistor is
always off and the memory cell stores always logic 0)
The primary advantage of this is low cost for high-volume production
Masked ROM is a good candidate for storing the embedded firmware for low cost embedded devices.
Limitations:
MROM is permanent in bit storage, hence not possible to alter bit information.
Cannot modify device firmware against firmware updates.
28
One-time programmable device
Factory programmed by masking and metallization during production (hardwired technology for storing
data)
Different mechanisms used for the masking process of ROM are
1.Creating enhancement or depletion mode transistor through channel implant
2.Creating a memory cell using a standard or high threshold transistor (high threshold mode the supply voltage
required to turn on the transistor is above the normal ROM IC operating voltage. This ensures the transistor is
always off and the memory cell stores always logic 0)
The primary advantage of this is low cost for high-volume production
Masked ROM is a good candidate for storing the embedded firmware for low cost embedded devices.
Limitations:
MROM is permanent in bit storage, hence not possible to alter bit information.
Cannot modify device firmware against firmware updates.
28
Programmable Read Only Memory (PROM)
OTP (One Time Programmable Memory)
Not pre-programmed by the manufacturer
End user program the device
Nichrome or polysilicon wires (fuses) arranged in a matrix
Fuses not burned/blown represent a logic 1 (default state) whereas
fuses that are blown/burned represent a logic “0”.
Low-cost solution for commercial production
Limitations:
Cannot be reprogrammed
Not useful for development purposes as the code is subjected to
continuous change (not economical to load code each time using OTP)
29
OTP (One Time Programmable Memory)
Not pre-programmed by the manufacturer
End user program the device
Nichrome or polysilicon wires (fuses) arranged in a matrix
Fuses not burned/blown represent a logic 1 (default state) whereas
fuses that are blown/burned represent a logic “0”.
Low-cost solution for commercial production
Limitations:
Cannot be reprogrammed
Not useful for development purposes as the code is subjected to
continuous change (not economical to load code each time using OTP)
29
Erasable Programmable Read Only Memory (EPROM)
Gives the flexibility to re-program the same chip
Stores bit information by charging the floating gate of a FET
EPROM programmer stores the bit information, which applies high voltage to charge the floating gate
Contains quartz crystal window for erasing the stored information
The window is exposed to ultraviolet rays for a fixed duration, the entire memory will be erased
The EPROM chip is flexible in terms of re-programmability, it needs to be taken out of the circuit
board and put in a UV eraser device for 20 to 30 minutes.
Limitation:
Tedious and time-consuming process
30
Gives the flexibility to re-program the same chip
Stores bit information by charging the floating gate of a FET
EPROM programmer stores the bit information, which applies high voltage to charge the floating gate
Contains quartz crystal window for erasing the stored information
The window is exposed to ultraviolet rays for a fixed duration, the entire memory will be erased
The EPROM chip is flexible in terms of re-programmability, it needs to be taken out of the circuit
board and put in a UV eraser device for 20 to 30 minutes.
Limitation:
Tedious and time-consuming process
30
Electrically Erasable PROM (EEPROM)
Information altered by electrical signals at the register/byte level
Erased and re-programmed in-circuit
These chips include a chip erase mode and in this mode they can be erased in a few milliseconds.
Limitation:
Capacity is limited (few kilobytes)
31
Information altered by electrical signals at the register/byte level
Erased and re-programmed in-circuit
These chips include a chip erase mode and in this mode they can be erased in a few milliseconds.
Limitation:
Capacity is limited (few kilobytes)
31
Flash Memory
FLASH memory is a variation of EEPROM technology.
It combines the re-programmability of EEPROM and the high capacity of standard ROMs.(in MB)
Stores information in an array of floating gate MOSFET transistors
Erasing of memory can be done at the sector or page level without affecting other sectors or pages
(they are erased before re-programming)
The typical erasable capacity of FLASH is of the order of a few 1000 cycles.
Latest technology computers use BIOS (Basic Input/Output System) stored on a Flash memory chip,
called Flash BIOS
Eg: Winbond Flash memory
Uses: modems, pen drives
32
FLASH memory is a variation of EEPROM technology.
It combines the re-programmability of EEPROM and the high capacity of standard ROMs.(in MB)
Stores information in an array of floating gate MOSFET transistors
Erasing of memory can be done at the sector or page level without affecting other sectors or pages
(they are erased before re-programming)
The typical erasable capacity of FLASH is of the order of a few 1000 cycles.
Latest technology computers use BIOS (Basic Input/Output System) stored on a Flash memory chip,
called Flash BIOS
Eg: Winbond Flash memory
Uses: modems, pen drives
32
Classification of Random Access Memory (RAM) 33
Static RAM (SRAM) 34
SRAM cell implementation
Static RAM stores data in the form of voltage.
They are made up of flipflops. Static RAM is the fastest form of
RAM available.
In typical implementation, an SRAM cell (bit) is realised using six
transistors (or 6 MOSFETs).
Four of the transistors are used for building the latch (flipflop)
part of the memory cell and two for controlling the access.
SRAM is fast in operation due to its resistive networking and
switching capabilities.
The major limitations of SRAM are low capacity and high cost.
Visualization of SRAM cell
(2 cross-coupled inverters with read/write control)
SRAM cell implementation
Static RAM stores data in the form of voltage.
They are made up of flipflops. Static RAM is the fastest form of
RAM available.
In typical implementation, an SRAM cell (bit) is realised using six
transistors (or 6 MOSFETs).
Four of the transistors are used for building the latch (flipflop)
part of the memory cell and two for controlling the access.
SRAM is fast in operation due to its resistive networking and
switching capabilities.
The major limitations of SRAM are low capacity and high cost.
Visualization of SRAM cell
(2 cross-coupled inverters with read/write control)
Dynamic RAM (DRAM)
Stores data in the form of a charge
Advantage:
High-density, low-cost
Disadvantage:
Information gets leaked off with time, so periodic refreshing required
Special circuits called DRAM controllers are used for the refreshing operation
The refresh operation is done periodically in millisecond intervals.
MOSFET acts as a gate for incoming and outgoing data
Capacitor acts as bit storage unit
DRAM cell implementation
35
Stores data in the form of a charge
Advantage:
High-density, low-cost
Disadvantage:
Information gets leaked off with time, so periodic refreshing required
Special circuits called DRAM controllers are used for the refreshing operation
The refresh operation is done periodically in millisecond intervals.
MOSFET acts as a gate for incoming and outgoing data
Capacitor acts as bit storage unit
DRAM cell implementation
35
SRAM Vs DRAM
SRAM DRAM
Made of 6 MOSFETs Made of a MOSFET and a Capacitor
Does not require refreshing Requires refreshing
Low capacity ( less dense) High capacity (highly dense)
Fast in operation. Typical access time is
10ns
Slow in operation. Typical access time is
60ns.
More expensive Less expensive
36
SRAM DRAM
Made of 6 MOSFETs Made of a MOSFET and a Capacitor
Does not require refreshing Requires refreshing
Low capacity ( less dense) High capacity (highly dense)
Fast in operation. Typical access time is
10ns
Slow in operation. Typical access time is
60ns.
More expensive Less expensive
36
Non-volatile RAM (NVRAM)
Non-volatile RAM is a random access memory with battery backup
It contains static RAM based memory and a minute battery for providing supply to the memory in the
absence of external power supply.
The memory and battery are packed together in a single package.
NVRAM is used for the nonvolatile storage of results of operations or for setting up of flags, etc.
The life span of NVRAM is expected to be around 10 years.
Eg : DS1744 from Maxim/Dallas is an example for 32KB NVRAM.
37
Non-volatile RAM is a random access memory with battery backup
It contains static RAM based memory and a minute battery for providing supply to the memory in the
absence of external power supply.
The memory and battery are packed together in a single package.
NVRAM is used for the nonvolatile storage of results of operations or for setting up of flags, etc.
The life span of NVRAM is expected to be around 10 years.
Eg : DS1744 from Maxim/Dallas is an example for 32KB NVRAM.
37
Memory Selection for Embedded System (ES)
Memory requirement is dependent on the type of ES and application for which it is designed
Electronic Toy Design
Identify the system requirement (complexity is less, the data memory requirement is minimal)
Microcontroller with few bytes of internal RAM, few bytes or kilobytes of FLASH memory, few bytes of
EEPROM (if required)
Embedded Design with RTOS
RTOS requires a certain amount of RAM for its execution and ROM for storing the RTOS image
binary code for RTOS kernel containing all the services is stored in non-volatile memory (Like FLASH)
as either compressed or non-compressed data
add a buffer value to the total estimated RAM and ROM size requirements.
Eg: A smartphone device with Windows mobile operating system is a typical example for an embedded
device with OS.
38
Memory requirement is dependent on the type of ES and application for which it is designed
Electronic Toy Design
Identify the system requirement (complexity is less, the data memory requirement is minimal)
Microcontroller with few bytes of internal RAM, few bytes or kilobytes of FLASH memory, few bytes of
EEPROM (if required)
Embedded Design with RTOS
RTOS requires a certain amount of RAM for its execution and ROM for storing the RTOS image
binary code for RTOS kernel containing all the services is stored in non-volatile memory (Like FLASH)
as either compressed or non-compressed data
add a buffer value to the total estimated RAM and ROM size requirements.
Eg: A smartphone device with Windows mobile operating system is a typical example for an embedded
device with OS.
38
Parameters that represent a memory
1) Memory size:
Memory density expressed in terms of the number of memory bytes per chip
Memory chips come in standard sizes like 512bytes, 1024bytes (1 kilobyte), 2048bytes (2 kilobytes),
4Kb, 8Kb, 16Kb, 32Kb, 64Kb, 128Kb, 256Kb, 512Kb, 1024Kb (1 megabytes), etc.
Consider the address range supported by your processor
For a processor/controller with a 16-bit address bus, the maximum number of memory locations that
can be addressed is 2^(16) = 65536 bytes = 64Kb.
2) Word size:
The word size refers to the number of memory bits that can be read/write together at a time.
4, 8, 12, 16, 24, 32, etc. are the word sizes supported by memory chips.
Ensure that the word size supported by the memory chip matches with the data bus width of the
processor/controller.
39
1) Memory size:
Memory density expressed in terms of the number of memory bytes per chip
Memory chips come in standard sizes like 512bytes, 1024bytes (1 kilobyte), 2048bytes (2 kilobytes),
4Kb, 8Kb, 16Kb, 32Kb, 64Kb, 128Kb, 256Kb, 512Kb, 1024Kb (1 megabytes), etc.
Consider the address range supported by your processor
For a processor/controller with a 16-bit address bus, the maximum number of memory locations that
can be addressed is 2^(16) = 65536 bytes = 64Kb.
2) Word size:
The word size refers to the number of memory bits that can be read/write together at a time.
4, 8, 12, 16, 24, 32, etc. are the word sizes supported by memory chips.
Ensure that the word size supported by the memory chip matches with the data bus width of the
processor/controller.
39
40
41
Sensors and Actuators
Sensors and Actuators: interfacing of LEDs, 7-segment LED Displays, Piezo Buzzer,
Stepper Motor, Relays, Optocouplers, Matrix keyboard, Push button switches,
Programmable Peripheral Interface Device (e.g. 8255 PPI), etc. with the I/O subsystem of
the embedded system
Sensors and Actuators
Sensors and Actuators: interfacing of LEDs, 7-segment LED Displays, Piezo Buzzer,
Stepper Motor, Relays, Optocouplers, Matrix keyboard, Push button switches,
Programmable Peripheral Interface Device (e.g. 8255 PPI), etc. with the I/O subsystem of
the embedded system
❖Sensors and Actuators 42
Sensors :
▪A sensor is a transducer device that converts energy from one form to another
for any measurement or control purpose.
▪ Example : we can identify that the sensor which counts steps for pedometer
functionality is an Accelerometer sensor and the sensor used in some of the
smartwatch devices to measure the light intensity is an Ambient Light Sensor (ALS)
Sensors :
▪A sensor is a transducer device that converts energy from one form to another
for any measurement or control purpose.
▪ Example : we can identify that the sensor which counts steps for pedometer
functionality is an Accelerometer sensor and the sensor used in some of the
smartwatch devices to measure the light intensity is an Ambient Light Sensor (ALS)
❖Sensors and Actuators 43
Actuators:
▪Actuator is a form of transducer device (mechanical or electrical) which converts
signals to corresponding physical action (motion).
▪Actuator acts as an output device.
▪Example: smartwatches use Ambient Light Sensor to detect the surrounding light
intensity and uses an electrical/electronic actuator circuit to adjust the screen
brightness for better readability.
Actuators:
▪Actuator is a form of transducer device (mechanical or electrical) which converts
signals to corresponding physical action (motion).
▪Actuator acts as an output device.
▪Example: smartwatches use Ambient Light Sensor to detect the surrounding light
intensity and uses an electrical/electronic actuator circuit to adjust the screen
brightness for better readability.
❖The I/O Subsystem
The I/O subsystem of the embedded system facilitates the interaction of the embedded
system with the external world.
The interaction happens through the sensors and actuators connected to the input and
output ports respectively of the embedded system.
The sensors may not be directly interfaced to the input ports, instead they may be
interfaced through signal conditioning and translating systems like ADC, optocouplers,
etc.
44
The I/O subsystem of the embedded system facilitates the interaction of the embedded
system with the external world.
The interaction happens through the sensors and actuators connected to the input and
output ports respectively of the embedded system.
The sensors may not be directly interfaced to the input ports, instead they may be
interfaced through signal conditioning and translating systems like ADC, optocouplers,
etc.
44
❖The I/O Subsystem (cont.)
❑Light Emitting Diode (LED)
❑7-Segment LED Display
❑Stepper Motor
❑Optocoupler
❑Relay
❑Piezo Buzzer
❑Push Button Switch
❑Keyboard
❑Programmable Peripheral Interface ( PPI)
45
❑Light Emitting Diode (LED)
❑7-Segment LED Display
❑Stepper Motor
❑Optocoupler
❑Relay
❑Piezo Buzzer
❑Push Button Switch
❑Keyboard
❑Programmable Peripheral Interface ( PPI)
45
❖Light Emitting Diode (LED)
LED is an important output device for visual indication in any
embedded system. LED can be used as an indicator for the status
of various signals or situations.
Typical examples are indicating the presence of power
conditions like ‘Device ON’, ‘Battery low’ or ‘Charging of battery’ for
a battery operated handheld embedded devices.
LED is a p-n junction diode it contains an anode and a cathode.
For proper functioning of the LED, the anode of it should be
connected to +ve terminal of the supply voltage and cathode to
the –ve terminal of supply voltage. The current flowing through the
LED must be limited to a value below the maximum current that it
can conduct. A resister is used in series between the power supply
and the LED to limit the current through the LED.
46
Fig : LED interfacing
LED is an important output device for visual indication in any
embedded system. LED can be used as an indicator for the status
of various signals or situations.
Typical examples are indicating the presence of power
conditions like ‘Device ON’, ‘Battery low’ or ‘Charging of battery’ for
a battery operated handheld embedded devices.
LED is a p-n junction diode it contains an anode and a cathode.
For proper functioning of the LED, the anode of it should be
connected to +ve terminal of the supply voltage and cathode to
the –ve terminal of supply voltage. The current flowing through the
LED must be limited to a value below the maximum current that it
can conduct. A resister is used in series between the power supply
and the LED to limit the current through the LED.
46
Fig : LED interfacing
❖Light Emitting Diode (LED) (Cont.)
LEDs can be interfaced to the port pin of a
processor/controller in two ways.
Current source:
The anode is directly connected to the port pin
The port pin ‘sources’ current to the LED when the port pin is at
logic High (Logic ‘1’)
Current Sink:
The cathode of the LED is connected to the port pin
The LED is turned on when the port pin is at logic Low (Logic ‘0’)
47
LEDs can be interfaced to the port pin of a
processor/controller in two ways.
Current source:
The anode is directly connected to the port pin
The port pin ‘sources’ current to the LED when the port pin is at
logic High (Logic ‘1’)
Current Sink:
The cathode of the LED is connected to the port pin
The LED is turned on when the port pin is at logic Low (Logic ‘0’)
47
❖ 7-Segment LED Display 48
The 7-segment LED display is an output device for displaying alpha numeric characters.
It contains 8 light-emitting diode (LED) segments arranged in a special form.
Out of the 8 LED segments, 7 are used for displaying alpha numeric characters and 1 is used
for representing ‘decimal point’ in decimal number display.
The LED segments are named A to G and the decimal point LED segment is named as DP.
The 7-segment LED display is an output device for displaying alpha numeric characters.
It contains 8 light-emitting diode (LED) segments arranged in a special form.
Out of the 8 LED segments, 7 are used for displaying alpha numeric characters and 1 is used
for representing ‘decimal point’ in decimal number display.
The LED segments are named A to G and the decimal point LED segment is named as DP.
❖7-Segment LED Display 49
The 7-segment LED displays are available in two different configurations, namely; Common
Anode and Common Cathode.
In the common anode configuration, the anodes of the 8 segments are connected commonly whereas
in the common cathode configuration, the 8 LED segments share a common cathode line.
The LED segment’s anode or cathode is connected to the port of the processor/controller in the order
‘A’ segment to the least significant port pin and DP segment to the most significant port pin.
Fig.: Common anode and cathode configurations of a 7-segment LED Display
The 7-segment LED displays are available in two different configurations, namely; Common
Anode and Common Cathode.
In the common anode configuration, the anodes of the 8 segments are connected commonly whereas
in the common cathode configuration, the 8 LED segments share a common cathode line.
The LED segment’s anode or cathode is connected to the port of the processor/controller in the order
‘A’ segment to the least significant port pin and DP segment to the most significant port pin.
Fig.: Common anode and cathode configurations of a 7-segment LED Display
❖7-Segment LED Display
7-segment LED display is a popular choice for low cost embedded applications like, Public telephone
call monitoring devices, point of sale terminals, etc.
50
https://www.electronics-tutorials.ws/blog/7-segment-display-tutorial.html
7-segment LED display is a popular choice for low cost embedded applications like, Public telephone
call monitoring devices, point of sale terminals, etc.
50
https://www.electronics-tutorials.ws/blog/7-segment-display-tutorial.html
❖ Stepper Motor
A stepper motor is an electro-mechanical device which generates discrete displacement
(motion) in response to dc electrical signals.
It differs from the normal dc motor in its operation.
The dc motor produces continuous rotation on applying dc voltage whereas a stepper
motor produces discrete rotation in response to the dc voltage applied to it.
Stepper motors are widely used in industrial embedded applications, consumer electronic
products and robotics control systems.
The paper feed mechanism of a printer/fax makes use of stepper motors for its functioning.
51
A stepper motor is an electro-mechanical device which generates discrete displacement
(motion) in response to dc electrical signals.
It differs from the normal dc motor in its operation.
The dc motor produces continuous rotation on applying dc voltage whereas a stepper
motor produces discrete rotation in response to the dc voltage applied to it.
Stepper motors are widely used in industrial embedded applications, consumer electronic
products and robotics control systems.
The paper feed mechanism of a printer/fax makes use of stepper motors for its functioning.
51
❖Stepper Motor (Cont.)
Based on the coil winding arrangements, a two-phase stepper
motor is classified into two. They are:
(1) Unipolar (2) Bipolar
(1) Unipolar:
▪A unipolar stepper motor contains two windings per phase.
▪The direction of rotation (clockwise or anticlockwise) of a
stepper motor is controlled by changing the direction of
current flow.
▪Current in one direction flows through one coil and in the
opposite direction flows through the other coil.
▪It is easy to shift the direction of rotation by just switching the
terminals to which the coils are connected.
52
2-Phase unipolar stepper motor
Based on the coil winding arrangements, a two-phase stepper
motor is classified into two. They are:
(1) Unipolar (2) Bipolar
(1) Unipolar:
▪A unipolar stepper motor contains two windings per phase.
▪The direction of rotation (clockwise or anticlockwise) of a
stepper motor is controlled by changing the direction of
current flow.
▪Current in one direction flows through one coil and in the
opposite direction flows through the other coil.
▪It is easy to shift the direction of rotation by just switching the
terminals to which the coils are connected.
52
2-Phase unipolar stepper motor
❖Stepper Motor (Cont.)
(2) Bipolar:
▪A bipolar stepper motor contains single winding per phase.
▪For reversing the motor rotation the current flow through the windings is reversed
dynamically.
▪It requires complex circuitry for current flow reversal.
53
(2) Bipolar:
▪A bipolar stepper motor contains single winding per phase.
▪For reversing the motor rotation the current flow through the windings is reversed
dynamically.
▪It requires complex circuitry for current flow reversal.
53
❖Stepper Motor (Cont.) 54
Fig. Stator Winding details for a 2 Phase unipolar stepper motor
The stator winding details for a two phase unipolar stepper motor is shown in Fig. below.
Fig. Stator Winding details for a 2 Phase unipolar stepper motor
The stator winding details for a two phase unipolar stepper motor is shown in Fig. below.
❖Stepper Motor (Cont.)
The stepping of stepper motor can be implemented in different ways by changing the sequence
of activation of the stator windings. The different stepping modes supported by stepper motor are
explained below.
Full Step In the full step mode both the phases are energized simultaneously. The coils A, B,
C and D are energized in the following order:
55
The stepping of stepper motor can be implemented in different ways by changing the sequence
of activation of the stator windings. The different stepping modes supported by stepper motor are
explained below.
Full Step In the full step mode both the phases are energized simultaneously. The coils A, B,
C and D are energized in the following order:
55
❖Stepper Motor (Cont.) 56
Wave Step:
In the wave step mode only one phase is energized at a time and each coils of the phase
is energized alternatively. The coils A, B, C, and D are energized in the following order.
Wave Step:
In the wave step mode only one phase is energized at a time and each coils of the phase
is energized alternatively. The coils A, B, C, and D are energized in the following order.
❖Stepper Motor (Cont.) 57
Half Step
It uses the combination of wave and full step. It has the highest torque and
stability. The coil energizing sequence for half step is given below.
Half Step
It uses the combination of wave and full step. It has the highest torque and
stability. The coil energizing sequence for half step is given below.
❖Stepper Motor (Cont.)
The rotation of the stepper motor can be reversed by reversing the order in which the coil is
energized.
Two-phase unipolar stepper motors are the popular choice for embedded applications.
The current requirement for stepper motor is little high and hence the port pins of a
microcontroller/processor may not be able to drive them directly.
Also the supply voltage required to operate stepper motor varies normally in the range 5V to
24 V.
Depending on the current and voltage requirements, special driving circuits are required
to interface the stepper motor with microcontroller/processors.
58
The rotation of the stepper motor can be reversed by reversing the order in which the coil is
energized.
Two-phase unipolar stepper motors are the popular choice for embedded applications.
The current requirement for stepper motor is little high and hence the port pins of a
microcontroller/processor may not be able to drive them directly.
Also the supply voltage required to operate stepper motor varies normally in the range 5V to
24 V.
Depending on the current and voltage requirements, special driving circuits are required
to interface the stepper motor with microcontroller/processors.
58
❖Stepper Motor (Cont.) 59
➢The following circuit diagram illustrates the interfacing of a stepper motor through a driver
circuit connected to the port pins of a microcontroller/processor.
Fig. The interfacing of a stepper motor through a driver circuit
➢The following circuit diagram illustrates the interfacing of a stepper motor through a driver
circuit connected to the port pins of a microcontroller/processor.
Fig. The interfacing of a stepper motor through a driver circuit
❖Optocoupler
In electronic circuits, an optocoupler is used for suppressing interference in data communication, circuit
isolation, high voltage separation, simultaneous separation and signal intensification, etc.
Optocouplers can be used in either input circuits or in output circuits. Figure below illustrates the usage
of optocoupler in input circuit and output circuit of an embedded system with a microcontroller as the
system core.
60
Optocoupler is a solid state device to isolate two parts of a circuit.
Optocoupler combines an LED and a photo-transistor in a single
housing (package).
Following figure illustrates the functioning of an optocoupler device.
Fig. optocoupler in input and output circuit
Optocoupler
In electronic circuits, an optocoupler is used for suppressing interference in data communication, circuit
isolation, high voltage separation, simultaneous separation and signal intensification, etc.
Optocouplers can be used in either input circuits or in output circuits. Figure below illustrates the usage
of optocoupler in input circuit and output circuit of an embedded system with a microcontroller as the
system core.
60
Optocoupler is a solid state device to isolate two parts of a circuit.
Optocoupler combines an LED and a photo-transistor in a single
housing (package).
Following figure illustrates the functioning of an optocoupler device.
Fig. optocoupler in input and output circuit
Optocoupler
❖Relay
Relay is an electro-mechanical device. In embedded application,
the ‘Relay’ unit acts as dynamic path selectors for signals and
power.
The ‘Relay’ unit contains a relay coil made up of insulated wire on
a metal core and a metal armature with one or more contacts.
‘Relay’ works on electromagnetic principle. When a voltage is
applied to the relay coil, current flows through the coil, which in
turn generates a magnetic field.
The magnetic field attracts the armature core and moves the
contact point. The movement of the contact point changes the
power/signal flow path.
61
Relay is an electro-mechanical device. In embedded application,
the ‘Relay’ unit acts as dynamic path selectors for signals and
power.
The ‘Relay’ unit contains a relay coil made up of insulated wire on
a metal core and a metal armature with one or more contacts.
‘Relay’ works on electromagnetic principle. When a voltage is
applied to the relay coil, current flows through the coil, which in
turn generates a magnetic field.
The magnetic field attracts the armature core and moves the
contact point. The movement of the contact point changes the
power/signal flow path.
61
❖Relay (Cont.) 62
➢ The Single Pole Single Throw configuration has only one path for information flow. The path is
either open or closed in normal condition.
➢ For normally Open Single Pole Single Throw relay, the circuit is normally open and it becomes
closed when the relay is energized.
➢ For normally closed Single Pole Single Throw configuration, the circuit is normally closed and it
becomes open when the relay is energized.
➢ For Single Pole Double Throw Relay, there are two paths for information flow and they are
selected by energising or de-energising the relay.
Fig.: Relay configurations
➢‘Relays’ are available in different
configurations. Figure given below
illustrates the widely used relay
configurations for embedded applications.
➢ The Single Pole Single Throw configuration has only one path for information flow. The path is
either open or closed in normal condition.
➢ For normally Open Single Pole Single Throw relay, the circuit is normally open and it becomes
closed when the relay is energized.
➢ For normally closed Single Pole Single Throw configuration, the circuit is normally closed and it
becomes open when the relay is energized.
➢ For Single Pole Double Throw Relay, there are two paths for information flow and they are
selected by energising or de-energising the relay.
Fig.: Relay configurations
➢‘Relays’ are available in different
configurations. Figure given below
illustrates the widely used relay
configurations for embedded applications.
❖Relay (Cont.) 63
➢The Relay is normally controlled using a relay driver circuit connected to the port pin of
the processor/controller.
➢A transistor is used for building the relay driver circuit.
Fig. Transistor based Relay driving circuit
➢The Relay is normally controlled using a relay driver circuit connected to the port pin of
the processor/controller.
➢A transistor is used for building the relay driver circuit.
Fig. Transistor based Relay driving circuit
❖Piezo Buzzer
Piezo buzzer is a piezoelectric device for generating audio indications in embedded application.
A piezoelectric buzzer contains a piezoelectric diaphragm which produces audible sound in
response to the voltage applied to it.
Piezoelectric buzzers are available in two types. ‘Self-driving’ and ‘External driving’.
The ‘Self-driving’ circuit contains all the necessary components to generate sound at a predefined
tone. It will generate a tone on applying the voltage.
External driving piezo buzzers supports the generation of different tones. The tone can be varied
by applying a variable pulse train to the piezoelectric buzzer.
64
Piezo buzzer is a piezoelectric device for generating audio indications in embedded application.
A piezoelectric buzzer contains a piezoelectric diaphragm which produces audible sound in
response to the voltage applied to it.
Piezoelectric buzzers are available in two types. ‘Self-driving’ and ‘External driving’.
The ‘Self-driving’ circuit contains all the necessary components to generate sound at a predefined
tone. It will generate a tone on applying the voltage.
External driving piezo buzzers supports the generation of different tones. The tone can be varied
by applying a variable pulse train to the piezoelectric buzzer.
64
❖Push Button Switch
It is an input device. Push button switch comes in two configurations, namely ‘Push to Make’ and
‘Push to Break’.
In the ‘Push to Make’ configuration, the switch is normally in the open state and it makes a circuit
contact when it is pushed or pressed.
In the ‘Push to Break’ configuration, the switch is normally in the closed state and it breaks the circuit
contact when it is pushed or pressed.
In embedded application push button is generally used as reset and start Switch.
65
It is an input device. Push button switch comes in two configurations, namely ‘Push to Make’ and
‘Push to Break’.
In the ‘Push to Make’ configuration, the switch is normally in the open state and it makes a circuit
contact when it is pushed or pressed.
In the ‘Push to Break’ configuration, the switch is normally in the closed state and it breaks the circuit
contact when it is pushed or pressed.
In embedded application push button is generally used as reset and start Switch.
65
❖Keyboard
Keyboard is an input device for user interfacing.
If the number of keys required is very limited, push button switches can be used and they can
be directly interfaced to the port pins for reading.
Matrix keyboard is an optimum solution for handling large key requirements.
Matrix keyboard greatly reduces the number of interface connections.
In a matrix keyboard, the keys are arranged in matrix fashion.
For example, for interfacing 16 keys, in the direct interfacing technique 16 port pins are
required, whereas in the matrix keyboard only 8 lines are required. The 16 keys are
arranged in a 4 column × 4 Row matrix.
The key press in Matrix keyboard is identified with row-column scanning technique.
66
Keyboard is an input device for user interfacing.
If the number of keys required is very limited, push button switches can be used and they can
be directly interfaced to the port pins for reading.
Matrix keyboard is an optimum solution for handling large key requirements.
Matrix keyboard greatly reduces the number of interface connections.
In a matrix keyboard, the keys are arranged in matrix fashion.
For example, for interfacing 16 keys, in the direct interfacing technique 16 port pins are
required, whereas in the matrix keyboard only 8 lines are required. The 16 keys are
arranged in a 4 column × 4 Row matrix.
The key press in Matrix keyboard is identified with row-column scanning technique.
66
❖Keyboard (Cont.) 67
Matrix keyboard Interfacing
Matrix keyboard Interfacing
❖Programmable Peripheral Interface ( PPI)
Assignment for you?
68
Assignment for you?
68
69❖Elements of an embedded system
Communication interface
Essential for communicating with various subsystems of embedded system and with the external
world
Onboard Communication Interface (Device/board level communication interface)
External Communication Interface (Product level communication interface)
Onboard Communication Interface:
Embedded product is a combination of different types of components (chips/devices) arranged
on PCB
The communication channel that interconnects various components within an embedded product
Serial interfaces like I2C, SPI, UART, 1-Wire, etc and parallel bus interfaces are examples
70
Essential for communicating with various subsystems of embedded system and with the external
world
Onboard Communication Interface (Device/board level communication interface)
External Communication Interface (Product level communication interface)
Onboard Communication Interface:
Embedded product is a combination of different types of components (chips/devices) arranged
on PCB
The communication channel that interconnects various components within an embedded product
Serial interfaces like I2C, SPI, UART, 1-Wire, etc and parallel bus interfaces are examples
70
External Communication Interface:
Some ES are self-contained units and they don’t require any interaction and data transfer with
other sub-systems or external world
On the other hand, certain ES may be a part of large distributed systems and they require
interaction and data transfer between various devices and sub-modules
External communication interface can be wired or wireless and serial or parallel interface
Wireless communication interface
Eg: Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi), Radio Frequency Waves (RF), GPRS, etc
Wired interface
Eg: RS-232C/RS-422/RS-485, USB, Ethernet IEEE 1392 port, Parallel port, CF-II interface
(Compact Flash card), Secure Digital Input Output (SDIO), PCMCIA (PC card), etc
71
Some ES are self-contained units and they don’t require any interaction and data transfer with
other sub-systems or external world
On the other hand, certain ES may be a part of large distributed systems and they require
interaction and data transfer between various devices and sub-modules
External communication interface can be wired or wireless and serial or parallel interface
Wireless communication interface
Eg: Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi), Radio Frequency Waves (RF), GPRS, etc
Wired interface
Eg: RS-232C/RS-422/RS-485, USB, Ethernet IEEE 1392 port, Parallel port, CF-II interface
(Compact Flash card), Secure Digital Input Output (SDIO), PCMCIA (PC card), etc
71
72
Onboard Communication Interface
I2C, SPI, UART, 1-Wire, parallel bus interfaces, CAN
Onboard Communication Interface
I2C, SPI, UART, 1-Wire, parallel bus interfaces, CAN
❖I2C (Inter Integrated Circuit) Bus
Synchronous bi-directional half duplex, two-wire serial interface bus
Two bus lines: Serial Clock (SCL) and Serial Data (SDA)
SCL responsible for generating synchronization clock pulses
SDA responsible for transmitting serial data across the device
Shared bus system (many I2C devices can be connected)
Master/Slave device (devices connected to I2C)
Master Device- responsible for controlling the communication by initiating/terminating data
transfer, sending data, and generating synchronization clock pulses
Slave device- wait for the commands from the master and respond accordingly
Master and Slave devices can act as transmitters or receivers (synchronization clock signal
generated by the master only).
73
Synchronous bi-directional half duplex, two-wire serial interface bus
Two bus lines: Serial Clock (SCL) and Serial Data (SDA)
SCL responsible for generating synchronization clock pulses
SDA responsible for transmitting serial data across the device
Shared bus system (many I2C devices can be connected)
Master/Slave device (devices connected to I2C)
Master Device- responsible for controlling the communication by initiating/terminating data
transfer, sending data, and generating synchronization clock pulses
Slave device- wait for the commands from the master and respond accordingly
Master and Slave devices can act as transmitters or receivers (synchronization clock signal
generated by the master only).
73
With pull-up resistors the output lines of
Bus in idle state will be HIGH
Operations:
1.Master device pulls the SCL of the bus to HIGH
2.SCL HIGH
SDA LOW – Start condition
3.Master Sends the address (7bit or 10bit wide) of
the slave to whom it wants to communicate
over the SDA line. Clock pulses are generated.
MSB of data is always transmitted first. Data is
valid during the high of the Clock signal
4.Master send Read or Write bit(1-Read, 0-Write)
5.Master waits for ack from slave whose address is
sent on the bus. Slave compares address
74
Bus in idle state will be HIGH
Operations:
1.Master device pulls the SCL of the bus to HIGH
2.SCL HIGH
SDA LOW – Start condition
3.Master Sends the address (7bit or 10bit wide) of
the slave to whom it wants to communicate
over the SDA line. Clock pulses are generated.
MSB of data is always transmitted first. Data is
valid during the high of the Clock signal
4.Master send Read or Write bit(1-Read, 0-Write)
5.Master waits for ack from slave whose address is
sent on the bus. Slave compares address
74
6.Slave sends ack bit( value=1) over SDA line
7.Once ack is received, the master sends 8-bit data to the slave device over the SDA line, if the requested
operation is ‘Write’. If ‘Read’, the slave sends data to the master over the SDA line
8.Master waits for ack bit upon byte transfer complete after Write operation and sends ack bit to slave for
a read operation
9.SCL HIGH
SDA HIGH – Stop condition
Supports 3different data rates
▪Standard mode(up to 100Kbps)
▪Fast mode(up to 400Kbps)
▪High-speed mode (up to 3.4Mbps)
75
7.Once ack is received, the master sends 8-bit data to the slave device over the SDA line, if the requested
operation is ‘Write’. If ‘Read’, the slave sends data to the master over the SDA line
8.Master waits for ack bit upon byte transfer complete after Write operation and sends ack bit to slave for
a read operation
9.SCL HIGH
SDA HIGH – Stop condition
Supports 3different data rates
▪Standard mode(up to 100Kbps)
▪Fast mode(up to 400Kbps)
▪High-speed mode (up to 3.4Mbps)
75
❖Serial Peripheral Interface (SPI)
Synchronous bi-directional full duplex four-wire serial interface bus
Single master multi-slave system
more than one SPI device can be master, provided the condition only one master device is active
at any given point of time
76
Synchronous bi-directional full duplex four-wire serial interface bus
Single master multi-slave system
more than one SPI device can be master, provided the condition only one master device is active
at any given point of time
76
Master Out Slave In (MOSI): Signal line carrying the data from master to slave device. It is also
known as Slave Input/Slave Data In (SI/SDI)
Master In Slave Out (MISO): Signal line carrying the data from slave to master device. It is also
known as Slave Output/ Slave Data out (SO/SDO)
Serial Clock (SCLK): Signal line carrying the clock signals
Slave Select (SS): Signal line for slave device select. It is an active low-signal
Working:
The master device is responsible for generating the clock signal.
It selects the required slave device by asserting the corresponding slave device’s slave select
signal ‘LOW’.
The data out line (MISO) of all the slave devices when not selected floats at high impedance state
77
known as Slave Input/Slave Data In (SI/SDI)
Master In Slave Out (MISO): Signal line carrying the data from slave to master device. It is also
known as Slave Output/ Slave Data out (SO/SDO)
Serial Clock (SCLK): Signal line carrying the clock signals
Slave Select (SS): Signal line for slave device select. It is an active low-signal
Working:
The master device is responsible for generating the clock signal.
It selects the required slave device by asserting the corresponding slave device’s slave select
signal ‘LOW’.
The data out line (MISO) of all the slave devices when not selected floats at high impedance state
77
The serial peripheral control register holds various configuration parameters like master/slave
selection for the device, baud rate selection for communication, clock signal control, etc.
The status register holds the status of various conditions for transmission and reception.
SPI works on the principle of ‘Shift Register’. The master and slave devices contain a special shift
register for the data to transmit or receive.
During transmission from the master to slave, the data in the master’s shift register is shifted out to
the MOSI pin and it enters the shift register of the slave device through the MOSI pin of the slave
device.
At the same time the shifted out data bit from the slave device’s shift register enters the shift register
of the master device through MISO pin.
Shift registers of ‘master’ and ‘slave’ devices form a circular buffer.
SPI doesn’t support an acknowledgment mechanism
78
selection for the device, baud rate selection for communication, clock signal control, etc.
The status register holds the status of various conditions for transmission and reception.
SPI works on the principle of ‘Shift Register’. The master and slave devices contain a special shift
register for the data to transmit or receive.
During transmission from the master to slave, the data in the master’s shift register is shifted out to
the MOSI pin and it enters the shift register of the slave device through the MOSI pin of the slave
device.
At the same time the shifted out data bit from the slave device’s shift register enters the shift register
of the master device through MISO pin.
Shift registers of ‘master’ and ‘slave’ devices form a circular buffer.
SPI doesn’t support an acknowledgment mechanism
78
I2C vs SPI 79
❖Universal Asynchronous Receiver Transmitter (UART)
Asynchronous form of serial data communication
Does not require a clock signal to synchronize the transmitting and receiving end for the
transmission
The serial communication settings (Baud rate, number of bits per byte, parity, number of start
bits and stop bit and flow control) should be set identical for transmitter and receiver
The start and stop of communication- through inserting special bits in the data stream
Sending a byte of data (start bit added first, stop bit added at the end of the bit stream. LSB
of the data byte follows the start bit)
80
Asynchronous form of serial data communication
Does not require a clock signal to synchronize the transmitting and receiving end for the
transmission
The serial communication settings (Baud rate, number of bits per byte, parity, number of start
bits and stop bit and flow control) should be set identical for transmitter and receiver
The start and stop of communication- through inserting special bits in the data stream
Sending a byte of data (start bit added first, stop bit added at the end of the bit stream. LSB
of the data byte follows the start bit)
80
Start bit- informs the receiver that a data byte is about to arrive
Receiver device starts polling its receive line as per baud rate settings (baud rate ‘x’ bits per
second, time slot available for one bit is 1/x seconds)
Parity enabled- UART of the transmitting device adds a parity bit (bit 1 for odd number of 1s and 0
for even number of 1s in the transmitted bit stream)
UART of receiving device calculates parity of bits received and compares for error checking
UART of receiving device discards the ‘Start’, ‘Stop’ and ‘Parity’ bit from the received bit
stream
Converts the received serial bit data to a word (first received bit as LSB and last received
data bits as MSB)
‘Transmit line’ of sending device connected to the ‘receive line’ of the receiving device
Provides hardware handshaking signal support for controlling serial data flow
Eg: 8250 UART
81
Receiver device starts polling its receive line as per baud rate settings (baud rate ‘x’ bits per
second, time slot available for one bit is 1/x seconds)
Parity enabled- UART of the transmitting device adds a parity bit (bit 1 for odd number of 1s and 0
for even number of 1s in the transmitted bit stream)
UART of receiving device calculates parity of bits received and compares for error checking
UART of receiving device discards the ‘Start’, ‘Stop’ and ‘Parity’ bit from the received bit
stream
Converts the received serial bit data to a word (first received bit as LSB and last received
data bits as MSB)
‘Transmit line’ of sending device connected to the ‘receive line’ of the receiving device
Provides hardware handshaking signal support for controlling serial data flow
Eg: 8250 UART
81
1-Wire Interface (Dallas 1-Wire® protocol)
Asynchronous half-duplex communication protocol
Single signal line called DQ for communication
Single master multi-slave system
It is typically used to communicate with small inexpensive devices such as digital thermometers
and weather instruments.
82
Asynchronous half-duplex communication protocol
Single signal line called DQ for communication
Single master multi-slave system
It is typically used to communicate with small inexpensive devices such as digital thermometers
and weather instruments.
82
83
The sequence of operation for communicating with a 1-wire slave device is listed below.
1.The master device sends a ‘Reset’ pulse on the 1-wire bus.
2. The slave device(s) present on the bus respond with a ‘Presence’ pulse.
3. The master device sends a ROM command (Net Address Command followed by the 64bit
address of the device). This addresses the slave device(s) to which it wants to initiate a
communication.
4. The master device sends a read/write function command to read/write the internal memory
or register of the slave device.
5. The master initiates a Read data/Write data from the device or to the device
The sequence of operation for communicating with a 1-wire slave device is listed below.
1.The master device sends a ‘Reset’ pulse on the 1-wire bus.
2. The slave device(s) present on the bus respond with a ‘Presence’ pulse.
3. The master device sends a ROM command (Net Address Command followed by the 64bit
address of the device). This addresses the slave device(s) to which it wants to initiate a
communication.
4. The master device sends a read/write function command to read/write the internal memory
or register of the slave device.
5. The master initiates a Read data/Write data from the device or to the device
Parallel Interface
On-board parallel interface is used for communicating with peripheral devices which are memory
mapped to the host of the ES
Contains parallel bus – the device which supports parallel bus can directly connect to this bus
subsystem
Controlled by the control signal interface between the device and the host
Control Signals: Read/Write signal and device select signal
Device select line: device becomes active when this line is asserted by the host processor
Read/Write: The direction of data transfer (host to device or device to host) can be controlled. Only
host processor has control over these control signals
84
On-board parallel interface is used for communicating with peripheral devices which are memory
mapped to the host of the ES
Contains parallel bus – the device which supports parallel bus can directly connect to this bus
subsystem
Controlled by the control signal interface between the device and the host
Control Signals: Read/Write signal and device select signal
Device select line: device becomes active when this line is asserted by the host processor
Read/Write: The direction of data transfer (host to device or device to host) can be controlled. Only
host processor has control over these control signals
84
Device is memory mapped to the host processor and a range of address is assigned to it
An address decoder circuit for generating the Chip Select signal for the device
(When the address selected by the processor is within the range assigned for the device, the decoder
circuit activates the chip select line and the device becomes active)
Strict timing characteristics for parallel communication
If a device wants to initiate communication, it can inform the processor through interrupts
Width of the parallel interface is determined by the data bus width of the host processor (4bit, 8bit,
16bit, 32bit or 64bit, etc)
Parallel data communication offers the highest speed for data transfer
Used within integrated circuits, in peripheral buses, and memory devices such as RAM.
85
An address decoder circuit for generating the Chip Select signal for the device
(When the address selected by the processor is within the range assigned for the device, the decoder
circuit activates the chip select line and the device becomes active)
Strict timing characteristics for parallel communication
If a device wants to initiate communication, it can inform the processor through interrupts
Width of the parallel interface is determined by the data bus width of the host processor (4bit, 8bit,
16bit, 32bit or 64bit, etc)
Parallel data communication offers the highest speed for data transfer
Used within integrated circuits, in peripheral buses, and memory devices such as RAM.
85
CAN (Controller Area Network)
Asynchronous serial communication protocol introduced in 1986 by Robert Bosch.
Message-based protocol (not address-based) means transmitted data is available for all nodes and
its receiver’s choice to receive data or not.
CAN is designed to replace the conventional wiring used in old days in the automobile for
communication between ECUs (Electronic Control Unit)
CAN nodes are connected on two wire(CAN_H and CAN_L) twisted pair cable (termed as
CAN bus) terminated with 120Ω resistance to prevent the reflection
Application areas
1.Transportation system (rail vehicle, aircraft, marine, etc.)
2.Home and building automation (e.g. HVAC, elevators)
3.Industrial machine control systems.
4.Mobile machines (construction and agriculture equipment)
5.Medical devices and laboratory automation
86
Asynchronous serial communication protocol introduced in 1986 by Robert Bosch.
Message-based protocol (not address-based) means transmitted data is available for all nodes and
its receiver’s choice to receive data or not.
CAN is designed to replace the conventional wiring used in old days in the automobile for
communication between ECUs (Electronic Control Unit)
CAN nodes are connected on two wire(CAN_H and CAN_L) twisted pair cable (termed as
CAN bus) terminated with 120Ω resistance to prevent the reflection
Application areas
1.Transportation system (rail vehicle, aircraft, marine, etc.)
2.Home and building automation (e.g. HVAC, elevators)
3.Industrial machine control systems.
4.Mobile machines (construction and agriculture equipment)
5.Medical devices and laboratory automation
86
CAN network is made of Node and CAN Bus terminated with 120ohm.
Every Node has three components to accomplish data transmission over CAN (represented in Fig:
CAN Network Architecture below)
1.Host Controller: MCU which is the host controller and decides how to deal with received or transmit
data. It processes data from the Application layer to the network layer and vice versa.
2.CAN Controller: takes care of the message reception and transmission, error detection and handling
etc.
3.CAN Transceiver: convert the CAN controller data into bus level before sending it on the CAN Bus
and vice-versa.
87
Every Node has three components to accomplish data transmission over CAN (represented in Fig:
CAN Network Architecture below)
1.Host Controller: MCU which is the host controller and decides how to deal with received or transmit
data. It processes data from the Application layer to the network layer and vice versa.
2.CAN Controller: takes care of the message reception and transmission, error detection and handling
etc.
3.CAN Transceiver: convert the CAN controller data into bus level before sending it on the CAN Bus
and vice-versa.
87
88
External Communication Interface
(wired)
RS-232C/RS-422/RS-485, USB, IEEE 1394 (Firewire)
External Communication Interface
(wired)
RS-232C/RS-422/RS-485, USB, IEEE 1394 (Firewire)
RS-232 C & RS-485
Recommended Standard Number 232, revision C from Electronic Industry Association(EIA)
Legacy, full duplex, wired, asynchronous serial communication interface
Extends the UART communication signals for external data communication
UART: standard TTL/CMOS logic (logic HIGH corresponds to bit value 1 and logic LOW to bit value
0)
RS 232: EIA standard for bit transmission (logic 0 represented with voltage between +3 and +25V
and logic 1 with voltage between -3 and -25V)
▪Logic 0 – Space
▪Logic 1 – Mark
Defines various handshaking and control signals for communication apart from the ‘Transmit’ and
‘Receive’ signal lines for data communication.
89
Recommended Standard Number 232, revision C from Electronic Industry Association(EIA)
Legacy, full duplex, wired, asynchronous serial communication interface
Extends the UART communication signals for external data communication
UART: standard TTL/CMOS logic (logic HIGH corresponds to bit value 1 and logic LOW to bit value
0)
RS 232: EIA standard for bit transmission (logic 0 represented with voltage between +3 and +25V
and logic 1 with voltage between -3 and -25V)
▪Logic 0 – Space
▪Logic 1 – Mark
Defines various handshaking and control signals for communication apart from the ‘Transmit’ and
‘Receive’ signal lines for data communication.
89
Supports 2 types of connectors
1.DB-9: 9-pin connector
2.DB-25: 25-pin connector
90
1.DB-9: 9-pin connector
2.DB-25: 25-pin connector
90
Point-to-point communication interface
Devices involved in communication are Data Terminal Equipment (DTE) and Data
Communication Equipment (DCE)
If no data flow control is required: only TXD and RXD signal lines and GND line are required for
data transmission and reception
The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper data
transmission
If hardware data flow control is required: various control signal lines (implemented mainly for
modem communication) are used appropriately
The Request To Send (RTS) and Clear To Send (CTS) signals coordinate communication
between DTE and DCE
(whenever DTE has data to send, it activates RTS line and if DCE is ready to accept the data, it
activates CTS line)
91
Devices involved in communication are Data Terminal Equipment (DTE) and Data
Communication Equipment (DCE)
If no data flow control is required: only TXD and RXD signal lines and GND line are required for
data transmission and reception
The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper data
transmission
If hardware data flow control is required: various control signal lines (implemented mainly for
modem communication) are used appropriately
The Request To Send (RTS) and Clear To Send (CTS) signals coordinate communication
between DTE and DCE
(whenever DTE has data to send, it activates RTS line and if DCE is ready to accept the data, it
activates CTS line)
91
The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept the data
The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a communication link
*DTR should be in the activated state before activation of DSR
The Data Carrier Detect (DCD) control signal is used by DCE to indicate the DTE that a good signal
is being received
Ring Indicator (RI) is a modem-specific signal line for indicating an incoming call on the telephone
line
Supports baud rate up to 20Kbps
Commonly used baud rates by devices are 300bps, 1200bps, 2400bps, 9600bps, 11.52Kbps, and
19.2Kbps
Maximum operating distance – 50 feet
Not suitable for multi-drop communication
92
The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a communication link
*DTR should be in the activated state before activation of DSR
The Data Carrier Detect (DCD) control signal is used by DCE to indicate the DTE that a good signal
is being received
Ring Indicator (RI) is a modem-specific signal line for indicating an incoming call on the telephone
line
Supports baud rate up to 20Kbps
Commonly used baud rates by devices are 300bps, 1200bps, 2400bps, 9600bps, 11.52Kbps, and
19.2Kbps
Maximum operating distance – 50 feet
Not suitable for multi-drop communication
92
Serial communication:
Embedded devices contain UART for serial communication.
They generate signal levels to TTL/CMOS logic.
A level translator (Eg: MAX 232) is used for converting signal lines from the UART to RS-232
signal lines for communication
On the receiving side the received data is converted back to the digital logic level by a converter
IC (for both transmitter and receiver)
RS-422:
▪Supports data rate up to 100Kbps
▪Distance up to 400 feet
▪Supports multidrop communication with one transmitter device and receiver device up to 10
RS-485:
▪Supports multi-drop communication up to 32 transmitting devices and 32 receiving devices on the
bus
93
Embedded devices contain UART for serial communication.
They generate signal levels to TTL/CMOS logic.
A level translator (Eg: MAX 232) is used for converting signal lines from the UART to RS-232
signal lines for communication
On the receiving side the received data is converted back to the digital logic level by a converter
IC (for both transmitter and receiver)
RS-422:
▪Supports data rate up to 100Kbps
▪Distance up to 400 feet
▪Supports multidrop communication with one transmitter device and receiver device up to 10
RS-485:
▪Supports multi-drop communication up to 32 transmitting devices and 32 receiving devices on the
bus
93
Universal Serial Bus (USB)
Universal Serial Bus ( USB) is a wired high-speed serial bus for data communication.
Connects Devices such as keyboards, mice, scanners, printers, joysticks, audio devices, disks.
Facilitates transfers of data at 480 (USB 2.0 only), 12 or 1.5 Mb/s (megabits/second).
The USB communication system follows a star topology with a USB host at the centre and one
or more USB peripheral devices/USB hosts connected to it.
A USB 2.0 host can support connections up to 127, including slave peripheral devices and other
USB hosts
94
Universal Serial Bus ( USB) is a wired high-speed serial bus for data communication.
Connects Devices such as keyboards, mice, scanners, printers, joysticks, audio devices, disks.
Facilitates transfers of data at 480 (USB 2.0 only), 12 or 1.5 Mb/s (megabits/second).
The USB communication system follows a star topology with a USB host at the centre and one
or more USB peripheral devices/USB hosts connected to it.
A USB 2.0 host can support connections up to 127, including slave peripheral devices and other
USB hosts
94
The USB cable in USB 2.0 specification supports communication distance of up to 5 meters
▪Low-Speed: 10 – 100 kb/s
▪Full-Speed: 500 kb/s – 10 Mb/s 12 Mb/s signaling bit rate
▪High-Speed: 400 Mb/s
There exist two pre-defined connectors in any USB system - Type A and Type B (Mini/Micro
USB) Connectors.
▪Type A : Connects USB devices to a hub port (host)
▪Type B : Connects detachable devices (Slaves)
95
▪Low-Speed: 10 – 100 kb/s
▪Full-Speed: 500 kb/s – 10 Mb/s 12 Mb/s signaling bit rate
▪High-Speed: 400 Mb/s
There exist two pre-defined connectors in any USB system - Type A and Type B (Mini/Micro
USB) Connectors.
▪Type A : Connects USB devices to a hub port (host)
▪Type B : Connects detachable devices (Slaves)
95
IEEE 1394 (Firewire) 96
Assignment for you?
Assignment for you?
97
External Communication Interface
(wireless)
Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi),
Zigbee, GPRS
External Communication Interface
(wireless)
Infrared (IR), Bluetooth (BT), Wireless LAN (Wi-Fi),
Zigbee, GPRS
Infrared (IrDA)
Infrared ( IrDA) is a serial, half duplex, line of sight based wireless technology for data
communication between devices.
Infrared communication technique uses infrared waves of the electromagnetic spectrum for
transmitting the data (Ranges from 0.7µ to 1000µ or 0.1mm in the light spectrum)
IrDA supports point-point and point-to-multipoint communication, provided all devices involved in
the communication are within the line of sight.
Range for IrDA lies in the range 10 cm to 1 m.
Supports data rates ranging from 9600bits/second to 16Mbps
▪Serial infrared: 9600bps to 115.2 kbps
▪Medium infrared: 0.576Mbps to 1.152 Mbps
▪Fast infrared: 4Mbps
98
Infrared ( IrDA) is a serial, half duplex, line of sight based wireless technology for data
communication between devices.
Infrared communication technique uses infrared waves of the electromagnetic spectrum for
transmitting the data (Ranges from 0.7µ to 1000µ or 0.1mm in the light spectrum)
IrDA supports point-point and point-to-multipoint communication, provided all devices involved in
the communication are within the line of sight.
Range for IrDA lies in the range 10 cm to 1 m.
Supports data rates ranging from 9600bits/second to 16Mbps
▪Serial infrared: 9600bps to 115.2 kbps
▪Medium infrared: 0.576Mbps to 1.152 Mbps
▪Fast infrared: 4Mbps
98
Contd..
IrDA communication involves a transmitter unit for transmitting the data over IR and a receiver for
receiving the data.
Infrared Light Emitting Diode (LED) is the IR source for the transmitter and at the receiving end a
photodiode acts as the receiver.
Device operating on Infrared- The remote control of your TV, VCD player
IrDA communication has two essential parts; a physical link part and a protocol part.
▪The physical link is responsible for the physical transmission of data between devices supporting IR
communication. The physical link works on the wireless principle making use of Infrared for
communication.
▪The protocol part is responsible for defining the rules of communication.
99
IrDA communication involves a transmitter unit for transmitting the data over IR and a receiver for
receiving the data.
Infrared Light Emitting Diode (LED) is the IR source for the transmitter and at the receiving end a
photodiode acts as the receiver.
Device operating on Infrared- The remote control of your TV, VCD player
IrDA communication has two essential parts; a physical link part and a protocol part.
▪The physical link is responsible for the physical transmission of data between devices supporting IR
communication. The physical link works on the wireless principle making use of Infrared for
communication.
▪The protocol part is responsible for defining the rules of communication.
99
Bluetooth (BT)
Bluetooth is a low cost, low power, short range wireless technology for data and audio
communication.
First proposed by ‘Ericsson’ in 1994.
Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses the Frequency Hopping
Spread Spectrum (FHSS) technique for communication.
Supports a data rate of up to 1Mbps to 24Mbps
Like IrDA, Bluetooth communication also has two essential parts; a physical link part and a
protocol part.
▪The physical link is responsible for the physical transmission of data between devices
supporting Bluetooth communication
▪The protocol part is responsible for defining the rules of communication.
100
Bluetooth is a low cost, low power, short range wireless technology for data and audio
communication.
First proposed by ‘Ericsson’ in 1994.
Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses the Frequency Hopping
Spread Spectrum (FHSS) technique for communication.
Supports a data rate of up to 1Mbps to 24Mbps
Like IrDA, Bluetooth communication also has two essential parts; a physical link part and a
protocol part.
▪The physical link is responsible for the physical transmission of data between devices
supporting Bluetooth communication
▪The protocol part is responsible for defining the rules of communication.
100
Bluetooth-enabled devices essentially contain a Bluetooth wireless radio for the transmission and
reception of data.
The rules governing Bluetooth communication are implemented in the ‘Bluetooth protocol
stack’. The Bluetooth communication IC holds the stack.
Each Bluetooth device will have a 48-bit unique identification number.
Bluetooth communication follows packet-based data transfer.
Bluetooth supports point-to-point (device-to-device) and point-to-multipoint (device-to-multiple
device broadcasting) wireless communication.
The point-to-point communication follows the master-slave relationship.
A Bluetooth device can function as either a master or slave.
When a network is formed with one Bluetooth device as master and more than one device as
slave, it is called a Piconet. A Piconet supports a maximum of seven slave devices.
101Contd..
reception of data.
The rules governing Bluetooth communication are implemented in the ‘Bluetooth protocol
stack’. The Bluetooth communication IC holds the stack.
Each Bluetooth device will have a 48-bit unique identification number.
Bluetooth communication follows packet-based data transfer.
Bluetooth supports point-to-point (device-to-device) and point-to-multipoint (device-to-multiple
device broadcasting) wireless communication.
The point-to-point communication follows the master-slave relationship.
A Bluetooth device can function as either a master or slave.
When a network is formed with one Bluetooth device as master and more than one device as
slave, it is called a Piconet. A Piconet supports a maximum of seven slave devices.
101Contd..
Wi-Fi
Wi-Fi or Wireless Fidelity is the popular wireless communication technique for networked
communication of devices.
Wi-Fi follows the IEEE 802.11 standard.
Wi-Fi is intended for network communication and it supports Internet Protocol (IP) based
communication.
Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless Access point
to manage the communications.
The Wi-Fi router is responsible for restricting the access to a network, assigning IP address to devices
on the network, routing data packets to the intended devices on the network.
Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the form of
radio signals through an antenna. The hardware part of it is known as Wi-Fi Radio.
102
Wi-Fi or Wireless Fidelity is the popular wireless communication technique for networked
communication of devices.
Wi-Fi follows the IEEE 802.11 standard.
Wi-Fi is intended for network communication and it supports Internet Protocol (IP) based
communication.
Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless Access point
to manage the communications.
The Wi-Fi router is responsible for restricting the access to a network, assigning IP address to devices
on the network, routing data packets to the intended devices on the network.
Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the form of
radio signals through an antenna. The hardware part of it is known as Wi-Fi Radio.
102
Wi-Fi operates at 2.4GHz or 5GHz of radio spectrum and they co-exist with other ISM band devices
like Bluetooth.
A Wi-Fi network is identified with a Service Set Identifier (SSID). A Wi-Fi device can connect to a
network by selecting the SSID of the network and by providing the credentials if the network is security
enabled
Wi-Fi networks implements different security mechanisms for authentication and data transfer.
Wireless Equivalency Protocol (WEP), Wireless Protected Access (WPA) etc are some of the security
mechanisms supported by Wi-Fi networks in data communication
supports data rates ranging from 1Mbps to 1300Mbps
103Contd..
like Bluetooth.
A Wi-Fi network is identified with a Service Set Identifier (SSID). A Wi-Fi device can connect to a
network by selecting the SSID of the network and by providing the credentials if the network is security
enabled
Wi-Fi networks implements different security mechanisms for authentication and data transfer.
Wireless Equivalency Protocol (WEP), Wireless Protected Access (WPA) etc are some of the security
mechanisms supported by Wi-Fi networks in data communication
supports data rates ranging from 1Mbps to 1300Mbps
103Contd..
ZigBee
ZigBee is a low power, low cost, wireless network communication protocol based on the IEEE
802.15.4-2006 standard.
Targeted for low power, low data rate and secure applications for Wireless Personal Area Networking
(WPAN).
ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400 to 2.484 GHz,
902 to 928 MHz and 868.0 to 868.6 MHz.
Supports an operating distance of up to 100 metres and a data rate of 20 to 250Kbps.
Application areas
home & industrial automation, home control/security
energy management
medical/patient tracking
Automatic Meter Reading (AMR), smoke detectors, wireless telemetry,
HVAC control, heating control, lighting controls, environmental controls
104
ZigBee is a low power, low cost, wireless network communication protocol based on the IEEE
802.15.4-2006 standard.
Targeted for low power, low data rate and secure applications for Wireless Personal Area Networking
(WPAN).
ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400 to 2.484 GHz,
902 to 928 MHz and 868.0 to 868.6 MHz.
Supports an operating distance of up to 100 metres and a data rate of 20 to 250Kbps.
Application areas
home & industrial automation, home control/security
energy management
medical/patient tracking
Automatic Meter Reading (AMR), smoke detectors, wireless telemetry,
HVAC control, heating control, lighting controls, environmental controls
104
ZigBee Coordinator (ZC)/Network Coordinator
The ZigBee coordinator acts as the root of the ZigBee network. The ZC is responsible for initiating the
ZigBee network and it can store information about the network.
ZigBee Router (ZR)/Full Function on Device (FFD)
Responsible for passing information from one device to another device or to another ZR.
ZigBee End Device (ZED)/Reduced Function on Device (RFD)
End device containing ZigBee functionality for data communication. It can talk only with a ZR or ZC and
cannot act as a mediator for transferring data from one device to another.
105Contd..
The ZigBee coordinator acts as the root of the ZigBee network. The ZC is responsible for initiating the
ZigBee network and it can store information about the network.
ZigBee Router (ZR)/Full Function on Device (FFD)
Responsible for passing information from one device to another device or to another ZR.
ZigBee End Device (ZED)/Reduced Function on Device (RFD)
End device containing ZigBee functionality for data communication. It can talk only with a ZR or ZC and
cannot act as a mediator for transferring data from one device to another.
105Contd..
GPRS (General Packet Radio Service)
GPRS, 3G, 4G and LTE are cellular communication technique for transferring data over a mobile
communication network like GSM and CDMA.
The transmitting device splits the data into several related packets. At the receiving end the data is re-
constructed by combining the received data packets.
GPRS supports a maximum transfer rate of 171.2 kbps.
The radio channel is concurrently shared between several users instead of dedicating a radio channel
to a cell phone user.
The GPRS communication divides the channel into 8 timeslots and transmits data over the available
channel.
GPRS supports Internet Protocol (IP), Point to Point Protocol (PPP) and X.25 protocols for
communication.
GPRS is mainly used by mobile-enabled embedded devices for data communication.
The device should support the necessary GPRS hardware like a GPRS modem and GPRS radio.
106
GPRS, 3G, 4G and LTE are cellular communication technique for transferring data over a mobile
communication network like GSM and CDMA.
The transmitting device splits the data into several related packets. At the receiving end the data is re-
constructed by combining the received data packets.
GPRS supports a maximum transfer rate of 171.2 kbps.
The radio channel is concurrently shared between several users instead of dedicating a radio channel
to a cell phone user.
The GPRS communication divides the channel into 8 timeslots and transmits data over the available
channel.
GPRS supports Internet Protocol (IP), Point to Point Protocol (PPP) and X.25 protocols for
communication.
GPRS is mainly used by mobile-enabled embedded devices for data communication.
The device should support the necessary GPRS hardware like a GPRS modem and GPRS radio.
106
Services offered
GPRS extends the GSM Packet circuit switched data capabilities and makes the following services
possible
SMS messaging and broadcasting
"Always on" internet access
Multimedia messaging service (MMS)
Push-to-talk over cellular (PoC)
Instant messaging and presence-wireless village Internet applications for smart devices through
wireless application protocol (WAP).
Point-to-point (P2P) service: inter-networking with the Internet (IP).
Point-to-multipoint (P2M) service: point-to- multipoint multicast and point-to-multipoint group calls.
107Contd..
GPRS extends the GSM Packet circuit switched data capabilities and makes the following services
possible
SMS messaging and broadcasting
"Always on" internet access
Multimedia messaging service (MMS)
Push-to-talk over cellular (PoC)
Instant messaging and presence-wireless village Internet applications for smart devices through
wireless application protocol (WAP).
Point-to-point (P2P) service: inter-networking with the Internet (IP).
Point-to-multipoint (P2M) service: point-to- multipoint multicast and point-to-multipoint group calls.
107Contd..
108❖Elements of an embedded system
Reset Circuit
essential to ensure that the device is not operating at a voltage level where the device is not
guaranteed to operate, during system power ON
It brings the internal registers and the different hardware systems of the processor to a known state
starts the firmware execution from the reset vector (Normally from vector address 0x0000)
lt can be either active high or active low
The reset pulse should be wide enough to give time for the clock oscillator to stabilize before the
internal reset state starts.
standard Reset IC - MAX810
109
essential to ensure that the device is not operating at a voltage level where the device is not
guaranteed to operate, during system power ON
It brings the internal registers and the different hardware systems of the processor to a known state
starts the firmware execution from the reset vector (Normally from vector address 0x0000)
lt can be either active high or active low
The reset pulse should be wide enough to give time for the clock oscillator to stabilize before the
internal reset state starts.
standard Reset IC - MAX810
109
Brown out protection circuit
Prevents the processor from unexpected program execution behaviour when the supply voltage to the
processor falls below a specified voltage
holds the processor in the reset state
Built-in or external circuit using passive elements
Working:
Transistor conducts if VCC > (VBE +VZ)
The transistor stops conducting when the supply voltage falls below (VBE and Vz)
Microprocessor Supervisor IC - DS1232
110
Prevents the processor from unexpected program execution behaviour when the supply voltage to the
processor falls below a specified voltage
holds the processor in the reset state
Built-in or external circuit using passive elements
Working:
Transistor conducts if VCC > (VBE +VZ)
The transistor stops conducting when the supply voltage falls below (VBE and Vz)
Microprocessor Supervisor IC - DS1232
110
Oscillator unit
The instruction execution of a microprocessor occurs in sync with a clock signal.
Clock signal is generated using different types of oscillators
Can be built-in or externally built using ceramic resonator or quartz crystal.
The speed of operation of a processor is primarily dependent on the clock frequency
The total system power consumption is directly proportional to the clock frequency
111
The instruction execution of a microprocessor occurs in sync with a clock signal.
Clock signal is generated using different types of oscillators
Can be built-in or externally built using ceramic resonator or quartz crystal.
The speed of operation of a processor is primarily dependent on the clock frequency
The total system power consumption is directly proportional to the clock frequency
111
Real-Time Clock (RTC)
System component responsible for keeping track of time
RTC holds information like Current time (hours, minutes, and seconds) in 12-hour/24-hour format, date,
month, year, day of the week
Supplies timing reference to the system (in the absence of a power supply too)
RTC chip contains a microchip for holding time and date-related information and a backup battery cell
for functioning in the absence of power
For OS-based ES, timing is essential for synchronizing the operations of the OS kernel.
OS kernel can perform necessary operations like system date time updation, managing software
timers, etc when an RTC timer tick interrupt occurs
RTC can be configured to interrupt the processor at predefined intervals or to interrupt the processor
when RTC register reaches a specified value (used as alarm interrupt)
112
System component responsible for keeping track of time
RTC holds information like Current time (hours, minutes, and seconds) in 12-hour/24-hour format, date,
month, year, day of the week
Supplies timing reference to the system (in the absence of a power supply too)
RTC chip contains a microchip for holding time and date-related information and a backup battery cell
for functioning in the absence of power
For OS-based ES, timing is essential for synchronizing the operations of the OS kernel.
OS kernel can perform necessary operations like system date time updation, managing software
timers, etc when an RTC timer tick interrupt occurs
RTC can be configured to interrupt the processor at predefined intervals or to interrupt the processor
when RTC register reaches a specified value (used as alarm interrupt)
112
Watchdog Timer
Monitor the firmware execution and reset the
system processor when the program execution hangs up
It consists of a free running counter(either up/down counter)
in sync with the system clock pulse
WD timer increments or decrements a free-running counter with each clock pulse and generates a
reset signal to reset the processor if the count reaches zero for a down-counting watchdog or the
highest count value for an up-counting watchdog
If the WD counter is enabled, firmware can write a zero (for up-counting WD implementation) to it
before starting execution of code (subroutine or piece of code which is susceptible to execution hang
up) & WD will start counting
113
Monitor the firmware execution and reset the
system processor when the program execution hangs up
It consists of a free running counter(either up/down counter)
in sync with the system clock pulse
WD timer increments or decrements a free-running counter with each clock pulse and generates a
reset signal to reset the processor if the count reaches zero for a down-counting watchdog or the
highest count value for an up-counting watchdog
If the WD counter is enabled, firmware can write a zero (for up-counting WD implementation) to it
before starting execution of code (subroutine or piece of code which is susceptible to execution hang
up) & WD will start counting
113
Contd..
If the firmware execution doesn’t complete due to malfunctioning, within the time required by WD to
reach the maximum count, the counter will generate a reset pulse
This reset the processor (if the counter is connected to the reset line of the processor)
If firmware execution completes before the expiration of the WDT we can reset the count by writing a 0
to the WDT register (for up-counting WDT)
Most processors implement WD as a built-in component, provide a status register to control the WDT
(enabling and disabling function), and WDT register for writing the count value.
Else using external WDT IC circuit
DS1232- integrates a hardware WDT in it
114
If the firmware execution doesn’t complete due to malfunctioning, within the time required by WD to
reach the maximum count, the counter will generate a reset pulse
This reset the processor (if the counter is connected to the reset line of the processor)
If firmware execution completes before the expiration of the WDT we can reset the count by writing a 0
to the WDT register (for up-counting WDT)
Most processors implement WD as a built-in component, provide a status register to control the WDT
(enabling and disabling function), and WDT register for writing the count value.
Else using external WDT IC circuit
DS1232- integrates a hardware WDT in it
114
115
Arm Cortex Mx Processor family Overview: Features, Architecture,
Memory System, Exception and Interrupts, Low Power Features
Arm Cortex Mx Processor family Overview: Features, Architecture,
Memory System, Exception and Interrupts, Low Power Features
Block Diagram of the Cortex-M3 and Cortex-M4 processor 116
117Various Bus Interfaces
Various Bus Interfaces on the Cortex-M3 and Cortex-M4 Processors
Various Bus Interfaces on the Cortex-M3 and Cortex-M4 Processors
Memory system
The Cortex-M3 and M4 processors themselves do not include memories (i.e., they do not have
program memory, SRAM, or cache). Instead, they come with a generic on-chip bus interface, so
microcontroller vendors can add their own memory system to their design.
The bus interfaces on the Cortex-M processors are 32-bit, and based on the Advanced
Microcontroller Bus Architecture (AMBA) standard.
AMBA contains a collection of several bus protocol specifications.
The main bus interface protocol used by the Cortex-M3 and M4 processors is the AHB Lite (Advanced
High-performance Bus), which is used in program memory and system bus interfaces.
Another bus protocol used is the Advanced Peripheral Bus (APB) interface commonly used in the
peripheral systems of ARM-based microcontrollers.
In addition, the APB protocol is used inside the Cortex-M3 and Cortex-M4 processor for debug support.
118
The Cortex-M3 and M4 processors themselves do not include memories (i.e., they do not have
program memory, SRAM, or cache). Instead, they come with a generic on-chip bus interface, so
microcontroller vendors can add their own memory system to their design.
The bus interfaces on the Cortex-M processors are 32-bit, and based on the Advanced
Microcontroller Bus Architecture (AMBA) standard.
AMBA contains a collection of several bus protocol specifications.
The main bus interface protocol used by the Cortex-M3 and M4 processors is the AHB Lite (Advanced
High-performance Bus), which is used in program memory and system bus interfaces.
Another bus protocol used is the Advanced Peripheral Bus (APB) interface commonly used in the
peripheral systems of ARM-based microcontrollers.
In addition, the APB protocol is used inside the Cortex-M3 and Cortex-M4 processor for debug support.
118
Interrupts : Interrupt vs. Polling
A single microprocessor can serve several modules by:
Interrupt
When module needs service, it notifies the CPU by sending an interrupt signal. When the
CPU receives the signal the CPU interrupts whatever it is doing and services the module.
Polling
The CPU continuously monitors the status of a given module, when a particular status
condition is met the CPU then services the module.
A single microprocessor can serve several modules by:
Interrupt
When module needs service, it notifies the CPU by sending an interrupt signal. When the
CPU receives the signal the CPU interrupts whatever it is doing and services the module.
Polling
The CPU continuously monitors the status of a given module, when a particular status
condition is met the CPU then services the module.
Interrupts : Interrupt vs. Polling
Interrupt Polling
Interrupt Polling
Interrupts : Interrupt Service Routine
The function that gets executed when an interrupt occurs is called the Interrupt Service
Routine(ISR) or the Interrupt Handler
The function that gets executed when an interrupt occurs is called the Interrupt Service
Routine(ISR) or the Interrupt Handler
Interrupts : NVIC
Nested Vector Interrupt Controller (NVIC)
A dedicated hardware inside the
Cortex-Microcontroller
It is responsible for handling interrupts.
➢The Cortex-M3 and Cortex-M4 processors include an interrupt controller called the Nested
Vectored Interrupt Controller (NVIC).
➢It is programmable and its registers are memory mapped. The address location of the NVIC is
fixed and the programmer’s model of the NVIC is consistent across all Cortex-M processors.
Nested Vector Interrupt Controller (NVIC)
A dedicated hardware inside the
Cortex-Microcontroller
It is responsible for handling interrupts.
➢The Cortex-M3 and Cortex-M4 processors include an interrupt controller called the Nested
Vectored Interrupt Controller (NVIC).
➢It is programmable and its registers are memory mapped. The address location of the NVIC is
fixed and the programmer’s model of the NVIC is consistent across all Cortex-M processors.
Interrupts : NVIC
Interrupts : NVIC
➢Interrupts from the processor core are know as exceptions.
➢Interrupts from outside the processor core are known as hardware exceptions or
Interrupt Requests.
➢Interrupts from the processor core are know as exceptions.
➢Interrupts from outside the processor core are known as hardware exceptions or
Interrupt Requests.
Interrupts : The Vector Table
The vector table contains the addresses of the
Interrupt Handlers and Exception Handlers.
**Note: Entire Table can be refereed from the chapter
12 from RM407_ESDLab document
The vector table contains the addresses of the
Interrupt Handlers and Exception Handlers.
**Note: Entire Table can be refereed from the chapter
12 from RM407_ESDLab document
Interrupts : External Interrupt (EXTI) lines
GPIO pins are connected to EXTI lines
It possible to enable interrupt for any GPIO pin.
Multiple pins share the same EXTI line
Pin 0 of every Port is connected EXTIO_IRQ.
Pin 1 of every Port is connected EXTI1_IRQ.
Pin 2 of every Port is connected EXTI2_IRQ
Pin 3 of every Port is connected EXTI3_IRQ
This means we cannot have PB0 and PAO as
input interrupt pins at the same time since they
are connected to the same multiplexer i.e. EXTIO
Same for PC4 and PB4 at the same time, etc.
GPIO pins are connected to EXTI lines
It possible to enable interrupt for any GPIO pin.
Multiple pins share the same EXTI line
Pin 0 of every Port is connected EXTIO_IRQ.
Pin 1 of every Port is connected EXTI1_IRQ.
Pin 2 of every Port is connected EXTI2_IRQ
Pin 3 of every Port is connected EXTI3_IRQ
This means we cannot have PB0 and PAO as
input interrupt pins at the same time since they
are connected to the same multiplexer i.e. EXTIO
Same for PC4 and PB4 at the same time, etc.
Interrupts : External Interrupt (EXTI) lines
Pins 10 to 15 share the same IRQ inside the
NVIC and therefore are serviced by the same
Interrupt Service Routine (ISR)
Application code must be able to find which pin
from 10 to 15 generated the interrupt.
Pins 10 to 15 share the same IRQ inside the
NVIC and therefore are serviced by the same
Interrupt Service Routine (ISR)
Application code must be able to find which pin
from 10 to 15 generated the interrupt.
Interrupts : States
Disabled : This is the default state
Enabled : Interrupt is enabled
Pending : Waiting to be serviced
Active : Being serviced
Disabled : This is the default state
Enabled : Interrupt is enabled
Pending : Waiting to be serviced
Active : Being serviced
Interrupts : States- Pending vs. Active
ADC Interrupt fires at time t = 0.
This is indicated by F
Since there is no other interrupt, the pending
state is cleared and the interrupt becomes
active.
This is indicated by P
At time t=1 TIMER interrupt fires
This is indicated by F
Since it has a lower priority than the ADC
interrupt it remains in the pending state
At time t=3 ADC interrupt completes its
execution
Since there is no other interrupt with a
higher priority, the pending state of the
TIMER interrupt is cleared and the interrupt
becomes active.
This is indicated by P
ADC Interrupt fires at time t = 0.
This is indicated by F
Since there is no other interrupt, the pending
state is cleared and the interrupt becomes
active.
This is indicated by P
At time t=1 TIMER interrupt fires
This is indicated by F
Since it has a lower priority than the ADC
interrupt it remains in the pending state
At time t=3 ADC interrupt completes its
execution
Since there is no other interrupt with a
higher priority, the pending state of the
TIMER interrupt is cleared and the interrupt
becomes active.
This is indicated by P
Interrupts : Priorities
Priorities allow us to set which interrupt should execute first.
They also allow us to set which interrupt can interrupt which.
Priorities allow us to set which interrupt should execute first.
They also allow us to set which interrupt can interrupt which.
Interrupts : Vector Table and IRQ#
**Note: Entire Table can be refereed from the
chapter 12 from RM407_ESDLab document
**Note: Entire Table can be refereed from the
chapter 12 from RM407_ESDLab document
Interrupts : Priorities
Some interrupt priorities are defined by ARM, these cannot be
changed. E.g .:
RESET : Priority of -3
NMI : Priority of -2
HardFault : Priority of -1
Lower number = Higher priority
Some interrupt priorities are defined by ARM, these cannot be
changed. E.g .:
RESET : Priority of -3
NMI : Priority of -2
HardFault : Priority of -1
Lower number = Higher priority
❖Features
Performance
The Cortex-M processors deliver high performance in microcontroller products.
The three-stage pipeline allows most instructions, including multiply, to execute in a single cycle,
and at the same time allows high clock frequencies for microcontroller devices. (Up to 200MHz)
Multiple bus interfaces allow simultaneous instruction and data accesses to be performed.
The highly efficient instruction set allows complex operations to be carried out in a low numbers of
instructions.
Each instruction fetch is 32-bit, and most instructions are 16-bit. Therefore up to two instructions
can be fetched at a time, allowing extra bandwidth on the memory interface for better performance
and better energy efficiency.
133
Performance
The Cortex-M processors deliver high performance in microcontroller products.
The three-stage pipeline allows most instructions, including multiply, to execute in a single cycle,
and at the same time allows high clock frequencies for microcontroller devices. (Up to 200MHz)
Multiple bus interfaces allow simultaneous instruction and data accesses to be performed.
The highly efficient instruction set allows complex operations to be carried out in a low numbers of
instructions.
Each instruction fetch is 32-bit, and most instructions are 16-bit. Therefore up to two instructions
can be fetched at a time, allowing extra bandwidth on the memory interface for better performance
and better energy efficiency.
133
❖Features
Code density
The Thumb instruction set used on the ARM Cortex-M processors provides excellent code density
compared to other processor architectures
The code density of the Cortex-M processors is also better than many commonly used 16-bit and
32-bit architectures. There are also additional advantages
➢Thumb-2 technology allows 16-bit instructions and 32-bit instructions to work together without any state
switching overhead. Most simple operations can be carried out with a 16-bit instruction.
➢Various memory addressing modes for efficient data accesses
➢Multiple memory accesses can be carried out in a single instruction
➢Support for hardware divide instructions and Multiply-and-Accumulate (MAC) instructions exist in both
Cortex-M3 and Cortex-M4
➢Instructions for bit field processing in Cortex-M3/M4
➢Single Instruction, multiple data (SIMD) instruction support exists in Cortex-M4
➢Optional single precision floating point instructions are available in Cortex-M4
134
Code density
The Thumb instruction set used on the ARM Cortex-M processors provides excellent code density
compared to other processor architectures
The code density of the Cortex-M processors is also better than many commonly used 16-bit and
32-bit architectures. There are also additional advantages
➢Thumb-2 technology allows 16-bit instructions and 32-bit instructions to work together without any state
switching overhead. Most simple operations can be carried out with a 16-bit instruction.
➢Various memory addressing modes for efficient data accesses
➢Multiple memory accesses can be carried out in a single instruction
➢Support for hardware divide instructions and Multiply-and-Accumulate (MAC) instructions exist in both
Cortex-M3 and Cortex-M4
➢Instructions for bit field processing in Cortex-M3/M4
➢Single Instruction, multiple data (SIMD) instruction support exists in Cortex-M4
➢Optional single precision floating point instructions are available in Cortex-M4
134
❖Features
Low Power
The Cortex-M processors are designed for low power implementations.
Many Cortex-M3 and Cortex-M4 microcontroller products can run at under 200 mA/ MHz
(approximately 0.36 mW/MHz for a supply voltage of 1.8 volt) and some of them can even run at
under 100 mA/MHz.
The Cortex-M processors provide a number of low power features. These include multiple sleep
modes defined in the architecture, and integrated architectural clock gating support, which allows
clock circuits for parts of the processor to be deactivated when the section is not in use.
135
Low Power
The Cortex-M processors are designed for low power implementations.
Many Cortex-M3 and Cortex-M4 microcontroller products can run at under 200 mA/ MHz
(approximately 0.36 mW/MHz for a supply voltage of 1.8 volt) and some of them can even run at
under 100 mA/MHz.
The Cortex-M processors provide a number of low power features. These include multiple sleep
modes defined in the architecture, and integrated architectural clock gating support, which allows
clock circuits for parts of the processor to be deactivated when the section is not in use.
135
❖Features
Memory System
Total of 4GB of addressable memory space with linear 32-bit addressing, with no need to use
memory paging.
The predefined memory map allows processor designs to be optimized for Harvard bus
architecture, and allows easy access to memory-mapped peripherals (such as the NVIC) inside
the processors.
Support of little endian or big endian memory systems. The Cortex-M3/M4 processors can operate
in both little endian or big endian mode. (Mostly uses little endian)
136
Memory System
Total of 4GB of addressable memory space with linear 32-bit addressing, with no need to use
memory paging.
The predefined memory map allows processor designs to be optimized for Harvard bus
architecture, and allows easy access to memory-mapped peripherals (such as the NVIC) inside
the processors.
Support of little endian or big endian memory systems. The Cortex-M3/M4 processors can operate
in both little endian or big endian mode. (Mostly uses little endian)
136
❖Features
Memory protection unit
The MPU is a programmable device that monitors the bus transactions and needs to be
configured by software, typically an embedded OS.
The MPU can be used in various ways.
In common scenarios, an OS can set up the MPU to protect data used by the OS kernel and other
privileged tasks, preventing untrusted user programs from corrupting them.
The MPU can also be used to make memory regions read-only, to prevent accidental erasure of
data in SRAM or overwriting of instruction code.
By default the MPU is disabled and applications that do not require a memory protection feature
do not have to initialize it.
137
Memory protection unit
The MPU is a programmable device that monitors the bus transactions and needs to be
configured by software, typically an embedded OS.
The MPU can be used in various ways.
In common scenarios, an OS can set up the MPU to protect data used by the OS kernel and other
privileged tasks, preventing untrusted user programs from corrupting them.
The MPU can also be used to make memory regions read-only, to prevent accidental erasure of
data in SRAM or overwriting of instruction code.
By default the MPU is disabled and applications that do not require a memory protection feature
do not have to initialize it.
137
❖Features
Interrupt handling
The Cortex-M3 and Cortex-M4 processors come with a sophisticated interrupt controller called the
Nested Vectored Interrupt Controller (NVIC).
Supports up to 240 interrupt inputs, a Non-Maskable Interrupt (NMI) input, and a number of
system exceptions. Each interrupt (apart from the NMI) can be individually enabled or disabled.
The NVIC has a number of programmable registers. These registers are memory mapped, and
CMSIS-Core provides the required register definitions and access functions (API) for most
common interrupt control tasks.
The vector table, which holds the starting addresses of interrupts and system exceptions, is a part
of the system memory. By default the vector table is located at the beginning of the memory space
(address 0x0), but the vector table offset can be changed at runtime if needed.
138
Interrupt handling
The Cortex-M3 and Cortex-M4 processors come with a sophisticated interrupt controller called the
Nested Vectored Interrupt Controller (NVIC).
Supports up to 240 interrupt inputs, a Non-Maskable Interrupt (NMI) input, and a number of
system exceptions. Each interrupt (apart from the NMI) can be individually enabled or disabled.
The NVIC has a number of programmable registers. These registers are memory mapped, and
CMSIS-Core provides the required register definitions and access functions (API) for most
common interrupt control tasks.
The vector table, which holds the starting addresses of interrupts and system exceptions, is a part
of the system memory. By default the vector table is located at the beginning of the memory space
(address 0x0), but the vector table offset can be changed at runtime if needed.
138
❖Features
OS support and system level features
The Cortex-M3 and Cortex-M4 processors are designed to support embedded
OSs efficiently.
They have a built-in system tick timer called SysTick, which can be set up to
generate regular timer interrupts for OS timekeeping.
Since the SysTick timer is available in all Cortex-M3 and Cortex-M4 devices,
source code for the embedded OS can easily be used on all of these devices
without modification for device specific timers.
139
OS support and system level features
The Cortex-M3 and Cortex-M4 processors are designed to support embedded
OSs efficiently.
They have a built-in system tick timer called SysTick, which can be set up to
generate regular timer interrupts for OS timekeeping.
Since the SysTick timer is available in all Cortex-M3 and Cortex-M4 devices,
source code for the embedded OS can easily be used on all of these devices
without modification for device specific timers.
139
❖Features
Cortex-M4 specific features
The DSP extensions of the Cortex-M4 cover:
8-bit and 16-bit Single Instruction Multiple Data (SIMD) instructions. These instructions allow
multiple data operations to be carried out in parallel.
Single-cycle 16-bit, dual 16-bit, and 32-bit Multiply and Accumulate (MAC).
The MAC instructions in Cortex-M4 provide more options, including multiplication for various
combinations of upper and lower 16-bits in the registers and a SIMD version of 16-bit MAC.
In addition, the MAC operation can be carried out in a single cycle in the Cortex-M4 processor,
while in the Cortex-M3 it takes multiple cycles.
140
Cortex-M4 specific features
The DSP extensions of the Cortex-M4 cover:
8-bit and 16-bit Single Instruction Multiple Data (SIMD) instructions. These instructions allow
multiple data operations to be carried out in parallel.
Single-cycle 16-bit, dual 16-bit, and 32-bit Multiply and Accumulate (MAC).
The MAC instructions in Cortex-M4 provide more options, including multiplication for various
combinations of upper and lower 16-bits in the registers and a SIMD version of 16-bit MAC.
In addition, the MAC operation can be carried out in a single cycle in the Cortex-M4 processor,
while in the Cortex-M3 it takes multiple cycles.
140
Cortex-M4 specific features (cont.)
The optional floating point unit (FPU) in the Cortex-M4 covers:
A single precision floating point unit compliant to IEEE 754 standard. In order to support
floating point operations, the Cortex-M4 processor supports a number of floating point
instructions. There are also a number of instructions to convert between single precision and
half precision floating point data.
The floating point unit supports fused MAC operations; this allows better precision in the MAC
result.
The floating point unit can be disabled when not in use, allowing for a reduction in power
consumption.
141❖Features
The optional floating point unit (FPU) in the Cortex-M4 covers:
A single precision floating point unit compliant to IEEE 754 standard. In order to support
floating point operations, the Cortex-M4 processor supports a number of floating point
instructions. There are also a number of instructions to convert between single precision and
half precision floating point data.
The floating point unit supports fused MAC operations; this allows better precision in the MAC
result.
The floating point unit can be disabled when not in use, allowing for a reduction in power
consumption.
141❖Features
Ease of use
Compared to other 32-bit processor architectures, the Cortex-M processors are very easy to use.
The programmer’s model and the instruction set is very C-friendly. Therefore you can develop your
applications entirely in C code without using any assembly and yet very easily get high performance.
Most of the features of the Cortex-M3 and Cortex-M4 processors are controlled by memory-mapped
registers.
In the Cortex-M processors, interrupt handlers can be written as normal C functions.
Since interrupt prioritization and nesting of interrupts is handled by the NVIC and the exception entry is
vectored, there is no need to use the software to check which interrupt needs to be served, or to handle
nested interrupts explicitly.
All you need to do is to assign a priority level to each interrupt and system exception.
142❖Features
Compared to other 32-bit processor architectures, the Cortex-M processors are very easy to use.
The programmer’s model and the instruction set is very C-friendly. Therefore you can develop your
applications entirely in C code without using any assembly and yet very easily get high performance.
Most of the features of the Cortex-M3 and Cortex-M4 processors are controlled by memory-mapped
registers.
In the Cortex-M processors, interrupt handlers can be written as normal C functions.
Since interrupt prioritization and nesting of interrupts is handled by the NVIC and the exception entry is
vectored, there is no need to use the software to check which interrupt needs to be served, or to handle
nested interrupts explicitly.
All you need to do is to assign a priority level to each interrupt and system exception.
142❖Features
Debug support
Debugging the Cortex-M3 and Cortex-M4 processors can be handled by a JTAG
connection, or a two-wire interface called a Serial-Wire Debug (SWD) interface.
Both JTAG and SWD protocols are widely supported by many development tool vendors.
Trace information can be collected using a single wire Serial-Wire Viewer (SWV)
interface, or a trace port interface (typically 5-pin) if high-trace bandwidth is required (e.g.,
when instruction trace is used). The debug and trace interfaces can be combined into a
single connector.
143❖Features
Debugging the Cortex-M3 and Cortex-M4 processors can be handled by a JTAG
connection, or a two-wire interface called a Serial-Wire Debug (SWD) interface.
Both JTAG and SWD protocols are widely supported by many development tool vendors.
Trace information can be collected using a single wire Serial-Wire Viewer (SWV)
interface, or a trace port interface (typically 5-pin) if high-trace bandwidth is required (e.g.,
when instruction trace is used). The debug and trace interfaces can be combined into a
single connector.
143❖Features
❖Features
Scalability
Microcontrollers with multiple Cortex-M processors, such as LPC4300 from NXP.
High-end Digital Signal Processing devices with one or more Cortex-M processors as the main
processor and an additional DSP for the data processing engine. For example, the Concerto
product series from Texas Instruments, which combines a Cortex-M3 processor with a DSP
core.
Complex System-on-Chips with one or more Cortex-M processors as companion processors.
For example, the Texas Instrument OMAP5 combines a Cortex-A15 and two Cortex-M4
processors into a single device.
Complex System-on-Chips with one or more Cortex-M processors for power management and
system control, and for Finite State Machine (FSM) replacement.
Exclusive access instructions
Scalable debug support
Event communication interface
144
Scalability
Microcontrollers with multiple Cortex-M processors, such as LPC4300 from NXP.
High-end Digital Signal Processing devices with one or more Cortex-M processors as the main
processor and an additional DSP for the data processing engine. For example, the Concerto
product series from Texas Instruments, which combines a Cortex-M3 processor with a DSP
core.
Complex System-on-Chips with one or more Cortex-M processors as companion processors.
For example, the Texas Instrument OMAP5 combines a Cortex-A15 and two Cortex-M4
processors into a single device.
Complex System-on-Chips with one or more Cortex-M processors for power management and
system control, and for Finite State Machine (FSM) replacement.
Exclusive access instructions
Scalable debug support
Event communication interface
144
❖Features
Compatibility
One advantage of using the ARM Cortex-M3 and Cortex-M4 processors is that they have great
compatibility with a wide family of other ARM devices
145
Compatibility
One advantage of using the ARM Cortex-M3 and Cortex-M4 processors is that they have great
compatibility with a wide family of other ARM devices
145
Tags
Categories
GeneralDownload
Download Slideshow Get the original presentation fileQuick Actions
Statistics
- Views 27
- Slides 145
- Age 543 days
Related Slideshows
22
Pray For The Peace Of Jerusalem and You Will Prosper
RodolfoMoralesMarcuc
32 views
26
Don_t_Waste_Your_Life_God.....powerpoint
chalobrido8
35 views
31
VILLASUR_FACTORS_TO_CONSIDER_IN_PLATING_SALAD_10-13.pdf
JaiJai148317
32 views
14
Fertility awareness methods for women in the society
Isaiah47
30 views
35
Chapter 5 Arithmetic Functions Computer Organisation and Architecture
RitikSharma297999
29 views
5
syakira bhasa inggris (1) (1).pptx.......
ourcommunity56
30 views