Electronics 1 complete course plus guide. For complete course and more visit our website https://www.swebllc.com/?cat=12
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Language: en
Added: Nov 01, 2018
Slides: 41 pages
Slide Content
DC Biasing BJT
Biasing
Biasing:The DC voltages applied to a transistor in order to turn it on so
that it can amplify the AC signal.
Operating Point
The DC input establishes an
operating or quiescent point
called the Q-point.
The Three States of Operation
•Active or Linear Region Operation
Base–Emitter junction is forward biased
Base–Collector junction is reverse biased
•Cutoff Region Operation
Base–Emitter junction is reverse biased
•Saturation Region Operation
Base–Emitter junction is forward biased
Base–Collector junction is forward biased
DC Biasing Circuits
•Fixed-bias circuit
•Emitter-stabilized bias circuit
•Voltage divider bias circuit
•DC bias with voltage feedback
•Emitter Followerconfiguration
•Common base configuration
Fixed Bias
The Base-Emitter Loop
From Kirchhoff’s voltage law:
Solving for base current:
+V
CC–I
BR
B–V
BE= 0B
BECC
B
R
VV
I
Collector-Emitter Loop
Collector current:
From Kirchhoff’s voltage law: BII
C
CCCCCE
RIVV
Transistor Saturation
When the transistor is operating in saturation, current through the transistor
is at its maximum possible value.C
R
CC
V
Csat
I V 0
CE
V
Load Line Analysis
I
Csat
I
C= V
CC/ R
C
V
CE= 0 V
V
CEcutoff
V
CE= V
CC
I
C= 0 mA
•where the value of R
Bsets the value of
I
B
•that sets the values of V
CEand I
C
The Q-point is the operating point:
The end points of the load line are:
Circuit Values Affect the Q-Point
more …
Circuit Values Affect the Q-Point
more …
Circuit Values Affect the Q-Point
Emitter-Stabilized Bias Circuit
Adding a resistor (R
E) to
the emitter circuit
stabilizes the bias circuit.
Base-Emitter Loop
From Kirchhoff’s voltage law: 0R1)I(-RI-V
EBBBCC
0 RI-V-RI-
EEBEBBCC
V EB
BECC
B
1)R(R
V-V
I
Since I
E= (+ 1)I
B:
Solving for I
B:
Collector-Emitter Loop
From Kirchhoff’s voltage law:0
CC
V
C
R
C
I
CE
V
E
R
E
I
Since I
EI
C:)R (RI– V V
ECCCCCE
Also:EBEBRCCB
CCCCECEC
EEE
V V RI– V V
RI - V V V V
RI V
Improved Biased Stability
Stabilityrefers to a circuit condition in which the currents and voltages
will remain fairly constant over a wide range of temperatures and
transistor Beta () values.
Adding RE to the emitter improves the stability of a transistor.
Saturation Level
V
CEcutoff: I
Csat:
The endpoints can be determined from the load line.mA 0 I
V V
C
CCCE
E
R
C
R
CC
V
C
I
CE V 0V
Voltage Divider Bias
This is a very stable bias
circuit.
The currents and voltages
are nearly independent of
any variations in .
Exact Analysis
Exact Analysis (cont.)
Approximate Analysis
Where I
B<< I
1and I
1I
2 :
Where R
E> 10R
2:
From Kirchhoff’s voltage law: 21
CC2
B
RR
VR
V
E
E
E
R
V
I BEBE
VVV EECCCCCE
RI RI V V )R (RIV V
II
ECCCCCE
CE
Voltage Divider Bias Analysis
Transistor Saturation LevelEC
CC
CmaxCsat
RR
V
II
Load Line Analysis
Cutoff: Saturation:mA0I
VV
C
CCCE
V0V
CE
E
R
C
R
CC
V
C
I
DC Bias with Voltage Feedback/ Collector
Feedback Configuration
Another way to
improve the stability
of a bias circuit is to
add a feedback path
from collector to
base.
In this bias circuit
the Q-point is only
slightly dependent on
the transistor beta, .
Base-Emitter Loop )R(RR
VV
I
ECB
BECC
B
From Kirchhoff’s voltage law:0RI–V–RI–RI– V
EEBEBBCCCC
Where I
B<< I
C:C
I
B
I
C
I
C
I'
Knowing I
C= I
Band I
EI
C, the loop
equation becomes: 0RIVRIRI– V
EBBEBBCBCC
Solving for I
B:
Collector-Emitter Loop
Applying Kirchoff’s voltage law:
I
E+ V
CE+ I’
CR
C–V
CC= 0
Since I
CI
Cand I
C= I
B:
I
C(R
C+
RE) + V
CE–V
CC=0
Solving for V
CE:
V
CE= V
CC–I
C(R
C+ R
E)
Saturation Analysis
Transistor Saturation LevelEC
CC
CmaxCsat
RR
V
II
Load Line Analysis
Cutoff: Saturation:mA 0I
VV
C
CCCE
V 0V
CE
E
R
C
R
CC
V
C
I
Emitter follower Configuration
Voltage is taken off from collector
Saturation:
Emitter follower Configuration (cont.)
Common Base Configuration
Common Base Configuration (cont.)
Design Problem Example
Design Problem: Solution
Transistor Switching Networks
•Transistors with only the DC source applied can be used as electronic
switches.
•Transistors as inverters
Switching Circuit CalculationsC
CC
Csat
R
V
I dc
Csat
B
I
I
Vi = 5V
Saturation current:
To ensure saturation:
Vi= 0
Emitter-collector resistance
at saturation and cutoff:Csat
CEsat
sat
I
V
R CEO
CC
cutoff
I
V
R
Switching Time
Transistor switching times:dron
ttt fsoff
ttt
Rise time 10% to 90%r
t dt ft s
t
Delay time
Storage time
Fall time 90% to 10%
PNP Transistors
The analysis for pnptransistor biasing circuits is the same
as that for npntransistor circuits. The only difference is that
the currents are flowing in the opposite direction.
Troubleshooting Hints
•Approximate voltages
–V
BE.7 V for silicon transistors
–V
CE25% to 75% of V
CC
•Test for opens and shorts with an ohmmeter.
•Test the solder joints.
•Test the transistor with a transistor tester or a curve tracer.
•Note that the load or the next stage affects the transistor operation.