ENERGY-EFFICIENT DUAL-NODE-UPSET-RECOVERABL E 7T SRAM FOR LOW-POWER AEROSPACE APPLICATIONS.pptx

ENERGY-EFFICIENT
DUAL-NODE-UPSET-RECOVERABL
E 7T SRAM FOR LOW-POWER
AEROSPACE APPLICATIONS

1. E NERGY -E FFICIENT D UAL -N ODE -U PSET -R ECOVERABLE 7T SRAM FOR L OW -P OWER A EROSPACE A PPLICATIONS GUIDE NAME : Mr . MARI SELVAM.M ASST PROF DEPT OF ECE KARTHIKA . M (110719106010) NALLAREDDY VIJITHA (110719106021) POODI VASUDHA (110719106024) SR U THI GNANA PRIYA . D (110719106033)

2. ABSTRACT The progression of minimizing the size of the device and enlarging the density of the chip by using millions of transistors has become a firm challenge for researcher. The complex design has affected not only the power consumption but also the first time delay. Considering all the facts this research proposed a new 7T SRAM memory cell with better read performance.

3. LITERATURE SURVEY Year Author Title methodology 2022 Uma Maheshwar Janniekode A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications non-volatile; symmetric NVSRAM; memristor; RRAM; instant-on; SRAM 2021 P. Saraza-Canflanca Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation SRAM, PUF (Physical Unclonable Functions), reliability, power-up, aging 2020 Wendong Wang Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices (random number generator) TRNGG · NBTI · process variation · entropy

4. LITERATURE SURVEY Year Author Title methodology 2019 Prachi Sanvale An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network PPN based 10T SRAM, h double ended write, and single-ended read decoupled circuit 2018 Sina Sayyah Ensan A robust and low-power near-threshold SRAM in 10-nm FinFET technology Single-ended SRAM Near-threshold operation Low-power Write enhancement Process variation Monte Carlo simulation

5. EXISTING MODEL A low power S RA M cell is proposed, whose leakage power is slightly negligible compared to that conventional 12T SRAM cell. A less write stability is achieved for the existing cell then 12T SRAM cell with a slight in the stability. For low standby power applications the proposed cell is less suitable.

6. DRAWBACKS Higher power dissipation in the standby mode which affecting read & write stability . Power consumption , delay and stability of SRAM cell is higher compared to proposed system.

7. PROPOSED SYSTEM A new 7T SARM cell parallel attached with one of the ground transistor compared to conventional 6T SRAM cell. With this model leakage current can be minimized and also the delay time perform better with over writing data. With a bit high noise margin this proposed cell consumes a compatible area.

8. SRAM In SRAM, All data has been stored in flip-flop. Flip-flop contains the every bit of this Ram. Flip-flop uses 4-6 transistors for making a memory cell and its circuit do not need to refreshment continuously.  Due to  read and write operations , other two access transistors are used to handle the availability for memory cell. It needs 6 MOFSET (metal-oxide-semiconductor field-effect transistor) to hold per memory bit. 

9. OPERATION The circuit of 7T SRAM cell is made of two CMOS inverters that connected to cross coupled to each other with additional NMOS Transistor which connected to read line and having two pass NMOS transistors connected to bit lines and bit-lines bar respectively. Fig 1 shows circuit of 7T SRAM Cell, where the access transistors MN3 is connected to the word-line (WL) to perform the access write and MN4 is connected to the Read-line (R) to perform the read operations thought the column bit-lines (BL and BLB). Bit-lines act as I/O nodes carrying the data from SRAM cells to a sense amplifier during read operation, or from write in the memory cells during write operations. All transistors have minimum length ( Lmin =45nm according to used Technology), while their widths are typically design parameters. Word line is activated and data lines  C C �� is pre-changed to VDD.

10. The value of Wp1 and Wp2 defines PMOS transistors width and Wn1 and Wn2 defines the NMOS driver transistors width use in CMOS Invertors, while Wn3 and Wn4 is the access transistors width.

11. BLOCK DIAGRAM

12. 8T SRAM

13. 7 T SRAM

14. OUTPUT WAVEFORM

15. ANALYSIS gain = -6.0000e+002 VOLTAGE 5.00000 CURRENT -324.51898u POWER -1.62259m

16. ADVANTAGES The seven transistors per bit makes large amounts of SRAM storage. SRAM is the fast local RAM used on CPUs for cache or local stores. Power consumption, delay and stability of SRAM cell is much smaller compared to existing system.

17. TOOLS USED Tanner EDA 18nm Tecnology

18. APPLICATIONS Clock rate and power. Industrial and scientific subsystem, automotive electronics , and similar , contain static RAM. Digital cameras, cell phones, synthesizers ,etc.

19. REFERENCES Janniekode , U. M., Somineni , R. P., Khalaf , O. I., Itani , M. M., Chinna Babu , J., & Abdulsahib , G. M. (2022). A symmetric novel 8T3R non-volatile SRAM cell for embedded applications.  Symmetry ,  14 (4), 768. Saraza-Canflanca , P., Carrasco-Lopez, H., Santana- Andreo , A., Brox , P., Castro-Lopez, R., Roca, E., & Fernandez, F. V. (2021). Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation.  Microelectronics Reliability ,  118 , 114049. Wang, W., Guin , U., & Singh, A. (2020). Aging-resilient SRAM-based true random number generator for lightweight devices.  Journal of Electronic Testing ,  36 , 301-311.

20. Sanvale , P., Gupta, N., Neema , V., Shah, A. P., & Vishvakarma , S. K. (2019). An improved read-assist energy efficient single ended PPN based 10T SRAM cell for wireless sensor network.  Microelectronics Journal ,  92 , 104611. Ensan , S. S., Moaiyeri , M. H., & Hessabi , S. (2018). A robust and low-power near-threshold SRAM in 10-nm FinFET technology.  Analog integrated circuits and signal processing ,  94 , 497-506.

21. Thank You