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Mar 01, 2025
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About This Presentation
dd
Slide Content
Evolution of logic
complexity in Integrated
Circuit for information
technology services
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
complexity in Integrated
Circuit for information
technology services
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Evolution in logic complexity in Integrated circuits
❖Evolution of size in Integrated services
❖Prominent Information Technology services
❖Features of Integrated circuits
❖Evolution in logic complexity in Integrated circuits
❖Evolution of size in Integrated services
❖Prominent Information Technology services
❖Features of Integrated circuits
Evolution in logic complexity in IC’s
MSI
•Medium Scale Integration
•Introduced in 1967
•Logic Block per chip 20-200
LSI
•Large Scale Integration
•Introduced in 1972
•Logic Block per chip 200-2000
VLSI
•Very Large Scale Integration
•Introduced in 1978
•Logic Block per chip 2000-20000
ULSI
•Ultra Large Scale Integration
•Introduced in 1989
•Logic Block per chip 20000 >>
MSI
•Medium Scale Integration
•Introduced in 1967
•Logic Block per chip 20-200
LSI
•Large Scale Integration
•Introduced in 1972
•Logic Block per chip 200-2000
VLSI
•Very Large Scale Integration
•Introduced in 1978
•Logic Block per chip 2000-20000
ULSI
•Ultra Large Scale Integration
•Introduced in 1989
•Logic Block per chip 20000 >>
Evolution of size in Integrated services
Minimum feature Size in (µm)
4.0 –
3.5 –
3.0 –
2.5 –
2.0 –
1.5 –
1.0 –
0.5 –
0.0 –
Year
1975 1980 1985 1990 1995 2000
4.0
0.1
Minimum feature Size in (µm)
4.0 –
3.5 –
3.0 –
2.5 –
2.0 –
1.5 –
1.0 –
0.5 –
0.0 –
Year
1975 1980 1985 1990 1995 2000
4.0
0.1
Prominent Information Technology services
Year
1975 1980 1985 1990 1995 2000
Main Frame Computer Personal Computer Computer Network
Consumer Electronics Portable Computer
Data Communication Multi-media Application
Wireless/Cellular Data Communication
Speech Processing
Video on Demand
Year
1975 1980 1985 1990 1995 2000
Main Frame Computer Personal Computer Computer Network
Consumer Electronics Portable Computer
Data Communication Multi-media Application
Wireless/Cellular Data Communication
Speech Processing
Video on Demand
Features of Integrated circuits
❖Less area/volume
❖Less power consumption
❖Less testing requirement at system level
❖Higher reliability, mainly due to improved on chip interconnects
❖Higher speed, mainly due to reduced interconnection length
❖Significant cost savings
❖Less area/volume
❖Less power consumption
❖Less testing requirement at system level
❖Higher reliability, mainly due to improved on chip interconnects
❖Higher speed, mainly due to reduced interconnection length
❖Significant cost savings
VLSI design
Methodologies
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Methodologies
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Design Time
❖Performance analysis versus design time
❖Technology window
❖Design Time
❖Performance analysis versus design time
❖Technology window
Design Time of IC
❖Design Time of IC depends on follwing parameters
❑Design complexity
❑Performance level
❑Acceptablecost
Types of design - Full custom design requires all the
components to be designed and verified right from the
transistor level. This methodology is used for mass
production and to optimize area speed and power. Semi-
custom design are used when there is less time for
design and for less quantities. Most of the modules are
prebuilt and pretested.Additional components can be
integrated. This saves a design time but not that
optimized and cost-efficient for mass production.
❖Design Time of IC depends on follwing parameters
❑Design complexity
❑Performance level
❑Acceptablecost
Types of design - Full custom design requires all the
components to be designed and verified right from the
transistor level. This methodology is used for mass
production and to optimize area speed and power. Semi-
custom design are used when there is less time for
design and for less quantities. Most of the modules are
prebuilt and pretested.Additional components can be
integrated. This saves a design time but not that
optimized and cost-efficient for mass production.
Performance analysis versus design time
Circuit Performance
Design Time
Semi-custom Design
Full-custom Design
Less Opportunities
for performance
improvement
More Opportunities
for performance
improvement
Shorter design
time until
“maturity”
longer design time
until “maturity”
Circuit Performance
Design Time
Semi-custom Design
Full-custom Design
Less Opportunities
for performance
improvement
More Opportunities
for performance
improvement
Shorter design
time until
“maturity”
longer design time
until “maturity”
Technology Window
Circuit Performance
Time
Technology Window 1 Technology Window 2
Design DesignProduction Production
Circuit Performance
Time
Technology Window 1 Technology Window 2
Design DesignProduction Production
Semi Custom and Full
Custom design
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Custom design
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Full Custom DesignSemi Custom Design
1. Some commonly used design, layout, geometry and
placement of transistor is interfaced with given demand.
1. Complete design, layout, geometry, orientation and
placement of transistor is done designer
2. Design is completed with the use of multiple library.2. Entire design is made without use of any library.
3. Development time for design before maturity is less.3. Development time for design before maturity is more.
4. It has less opportunity for performance improvement4. It has more opportunity for performance improvement
5. Complete dependency on existing technology.5. Less dependency on existing technology.
6. Low cost6. High Cost
1. Some commonly used design, layout, geometry and
placement of transistor is interfaced with given demand.
1. Complete design, layout, geometry, orientation and
placement of transistor is done designer
2. Design is completed with the use of multiple library.2. Entire design is made without use of any library.
3. Development time for design before maturity is less.3. Development time for design before maturity is more.
4. It has less opportunity for performance improvement4. It has more opportunity for performance improvement
5. Complete dependency on existing technology.5. Less dependency on existing technology.
6. Low cost6. High Cost
Performance analysis versus design time
Circuit Performance
Design Time
Semi-custom Design
Full-custom Design
Less Opportunities
for performance
improvement
More Opportunities
for performance
improvement
Shorter design
time until
“maturity”
longer design time
until “maturity”
Circuit Performance
Design Time
Semi-custom Design
Full-custom Design
Less Opportunities
for performance
improvement
More Opportunities
for performance
improvement
Shorter design
time until
“maturity”
longer design time
until “maturity”
Semi Custom
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of Semicustom design
❖Classification of Semicustom design
❖Working of Different Semicustom design
❖Basics of Semicustom design
❖Classification of Semicustom design
❖Working of Different Semicustom design
Basics of Semicustom design
❖Thismethodisusedtoreducetimetomarket.
❖Here,wereducecostofdesigningofproduct.
❖Performanceofsemicustomdesignislowerthenfullcustomdesign.
❖Here,insemicustomdesign,weusereadilyavailableblock,design,
libraryormodules.
❖Thismethodisusedtoreducetimetomarket.
❖Here,wereducecostofdesigningofproduct.
❖Performanceofsemicustomdesignislowerthenfullcustomdesign.
❖Here,insemicustomdesign,weusereadilyavailableblock,design,
libraryormodules.
Classification of Semicustom design
Semicustom Design
Standard Cell Gate array Programmable devices
Semicustom Design
Standard Cell Gate array Programmable devices
Standard Cell
❖Here,weusestandardcelllibrary.
❖Atypicallibrarymaycontainafewhundredcellsincludinginverters,
NANDGates,NORGates,complexAOI/OAIGates,D-Latches,FFand
Counters.
❖Inlibrary,therearegates,withdifferentdrivingcapabilities,forexample,
standardsize,doublesizeandquadruplesize.
❖Weneedtousesizebasedoncurrentdrivingcapabilitiesandspeedof
device.
❖Designersendstheschematictofabricatorwhopreparesthemaskifthe
cellsarefromthelibrary.
❖Largerthelibrary,thelargerthecost.
❖Standardcellguaranteesthatitwillwork.
Advantages
❑Flexibledesign
❑Workswithanaloganddigitalfunction
❑Sophisticatedsystemcanbebuilteasily
Disdvantages
❑MaskCost
❖Here,weusestandardcelllibrary.
❖Atypicallibrarymaycontainafewhundredcellsincludinginverters,
NANDGates,NORGates,complexAOI/OAIGates,D-Latches,FFand
Counters.
❖Inlibrary,therearegates,withdifferentdrivingcapabilities,forexample,
standardsize,doublesizeandquadruplesize.
❖Weneedtousesizebasedoncurrentdrivingcapabilitiesandspeedof
device.
❖Designersendstheschematictofabricatorwhopreparesthemaskifthe
cellsarefromthelibrary.
❖Largerthelibrary,thelargerthecost.
❖Standardcellguaranteesthatitwillwork.
Advantages
❑Flexibledesign
❑Workswithanaloganddigitalfunction
❑Sophisticatedsystemcanbebuilteasily
Disdvantages
❑MaskCost
Gate Array
❖AGatearraycircuitisaprefabricatedcircuitwithnoparticular
function,inwhichtransistorsandotheractivedevicesareplacedat
regularpredefinedpositions.
❖Onlymasksformetallizationneedtobecreated.
Advantages
❑Reducesthemaskcost
❑Lesstimetomarket
Disadvantages
❑Sizeisfixed
❑Numberoftransistorarefixed
❑Metalheightisfix
❑2metallayerarepossible
❑Lowefficiency
❑Suitableforlowproductionvolume
❖AGatearraycircuitisaprefabricatedcircuitwithnoparticular
function,inwhichtransistorsandotheractivedevicesareplacedat
regularpredefinedpositions.
❖Onlymasksformetallizationneedtobecreated.
Advantages
❑Reducesthemaskcost
❑Lesstimetomarket
Disadvantages
❑Sizeisfixed
❑Numberoftransistorarefixed
❑Metalheightisfix
❑2metallayerarepossible
❑Lowefficiency
❑Suitableforlowproductionvolume
Programmable Logic Devices (PLD)
❖TherearevarietyofICavailableinthemarketthatcouldbe
programmedaccordingtospecification.
❖Somearchitecturearelistedhere
❑SPLD–SimpleProgrammablelogicaldevice
❑CPLD–Complexprogrammablelogicaldevice
❑FPGA–FieldprogrammableGateArray
❖TherearevarietyofICavailableinthemarketthatcouldbe
programmedaccordingtospecification.
❖Somearchitecturearelistedhere
❑SPLD–SimpleProgrammablelogicaldevice
❑CPLD–Complexprogrammablelogicaldevice
❑FPGA–FieldprogrammableGateArray
Hierarchy, Regularity,
Modularity & Locality
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Modularity & Locality
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Hierarchy
❖Itinvolvesdividingcomplexdesignintovariousmodulesand
submodules.
❖Thisdivisionisdoneuntilthecomplexityofsubmodulesisatan
understandablelevelofdetails.
❖Itinvolvesdividingcomplexdesignintovariousmodulesand
submodules.
❖Thisdivisionisdoneuntilthecomplexityofsubmodulesisatan
understandablelevelofdetails.
Regularity
❖Heredesignerdividesthehierarchyintosetsofsimilarbuilding
blocks.
❖Regularityisthedesignofarraystructuresconsistingofidentical
cells.
❖Regularitycanbethereatmanylevels,
❑Attransistorlevel
❑AtidenticalGATElevel
❑Atmicroblock
❑Atmacroblock
❖Heredesignerdividesthehierarchyintosetsofsimilarbuilding
blocks.
❖Regularityisthedesignofarraystructuresconsistingofidentical
cells.
❖Regularitycanbethereatmanylevels,
❑Attransistorlevel
❑AtidenticalGATElevel
❑Atmicroblock
❑Atmacroblock
Modularity
❖Modularitymeansvariousfunctionalblockshaswelldefined
functionsandinterfaces,sothat,theycanbeimplementedand
testedseparately.
❖Alltheblockscanbecombinedeasilyattheendofthedesign
processtoformlargesystem.
❖Modularitymeansvariousfunctionalblockshaswelldefined
functionsandinterfaces,sothat,theycanbeimplementedand
testedseparately.
❖Alltheblockscanbecombinedeasilyattheendofthedesign
processtoformlargesystem.
Locality
❖Localityensuresthattheinternalsofmodulesarenotvisibletoany
exteriorinterface.
❖Thisenablestheoutsideworldtotreateachmoduleasablockbox
withwelldefinedinputsandoutputs.
❖Localityensuresthattheinternalsofmodulesarenotvisibletoany
exteriorinterface.
❖Thisenablestheoutsideworldtotreateachmoduleasablockbox
withwelldefinedinputsandoutputs.
Package Technology
in IC
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
in IC
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Through hole Package
❖Surface Mount Package
❖Contactless Package
❖Through hole Package
❖Surface Mount Package
❖Contactless Package
Through Hole Package
❖OneormoreleadsgothroughholesofPCBandaresoldered
underneath.
❖Packagesaremadefromeitherplasticorceramic.
❖Inthoughholepackage,mainlytherethreecategories
1.SIP(SingleInlinePackage)
2.DIP(DualInlinePackage)
3.PGA(PinGridArray)
❖OneormoreleadsgothroughholesofPCBandaresoldered
underneath.
❖Packagesaremadefromeitherplasticorceramic.
❖Inthoughholepackage,mainlytherethreecategories
1.SIP(SingleInlinePackage)
2.DIP(DualInlinePackage)
3.PGA(PinGridArray)
SIP (Single In line Package)
❖ICpackagehavingsinglerowofleadsisSIP(SingleInlinePackage)
❖Ithaslessnumberofleadsinsingleraw.
❖ICpackagehavingsinglerowofleadsisSIP(SingleInlinePackage)
❖Ithaslessnumberofleadsinsingleraw.
DIP (Dual In line Package)
❖ICpackagehavingtworowsofleadsisDIP(DualInlinePackage)
❖DIP’saremostlyusedineducationalinstitutes.
❖ICpackagehavingtworowsofleadsisDIP(DualInlinePackage)
❖DIP’saremostlyusedineducationalinstitutes.
PGA (Package Grid Array)
❖ICpackagehavinggridarrangementofleads,isPGA
❖Theyoffersmorenumberofleads(atmax400pins).
❖ItisbetterthanDIP’sintermsofthermalconductivityandpower
dissipationcharacteristics.
❖ICpackagehavinggridarrangementofleads,isPGA
❖Theyoffersmorenumberofleads(atmax400pins).
❖ItisbetterthanDIP’sintermsofthermalconductivityandpower
dissipationcharacteristics.
Surface Mount Package
❖Unlikethroughholepackage,theleadsofsurfacemountpackagesare
mounteddirectlyonthesurfaceofPCB.
❖Theydonotgothroughholesorfitintoasocket.
❖Normally,leadsofSurfaceMountPackageisbentatananglenearfootto
aidsolderingtothesurfaceofPCB.
❖BGA(BallGridArray)
❑Ithasmetalballs
❑Itdoesnothavesolderableleads,
❑BylittlepressurewecanfixitonPCB
❑Ithasmanyterminals(56to1312)
❑Itcanhavepackagingfrommultipleside(onetofoursides)
❖Unlikethroughholepackage,theleadsofsurfacemountpackagesare
mounteddirectlyonthesurfaceofPCB.
❖Theydonotgothroughholesorfitintoasocket.
❖Normally,leadsofSurfaceMountPackageisbentatananglenearfootto
aidsolderingtothesurfaceofPCB.
❖BGA(BallGridArray)
❑Ithasmetalballs
❑Itdoesnothavesolderableleads,
❑BylittlepressurewecanfixitonPCB
❑Ithasmanyterminals(56to1312)
❑Itcanhavepackagingfrommultipleside(onetofoursides)
Contactless Package
❖ItdoesnothavephysicalcontactwithPCB.
❖Itdoesnothaveanyleads.
❖Itprovidesinformationwirelessly.
❖ItdoesnothavephysicalcontactwithPCB.
❖Itdoesnothaveanyleads.
❖Itprovidesinformationwirelessly.
VLSI Design Flow
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of VLSI Design flow
❖Flow Chart of VLSI Design flow
❖Domains of VLSI Design flow
❖Y chart of VLSI Design flow
❖Basics of VLSI Design flow
❖Flow Chart of VLSI Design flow
❖Domains of VLSI Design flow
❖Y chart of VLSI Design flow
Basics of VLSI Design Flow
❖Thedesignflowstartwithagivensetofspecificationor
requirements.
❖So,systemshouldgetdesignwithrespecttogivenspecifications.
❖Attheend,whenthedesiredspecificationsarenotmet,thedesign
hastobemodifiedandre-checkedseveraltimesuntilitmeetsthe
requiredspecifications.
❖Thedesignflowstartwithagivensetofspecificationor
requirements.
❖So,systemshouldgetdesignwithrespecttogivenspecifications.
❖Attheend,whenthedesiredspecificationsarenotmet,thedesign
hastobemodifiedandre-checkedseveraltimesuntilitmeetsthe
requiredspecifications.
Flow Chart of VLSI Design Flow
Design Specification
Architecture design
Gate level design
Circuit level design
HDL Coding
Simulation
Verification
Meets
Fabrication
Yes
No
Design Specification
Architecture design
Gate level design
Circuit level design
HDL Coding
Simulation
Verification
Meets
Fabrication
Yes
No
Domains of VLSI Design Flow
❖ThedesigndescriptionforaVLSIcircuitmaybedescribedinformsof
threedomains:
1.BehavioralDomain
2.StructuralDomain
3.PhysicalDomain
❖ThedesigndescriptionforaVLSIcircuitmaybedescribedinformsof
threedomains:
1.BehavioralDomain
2.StructuralDomain
3.PhysicalDomain
Y Chart of VLSI Design
Behavior
Domain
Structural
Domain
Physical Domain
AlgorithmSystem
Chip Floor plan
Finite State
Machine
Register
Modules
placement
Module
Description
Logic Gate
Cell placement
Boolean
Equation
Transistor
Mask
Behavior
Domain
Structural
Domain
Physical Domain
AlgorithmSystem
Chip Floor plan
Finite State
Machine
Register
Modules
placement
Module
Description
Logic Gate
Cell placement
Boolean
Equation
Transistor
Mask
Importance CAD tool
in VLSI design
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
in VLSI design
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of CAD tool in VLSI design
❖IC design process
❖IC fabrication process
❖Important feature of CAD tools in VLSI design
❖Basics of CAD tool in VLSI design
❖IC design process
❖IC fabrication process
❖Important feature of CAD tools in VLSI design
Basics of CAD tools in VLSI design flow
❖AsperMoore’sLaw,complexityofIC’sisincreasingovertheyears.
❖DesigningofVLSIcircuitwithmillionsoftransistorinsingleICis
beyondhumansbrain.
❖TodesignVLSIcircuit,Computerisrequiredtochecklayout,circuit
performance,processetc.
❖Computerareusedtoaidinthedesignandoptimizationprocess.
❖VLSIdesignersarenormallygivenasetofdesignrulesbasedon
giventechnology.
❖AsperMoore’sLaw,complexityofIC’sisincreasingovertheyears.
❖DesigningofVLSIcircuitwithmillionsoftransistorinsingleICis
beyondhumansbrain.
❖TodesignVLSIcircuit,Computerisrequiredtochecklayout,circuit
performance,processetc.
❖Computerareusedtoaidinthedesignandoptimizationprocess.
❖VLSIdesignersarenormallygivenasetofdesignrulesbasedon
giventechnology.
IC design process and IC fabrication process
Design Entry
Design Verification,
DRC, Simulation etc.
Pattern Generator
Pattern file
Produce mask
For each layer wafer
processing, deposit,
expose, develop etch
etc.
Package
Test
Design Entry
Design Verification,
DRC, Simulation etc.
Pattern Generator
Pattern file
Produce mask
For each layer wafer
processing, deposit,
expose, develop etch
etc.
Package
Test
Feature of VLSI CAD tools
❖VLSICADtoolshavefollowingtoolstomeetdesignfeatures:
1.Physicaldesign(Layout,editor,circuitschematics)
2.Physicalverification(DRC(designRuleCheck),circuitextractor,plotoutput,
visualchecking)
3.Behavioralverification.
❖VLSICADtoolshavefollowingtoolstomeetdesignfeatures:
1.Physicaldesign(Layout,editor,circuitschematics)
2.Physicalverification(DRC(designRuleCheck),circuitextractor,plotoutput,
visualchecking)
3.Behavioralverification.
Comparison of FPGA
and CPLD
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
and CPLD
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Comparison of FPGA and CPLD
FPGA CPLDParameters
1. Complex Programable Logic Design1. Field Programable Gate Array 1. Full Form
2. Based on “Logic Function”2. Based on “Look up table” 2. Architecture
3. Few blocks3. Around 100000 3. Blocks in Architecture
4. Course Grain Devices4. Fine Grain Devices 4. Architecture tuning
5. EPROM5. SRAM 5. Architectural Memory
6. Less6. High6. Complexity
7. Less 7. High7. Cost
8. Instant ON 8. It takes time to load program8. Time to ON
9. Program stays in CPLD9. Program lost once power is OFF9. Volatility of Program
10. Weaker Power Consumption10. Ideal Power Consumption10. Power Consumption
11. Easier to determine11. Complex to determine 11. Timing Analysis
FPGA CPLDParameters
1. Complex Programable Logic Design1. Field Programable Gate Array 1. Full Form
2. Based on “Logic Function”2. Based on “Look up table” 2. Architecture
3. Few blocks3. Around 100000 3. Blocks in Architecture
4. Course Grain Devices4. Fine Grain Devices 4. Architecture tuning
5. EPROM5. SRAM 5. Architectural Memory
6. Less6. High6. Complexity
7. Less 7. High7. Cost
8. Instant ON 8. It takes time to load program8. Time to ON
9. Program stays in CPLD9. Program lost once power is OFF9. Volatility of Program
10. Weaker Power Consumption10. Ideal Power Consumption10. Power Consumption
11. Easier to determine11. Complex to determine 11. Timing Analysis
On Chip Clock Generation
and Distribution
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
and Distribution
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of Clock in Digital Integrated circuits
❖Pierce Crystal oscillator
❖Generation of two non overlapping clocks
❖Y chart of VLSI Design flow
❖Basics of Clock in Digital Integrated circuits
❖Pierce Crystal oscillator
❖Generation of two non overlapping clocks
❖Y chart of VLSI Design flow
Basics of Clock in Digital Integrated Circuits
❖Clocksignalsaretheheartbeatsofdigitalsystems.So,stabilityof
clocksignalishighlyimportant.
❖Ideally,clocksignalshouldhaveminimumrisetime&falltime,it
shouldhavespecifieddutycyclesandzeroskew.
Rise Time Fall Time
Skew
❖Clocksignalsaretheheartbeatsofdigitalsystems.So,stabilityof
clocksignalishighlyimportant.
❖Ideally,clocksignalshouldhaveminimumrisetime&falltime,it
shouldhavespecifieddutycyclesandzeroskew.
Rise Time Fall Time
Skew
Basics of Clock in Digital Integrated Circuits
❖Practically,thereisnoticeablerisetimeandfalltime,Dutycyclescan
alsovary.
❖Infact,asmuchas10%ofamachinecycletimeusexpandedto
allowrealisticclockskewsinlargecomputersystem.
❖Onchipgeneratedclockcanbeprocessdependentandunstable.
❖Asaresult,usuallyseparateclockchipwhichusecrystaloscillators
havebeenusedforhighperformanceVLSIchip.
❖Practically,thereisnoticeablerisetimeandfalltime,Dutycyclescan
alsovary.
❖Infact,asmuchas10%ofamachinecycletimeusexpandedto
allowrealisticclockskewsinlargecomputersystem.
❖Onchipgeneratedclockcanbeprocessdependentandunstable.
❖Asaresult,usuallyseparateclockchipwhichusecrystaloscillators
havebeenusedforhighperformanceVLSIchip.
Pierce Crystal Oscillator
❖Inthiscrystal,seriesresonantexists.
❖Butinternalseriesresonant
determinestheoscillationfrequency.
❖Externalloadattheterminalshas
considerableeffectonitsfrequency
andfrequencystability.
❖Highertheseriesresistance,lower
theresonantfrequency.
❖Inthiscrystal,seriesresonantexists.
❖Butinternalseriesresonant
determinestheoscillationfrequency.
❖Externalloadattheterminalshas
considerableeffectonitsfrequency
andfrequencystability.
❖Highertheseriesresistance,lower
theresonantfrequency.
Generation of two non overlapping clock
❖Productoftwononoverlappingclockiszeroatalltimes.
Ck
Ck-1
Ck-2
❖Productoftwononoverlappingclockiszeroatalltimes.
Ck
Ck-1
Ck-2
Comparison of FPGA,
CPLD, PLC,
Microprocessor,
Microcontroller & DSP
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
CPLD, PLC,
Microprocessor,
Microcontroller & DSP
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
FPGA CPLDParameters PLC MP MC DSP
Field
Programmable
Gate Array
Complex
Programmable
Logic Device
1. Full Form
Programmable
Logic Control
MicroprocessorMicrocontroller
Digital Signal
Processor
Look up table Logical Blocks2. Architecture
CPU, IO port,
Memory
CPU, IO Port
Von Neumann
Mostly
Harvard
architecture
Real Time
Applications
(Fine Tuning)
Course Tuning
Applications
3. Applications
In Industries, at
high power &
high Temp.
Computer
Applications
Consumer
Electronics like
Camera,
Automobile
Real Time
Applications
(Fine Tuning)
Fast for real
time
Slow4. Response Slow
Optimized for
speed only
Slow
Fast for real
time
Very Good Moderate5. Immunity with noise Highest
Needs
additional setup
Low Good
Not designed for
Multitasking
Single Task6. Task Single Task Multitasking
Not designed
for Multitasking
Not designed
for Multitasking
It takes time to
get ON
Less Time (In
terms of mili
Sec)
7. Turn ON time
Less Time (In
terms of Mili
Sec)
It takes time to
get ON
Less Time (In
terms of Micro
Sec)
Less Time (In
terms of Neno
Sec)
Expensive Cheap8. Cost Expensive Expensive Cheap Expensive
Field
Programmable
Gate Array
Complex
Programmable
Logic Device
1. Full Form
Programmable
Logic Control
MicroprocessorMicrocontroller
Digital Signal
Processor
Look up table Logical Blocks2. Architecture
CPU, IO port,
Memory
CPU, IO Port
Von Neumann
Mostly
Harvard
architecture
Real Time
Applications
(Fine Tuning)
Course Tuning
Applications
3. Applications
In Industries, at
high power &
high Temp.
Computer
Applications
Consumer
Electronics like
Camera,
Automobile
Real Time
Applications
(Fine Tuning)
Fast for real
time
Slow4. Response Slow
Optimized for
speed only
Slow
Fast for real
time
Very Good Moderate5. Immunity with noise Highest
Needs
additional setup
Low Good
Not designed for
Multitasking
Single Task6. Task Single Task Multitasking
Not designed
for Multitasking
Not designed
for Multitasking
It takes time to
get ON
Less Time (In
terms of mili
Sec)
7. Turn ON time
Less Time (In
terms of Mili
Sec)
It takes time to
get ON
Less Time (In
terms of Micro
Sec)
Less Time (In
terms of Neno
Sec)
Expensive Cheap8. Cost Expensive Expensive Cheap Expensive
CMOS Fabrication
Process
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Process
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
nMOSand pMOSstructure on P Type Substrate
Create n well or p well
region and channel
stop region
❖FornMOSandpMOS,specialregionmustbecreatedinwhich
semiconductortypeisoppositetothesubstratetype,theseregion
arecalledwellsortubs.
❖pwelliscreatedinntypesubstrateandnwelliscreatedinptype
substrate.
❖nMOStransistorarecreatedinptypesubstrateorpwellandpMOS
transistorarecreatedinntypesubstrateornwell.
❖Thatwellshouldbeofdefinedboundarytohavefixedchannelstop
region.
❖ThickOxideisgrowninactiveregionofnMOSandpMOS.
❖Thethingateoxideisgrownonthesurfacethroughthermal
oxidation.
❖Aspercircuitmakeapatternofpolysiliconlayer.
❖Afterthatcreaten+andp+regionsforsource,drainandsubstrate.
❖Finalmetallizationformetalinterconnects.
Grow field oxide (Thick
Oxide) and gate oxide
(Thin Oxide)
Deposit and pattern
polysilicon layer
Implant source, drain
region and substrate
contacts
Create contact
windows, deposit and
pattern metal layer
region and channel
stop region
❖FornMOSandpMOS,specialregionmustbecreatedinwhich
semiconductortypeisoppositetothesubstratetype,theseregion
arecalledwellsortubs.
❖pwelliscreatedinntypesubstrateandnwelliscreatedinptype
substrate.
❖nMOStransistorarecreatedinptypesubstrateorpwellandpMOS
transistorarecreatedinntypesubstrateornwell.
❖Thatwellshouldbeofdefinedboundarytohavefixedchannelstop
region.
❖ThickOxideisgrowninactiveregionofnMOSandpMOS.
❖Thethingateoxideisgrownonthesurfacethroughthermal
oxidation.
❖Aspercircuitmakeapatternofpolysiliconlayer.
❖Afterthatcreaten+andp+regionsforsource,drainandsubstrate.
❖Finalmetallizationformetalinterconnects.
Grow field oxide (Thick
Oxide) and gate oxide
(Thin Oxide)
Deposit and pattern
polysilicon layer
Implant source, drain
region and substrate
contacts
Create contact
windows, deposit and
pattern metal layer
nMOSand pMOSon P Type Substrate
Twin Tube Fabrication
Process
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Process
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Basics of Twin tube fabrication process
❖Inourpreviousvideo,IhaveexplainednMOSandpMOSstructureonPTypeSubstrate.
❖Inthat,therecanbeissuesregarding,mutualcouplinginbetweennMOSandpMOS.
❖Therecanbemajorissuesregarding,LatchupforCMOSfabrication.
❖Toavoidthoseissues,weshouldfabricationnMOSandpMOSbytwintubefabrication
process.
❖Inourpreviousvideo,IhaveexplainednMOSandpMOSstructureonPTypeSubstrate.
❖Inthat,therecanbeissuesregarding,mutualcouplinginbetweennMOSandpMOS.
❖Therecanbemajorissuesregarding,LatchupforCMOSfabrication.
❖Toavoidthoseissues,weshouldfabricationnMOSandpMOSbytwintubefabrication
process.
❖LetususenTypesubstrate.
❖Theresistivityofsubstrateshouldbehigher.
❖Highertheresistivitylesserthecurrent
throughsubstrate.
n –Type Substrate
n –Type Substrate
Epitaxial Layer
❖Thenweshouldgrown+layerepitaxially.
❖Thatishavinglesserresistancecomparedto
substrate.
n –Type Substrate
Epitaxial Layer
SiO2 Layer
❖Afterthat,substrateissubjectedtooxidation
andwegrowSiO2layer.
❖Theresistivityofsubstrateshouldbehigher.
❖Highertheresistivitylesserthecurrent
throughsubstrate.
n –Type Substrate
n –Type Substrate
Epitaxial Layer
❖Thenweshouldgrown+layerepitaxially.
❖Thatishavinglesserresistancecomparedto
substrate.
n –Type Substrate
Epitaxial Layer
SiO2 Layer
❖Afterthat,substrateissubjectedtooxidation
andwegrowSiO2layer.
n –Type Substrate
Epitaxial Layer
SiO2 Layer
❖SiO2layerisetchedusingmasking.
❖Twowindowsareformed,Oneforn-welland
anotherforp-well.
n –Type Substrate
Epitaxial Layer
SiO2 Layer
Photoresist mask
P+ diffusion
P well ❖1
st
windowiscoveredbyphotoresistmask.
❖Thenptypeimpuritiesdiffusedtoformp
well.
Epitaxial Layer
SiO2 Layer
❖SiO2layerisetchedusingmasking.
❖Twowindowsareformed,Oneforn-welland
anotherforp-well.
n –Type Substrate
Epitaxial Layer
SiO2 Layer
Photoresist mask
P+ diffusion
P well ❖1
st
windowiscoveredbyphotoresistmask.
❖Thenptypeimpuritiesdiffusedtoformp
well.
Photoresist mask
N+ diffusion
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p well
❖2
nd
windowiscoveredbyphotoresistmask.
❖Thenntypeimpuritiesdiffusedtoformn
well.
n well
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
❖GrowThinSiO2layerbythermaloxidation
forGateterminal
❖GrowPolysiliconlayerforphotolithography
andpatternmaking.
N+ diffusion
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p well
❖2
nd
windowiscoveredbyphotoresistmask.
❖Thenntypeimpuritiesdiffusedtoformn
well.
n well
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
❖GrowThinSiO2layerbythermaloxidation
forGateterminal
❖GrowPolysiliconlayerforphotolithography
andpatternmaking.
❖EachSiO2andPolysilicontoimplantDrain
andSource.
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
Photoresist mask
p+ diffusion
❖pwellcoveredwithphotoresistmaskandp+
diffusionisdonetoformsourceanddrain
region
p+ p+
andSource.
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
Photoresist mask
p+ diffusion
❖pwellcoveredwithphotoresistmaskandp+
diffusionisdonetoformsourceanddrain
region
p+ p+
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
Photoresist mask
n+ diffusion
❖nwellcoveredwithphotoresistmaskandn+
diffusionisdonetoformsourceanddrain
region
p+ p+ n+ n+
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
p+ p+ n+ n+
❖Metaldiffusionisdoneforcontact
formation.
❖Metaletchingisdone.
❖ContactformationsforsourceS,DrainDand
GateGisdone
S G D S G D
Epitaxial Layer
SiO2 Layer
p welln well
Photoresist mask
n+ diffusion
❖nwellcoveredwithphotoresistmaskandn+
diffusionisdonetoformsourceanddrain
region
p+ p+ n+ n+
n –Type Substrate
Epitaxial Layer
SiO2 Layer
p welln well
p+ p+ n+ n+
❖Metaldiffusionisdoneforcontact
formation.
❖Metaletchingisdone.
❖ContactformationsforsourceS,DrainDand
GateGisdone
S G D S G D
Two Terminal MOS
and it’s Energy band
diagram
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
and it’s Energy band
diagram
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of MOS
❖Two terminal MOS structure
❖MOS substrate basic properties
❖Energy band diagram of p type substrate
❖Energy band diagram of MOS structure
❖Energy Band diagram of Combined MOS structure
❖Basics of MOS
❖Two terminal MOS structure
❖MOS substrate basic properties
❖Energy band diagram of p type substrate
❖Energy band diagram of MOS structure
❖Energy Band diagram of Combined MOS structure
Basics of MOS
❖FullformofMOSis‘MetalOxideSemiconductor’.
❖ComparedtoBJT,itoccupylessspace.Soitismoresuitablefor
integratedcircuits.
❖Atgateterminal,ifvoltageisapplied,itcreateschannelfor
conductioninbetweenDRAINandSOURCEterminal.
❖Conductionisonlydependsonmajoritycarrieronly.
❖FullformofMOSis‘MetalOxideSemiconductor’.
❖ComparedtoBJT,itoccupylessspace.Soitismoresuitablefor
integratedcircuits.
❖Atgateterminal,ifvoltageisapplied,itcreateschannelfor
conductioninbetweenDRAINandSOURCEterminal.
❖Conductionisonlydependsonmajoritycarrieronly.
Two Terminal MOS structure
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
�Substrate Voltage
❖ByAddingimpuritieslikeBORON
(Trivalent)inpuresemiconductor,
wemakePtypematerial.
❖SiO2layerisactinglikeadielectric
layer.Thatformscapacitorin
betweengateandsubstrate.
❖Thicknessisthereinorderof10nm
to50nm.
❖Externalvoltageisappliedin
betweengateandsubstrate
terminal,whichwilljustifycarrier
concentrationforchannel.
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
�Substrate Voltage
❖ByAddingimpuritieslikeBORON
(Trivalent)inpuresemiconductor,
wemakePtypematerial.
❖SiO2layerisactinglikeadielectric
layer.Thatformscapacitorin
betweengateandsubstrate.
❖Thicknessisthereinorderof10nm
to50nm.
❖Externalvoltageisappliedin
betweengateandsubstrate
terminal,whichwilljustifycarrier
concentrationforchannel.
MOS substrate basic properties
❖AtequilibriumasperMassActionLaw
❖Where,n&pareelectrons&holesconcentration,respectively.
❖�
??????isintrinsiccarrierconcentration,itsvalueatroomtemperature
300Kisapproximately1.45×10
10
1/??????�
−3
.
❖Here,wehavesubstrateofacceptorconcentration??????
??????(inorderof
10
15
to10
16
??????�
−3
),soholesandelectronsconcentrationisgivenby,
??????�=??????
??????
�
�=�
�
??????=
??????
??????
�
�
�
❖AtequilibriumasperMassActionLaw
❖Where,n&pareelectrons&holesconcentration,respectively.
❖�
??????isintrinsiccarrierconcentration,itsvalueatroomtemperature
300Kisapproximately1.45×10
10
1/??????�
−3
.
❖Here,wehavesubstrateofacceptorconcentration??????
??????(inorderof
10
15
to10
16
??????�
−3
),soholesandelectronsconcentrationisgivenby,
??????�=??????
??????
�
�=�
�
??????=
??????
??????
�
�
�
Energy Band diagram of P Type substrate
�
??????valance Band
�
??????Conduction
Band
Band gap 1.1eV
❖Thebandgapinbetweenconductionbandandvalance
bandis1.1eV.
�
??????Intrinsic Fermi
Level
�
�Fermi Level
�??????
�
❖Fermi potential ??????
�, is based on intrinsic Fermi Level �
??????
and Fermi level �
�
??????
�=
�
�−�
??????
�
❖Forptypesemiconductor,Fermipotentialcanbe
approximatedby
??????
��=
??????�
�
????????????
??????
??????
�
�
❖Forntypesemiconductor,Fermipotentialcanbe
approximatedby
??????
��=
??????�
�
????????????
�
�
??????
??????
Free Space
�??????
❖Electronaffinityis�??????,whichisenergygapinbetween
conductionbandandFreespace.
❖Energyrequiredtomoveelectronfromfermileveltofree
spaceisworkfunction�??????
�.
�??????
??????=�??????+(�
�−�
�)
�
??????valance Band
�
??????Conduction
Band
Band gap 1.1eV
❖Thebandgapinbetweenconductionbandandvalance
bandis1.1eV.
�
??????Intrinsic Fermi
Level
�
�Fermi Level
�??????
�
❖Fermi potential ??????
�, is based on intrinsic Fermi Level �
??????
and Fermi level �
�
??????
�=
�
�−�
??????
�
❖Forptypesemiconductor,Fermipotentialcanbe
approximatedby
??????
��=
??????�
�
????????????
??????
??????
�
�
❖Forntypesemiconductor,Fermipotentialcanbe
approximatedby
??????
��=
??????�
�
????????????
�
�
??????
??????
Free Space
�??????
❖Electronaffinityis�??????,whichisenergygapinbetween
conductionbandandFreespace.
❖Energyrequiredtomoveelectronfromfermileveltofree
spaceisworkfunction�??????
�.
�??????
??????=�??????+(�
�−�
�)
Energy band diagram of MOS structure
Oxide
�
??????valance Band
�
??????Conduction Band
Band gap 8eV
�??????=�.??????�????????????
�
�Fermi Level
�??????
�=�.�????????????
Metal Al
�??????=�.��????????????
Semiconductor Si
Oxide
�
??????valance Band
�
??????Conduction Band
Band gap 8eV
�??????=�.??????�????????????
�
�Fermi Level
�??????
�=�.�????????????
Metal Al
�??????=�.��????????????
Semiconductor Si
Energy band Diagram of combined MOS structure
❖WhenwecombinedthethreeMOSmaterial,fermilevelmustlinedupin
singlelineandFreespacemustbecontinuous.
❖Becauseofworkfunctiondifferenceinbetweensemiconductorandmetal,
thereisvoltagedropacrossMOSandbandingofbands.
�
�Fermi Level
Semiconductor SiOxideMetal Al
�
??????Conduction Band
�
??????Intrinsic Level
�
??????Valance Band
❖WhenwecombinedthethreeMOSmaterial,fermilevelmustlinedupin
singlelineandFreespacemustbecontinuous.
❖Becauseofworkfunctiondifferenceinbetweensemiconductorandmetal,
thereisvoltagedropacrossMOSandbandingofbands.
�
�Fermi Level
Semiconductor SiOxideMetal Al
�
??????Conduction Band
�
??????Intrinsic Level
�
??????Valance Band
Flat Band Voltage
and Example on Flat
Band Voltage
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
and Example on Flat
Band Voltage
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Basics of Flat Band Voltage
❖IndividuallythereisadifferentworkfunctionwithMetal,SiO2and
Substrate.
❖Whenwecombinethreelayers,Becauseofworkfunctiondifference
betweenmetalandsemiconductor,voltagedropoccursacrossthe
MOSstructure.
❖PartofthisvoltageappearsacrossSiO2layerandrestacrossthe
siliconsurface.
❖Thisresultsintobandingofenergybands.
❖So,togetenergybandwithoutanybanding,voltagerequiredis
referredasflatbandvoltage
❖IndividuallythereisadifferentworkfunctionwithMetal,SiO2and
Substrate.
❖Whenwecombinethreelayers,Becauseofworkfunctiondifference
betweenmetalandsemiconductor,voltagedropoccursacrossthe
MOSstructure.
❖PartofthisvoltageappearsacrossSiO2layerandrestacrossthe
siliconsurface.
❖Thisresultsintobandingofenergybands.
❖So,togetenergybandwithoutanybanding,voltagerequiredis
referredasflatbandvoltage
ConsidertheMOSstructurethatconsistsofaptypedopedSisubstrate,aSiO2layerandametal(Al)
gate.TheequilibriumFermipotentialofthedopedSisubstrateis�??????
��=�.�????????????.Usingelectron
affinityforSi&workfunctionforAlgiveninfigure,Calculatethebuiltinpotentialdifferenceacross
MOSsystem.
❖Work Function for Si
∴�??????
??????=�??????+(�
�−�
�)
∴�??????
??????=�.��+(�.��+�.�)
∴�??????
??????=�.�????????????
❖Soworkfunctiondifference
inbetweenmetaland
substrateisgivenby
∴�??????
??????−�??????
??????=�.�−�.�
∴�??????
??????−�??????
??????=−�.�????????????
❖Soifvoltagecorrespondingtothisisappliedexternallybetweengateandsubstratethenthebandingofenergybands
canbecompensatedandenergybandsbecomeflat.Soflatbandvoltageisgivenby
∴??????
��=??????
??????−??????
??????
gate.TheequilibriumFermipotentialofthedopedSisubstrateis�??????
��=�.�????????????.Usingelectron
affinityforSi&workfunctionforAlgiveninfigure,Calculatethebuiltinpotentialdifferenceacross
MOSsystem.
❖Work Function for Si
∴�??????
??????=�??????+(�
�−�
�)
∴�??????
??????=�.��+(�.��+�.�)
∴�??????
??????=�.�????????????
❖Soworkfunctiondifference
inbetweenmetaland
substrateisgivenby
∴�??????
??????−�??????
??????=�.�−�.�
∴�??????
??????−�??????
??????=−�.�????????????
❖Soifvoltagecorrespondingtothisisappliedexternallybetweengateandsubstratethenthebandingofenergybands
canbecompensatedandenergybandsbecomeflat.Soflatbandvoltageisgivenby
∴??????
��=??????
??????−??????
??????
MOS under External
Bias
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Bias
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Basics of External biasing to MOS
❖Here,weapplyexternalbiastoMOSbyGatevoltage??????
??????and
substratevoltage??????
??????.
❖Herewekeep,??????
??????=0(constant)and??????
??????ascontrollingvoltage.
❖Dependingonthepolarityandmagnitudeof??????
??????,MOSfunctionsin
threedifferentregions.
❑Accumulation
❑Depletion
❑Inversion
❖Here,weapplyexternalbiastoMOSbyGatevoltage??????
??????and
substratevoltage??????
??????.
❖Herewekeep,??????
??????=0(constant)and??????
??????ascontrollingvoltage.
❖Dependingonthepolarityandmagnitudeof??????
??????,MOSfunctionsin
threedifferentregions.
❑Accumulation
❑Depletion
❑Inversion
Condition 1 : ??????
�<??????and ??????
??????=??????Accumulation
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
??????Substrate Voltage
??????
�<??????
??????
??????=??????
Holes accumulated on the surface
�
???????????? �
????????????
❖Herecarrierconcentrationbecomeslargeronsurface,thisis
calledaccumulationofcarrieronthesurface.
❖Here,electronconcentrationgoesdeeperinsideduetonegative
potential
�
??????valance Band
�
??????Conduction
Band
�
??????Intrinsic Fermi
Level
�
�Fermi Level
OxideMetal Al Semiconductor Si
????????????
�
�<??????and ??????
??????=??????Accumulation
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
??????Substrate Voltage
??????
�<??????
??????
??????=??????
Holes accumulated on the surface
�
???????????? �
????????????
❖Herecarrierconcentrationbecomeslargeronsurface,thisis
calledaccumulationofcarrieronthesurface.
❖Here,electronconcentrationgoesdeeperinsideduetonegative
potential
�
??????valance Band
�
??????Conduction
Band
�
??????Intrinsic Fermi
Level
�
�Fermi Level
OxideMetal Al Semiconductor Si
????????????
�
Condition 1 : ??????
�>??????(small) and ??????
??????=??????Depletion
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
??????Substrate Voltage
??????
�>??????
??????
??????=??????
�
???????????? �
????????????
❖Herecarrierconcentration(holes)willmovedeeplyinsidePtype
material,andthatformsdepletionregionneartosurfaceofoxidelayer.
�
??????valance Band
�
??????Conduction
Band
�
??????Intrinsic Fermi
Level
�
�Fermi Level
OxideMetal Al Semiconductor Si
????????????
�
Depletion Region
�>??????(small) and ??????
??????=??????Depletion
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
??????Substrate Voltage
??????
�>??????
??????
??????=??????
�
???????????? �
????????????
❖Herecarrierconcentration(holes)willmovedeeplyinsidePtype
material,andthatformsdepletionregionneartosurfaceofoxidelayer.
�
??????valance Band
�
??????Conduction
Band
�
??????Intrinsic Fermi
Level
�
�Fermi Level
OxideMetal Al Semiconductor Si
????????????
�
Depletion Region
Condition 1 : ??????
�>??????(Large) and ??????
??????=??????Inversion
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
??????Substrate Voltage
??????
�>??????
??????
??????=??????
�
???????????? �
????????????
❖ForLargegatevoltage,electronswillmakelayeratsurfaceofoxide,whichis
oppositetoptypesubstrate,thatiscalledsurfaceinversion.
❖Belowelectrons,therewilldepletionlayer.
❖Aftersomevoltage,depletionlayerwillnotincreaseandelectronswill
increase.
�
??????valance Band
�
??????Conduction
Band
�
??????Intrinsic Fermi
Level
�
�Fermi Level
OxideMetal Al Semiconductor Si
????????????
�
Electrons
Depletion Region
�>??????(Large) and ??????
??????=??????Inversion
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
??????Substrate Voltage
??????
�>??????
??????
??????=??????
�
???????????? �
????????????
❖ForLargegatevoltage,electronswillmakelayeratsurfaceofoxide,whichis
oppositetoptypesubstrate,thatiscalledsurfaceinversion.
❖Belowelectrons,therewilldepletionlayer.
❖Aftersomevoltage,depletionlayerwillnotincreaseandelectronswill
increase.
�
??????valance Band
�
??????Conduction
Band
�
??????Intrinsic Fermi
Level
�
�Fermi Level
OxideMetal Al Semiconductor Si
????????????
�
Electrons
Depletion Region
Thickness of depletion
region, Depletion region
charge density and Surface
Inversion in MOS structure
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
region, Depletion region
charge density and Surface
Inversion in MOS structure
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
??????
�>??????(small) and ??????
�=??????Depletion region
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
�Substrate Voltage
??????
�>??????
??????
�=??????
�
???????????? �
????????????
❖Herewewillcalculatedepletion
width??????
??????asafunctionofsurface
potential??????
??????.
❖Mobileholechargeinathin
horizontallayerparalleltothe
surfaceis
Depletion Region
X
????????????=−????????????
�????????????
??????
??????
❖Thechangeinsurfacepotential
requiredtodisplacethincharge
dQbydistance??????
??????canbe
calculatedbyPoissonequation.
????????????=−??????.
????????????
??????
????????????
????????????=
????????????
�??????????????????
??????
????????????
❖Inintegration,dxvariesfrom0to
??????
??????andpotentialvariesfrom
Fermipotential??????
�tosurface
potential??????
??????.
∴න
??????�
????????????
????????????=න
??????
????????????????????????
�??????????????????
??????
????????????
∴??????
??????−??????
�=
????????????
�??????
??????
??????
????????????
????????????
❖Sodepthofdepletionregionis
∴??????
??????=
????????????
????????????(??????
??????−??????
�)
????????????
�
❖Sodepletionregionchargedensity
isgivenby
∴??????=−????????????
�??????
??????
∴??????=−??????????????????
�??????
????????????(??????
??????−??????
�)
❖Nowifwefurtherincreasethe
gatevoltagethenitwillstartto
createsurfaceinversionby
attractingelectrons.
�>??????(small) and ??????
�=??????Depletion region
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
�Substrate Voltage
??????
�>??????
??????
�=??????
�
???????????? �
????????????
❖Herewewillcalculatedepletion
width??????
??????asafunctionofsurface
potential??????
??????.
❖Mobileholechargeinathin
horizontallayerparalleltothe
surfaceis
Depletion Region
X
????????????=−????????????
�????????????
??????
??????
❖Thechangeinsurfacepotential
requiredtodisplacethincharge
dQbydistance??????
??????canbe
calculatedbyPoissonequation.
????????????=−??????.
????????????
??????
????????????
????????????=
????????????
�??????????????????
??????
????????????
❖Inintegration,dxvariesfrom0to
??????
??????andpotentialvariesfrom
Fermipotential??????
�tosurface
potential??????
??????.
∴න
??????�
????????????
????????????=න
??????
????????????????????????
�??????????????????
??????
????????????
∴??????
??????−??????
�=
????????????
�??????
??????
??????
????????????
????????????
❖Sodepthofdepletionregionis
∴??????
??????=
????????????
????????????(??????
??????−??????
�)
????????????
�
❖Sodepletionregionchargedensity
isgivenby
∴??????=−????????????
�??????
??????
∴??????=−??????????????????
�??????
????????????(??????
??????−??????
�)
❖Nowifwefurtherincreasethe
gatevoltagethenitwillstartto
createsurfaceinversionby
attractingelectrons.
??????
�>??????(Large) and ??????
�=??????Inversion Region
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
�Substrate Voltage
??????
�>??????
??????
�=??????
�
???????????? �
????????????
Electrons
Depletion Region
❖Whensurfaceinversiontakesplace,thedensityof
mobileelectronsonthesurfaceequalstothedensity
ofholesintheptype.
❖Conditionforthatisgivenby(??????
??????=−??????
�)
❖Nowifwefurtherincreasegatevoltage??????
�then
widthofdepletionregionwillnotincreasebutit
increasethenumberofelectrons.
❖Somaximumdepletionregiondepthcanbe
calculatedby
∴??????
????????????=
????????????
????????????(????????????
�)
????????????
�
❖Sothiscreationofinversionlayerbyexternally
appliedgatevoltageisusedforchannelcreationin
MOSFET,Whichisusedforcurrentconductionin
betweendrainandsource.
�>??????(Large) and ??????
�=??????Inversion Region
P Type Si Substrate
Oxide SiO2
Metal
Gate G Terminal
??????
�Gate Voltage
Substrate Terminal
??????
�Substrate Voltage
??????
�>??????
??????
�=??????
�
???????????? �
????????????
Electrons
Depletion Region
❖Whensurfaceinversiontakesplace,thedensityof
mobileelectronsonthesurfaceequalstothedensity
ofholesintheptype.
❖Conditionforthatisgivenby(??????
??????=−??????
�)
❖Nowifwefurtherincreasegatevoltage??????
�then
widthofdepletionregionwillnotincreasebutit
increasethenumberofelectrons.
❖Somaximumdepletionregiondepthcanbe
calculatedby
∴??????
????????????=
????????????
????????????(????????????
�)
????????????
�
❖Sothiscreationofinversionlayerbyexternally
appliedgatevoltageisusedforchannelcreationin
MOSFET,Whichisusedforcurrentconductionin
betweendrainandsource.
MOS Transistor
MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of MOS Transistor
❖Types of MOS Transistor
❖Structure of n channel MOSFET
❖Working of n channel MOSFET
❖Basics of MOS Transistor
❖Types of MOS Transistor
❖Structure of n channel MOSFET
❖Working of n channel MOSFET
Basics of MOS Transistor
❖ItisMOSFET(MetalOxidSemiconductorFieldEffectTransistor)
❖Ithasfourterminals:Gate,Substrate,DrainandSource.
❖ThisdeviceisformedusingMOSstructure.
❖StructureofMOStransistorissymmetricaltodrainandsource
terminal.
❖ItisMOSFET(MetalOxidSemiconductorFieldEffectTransistor)
❖Ithasfourterminals:Gate,Substrate,DrainandSource.
❖ThisdeviceisformedusingMOSstructure.
❖StructureofMOStransistorissymmetricaltodrainandsource
terminal.
Types of MOS Transistor
❖TherearetwotypesofMOStransistorbasedonchannel.
❑EnhancementtypeMOSTransistor:Ithasnoconductingchannel
regionatzerogatebiasvoltage.
❑DepletiontypeMOSTransistor:Ithasconductingchannelregion
atzerogatebiasvoltage.
❖TherearetwotypesofMOStransistorbasedonchannel.
❑EnhancementtypeMOSTransistor:Ithasnoconductingchannel
regionatzerogatebiasvoltage.
❑DepletiontypeMOSTransistor:Ithasconductingchannelregion
atzerogatebiasvoltage.
Structure of n Channel MOSFET
P Type Si Substrate
Oxide SiO2
Metal
Gate G
Substrate
Source n+ Drain n+
Source S Drain D
Channel Length L
P Type Si Substrate
Oxide SiO2
Metal
Gate G
Substrate
Source n+ Drain n+
Source S Drain D
Channel Length L
Working of n Channel MOSFET in cut off region
??????
??????�<??????
�??????
Depletion Region
??????
??????�<??????
�??????
Depletion Region
Working of n Channel MOSFET cut off region
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
Working of n Channel MOSFET in Linear region
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
??????
??????small
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
??????
??????small
Working of n Channel MOSFET threshold of
linear region
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
??????
??????=??????
??????�??????�
Pinch off Point
linear region
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
??????
??????=??????
??????�??????�
Pinch off Point
Working of n Channel MOSFET in saturation
region
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
??????
??????>??????
??????�??????�
Pinch off Point
region
??????
??????�>??????
�??????
Depletion Region
Inversion Layer (Channel)
??????
??????>??????
??????�??????�
Pinch off Point
Threshold Voltage of
MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of Threshold Voltage of MOSFET
❖Parameters of Threshold Voltage of MOSFET
❖Derivation of Threshold Voltage of MOSFET
❖Basics of Threshold Voltage of MOSFET
❖Parameters of Threshold Voltage of MOSFET
❖Derivation of Threshold Voltage of MOSFET
Basics of Threshold Voltage of MOSFET
❖Itisaminimumvoltage??????
????????????(GatetoSource)requiredtoform
inversionlayer(channel)inbetweensourceanddrain.
❖ThresholdvoltagedefinesoperationofMOSFET.
❖If??????
????????????islessthanthresholdvoltagethenMOSFETwillstayincutoff
region.
❖Itisaminimumvoltage??????
????????????(GatetoSource)requiredtoform
inversionlayer(channel)inbetweensourceanddrain.
❖ThresholdvoltagedefinesoperationofMOSFET.
❖If??????
????????????islessthanthresholdvoltagethenMOSFETwillstayincutoff
region.
Parameters of Threshold Voltage in MOSFET
❖Therearefourphysicalparameterswhicheffectsthe
thresholdvoltageofMOSstructure:
❑Workfunctiondifferencebetweengateandthechannel.
❑Thegatevoltagecomponenttochangesurfacepotential.
❑Thegatevoltagecomponenttooffsetthedepletionregion
charge.
❑Thevoltagecomponenttooffsetthefixedchargesinthegate
oxideandinthesiliconoxideinterface.
❖Therearefourphysicalparameterswhicheffectsthe
thresholdvoltageofMOSstructure:
❑Workfunctiondifferencebetweengateandthechannel.
❑Thegatevoltagecomponenttochangesurfacepotential.
❑Thegatevoltagecomponenttooffsetthedepletionregion
charge.
❑Thevoltagecomponenttooffsetthefixedchargesinthegate
oxideandinthesiliconoxideinterface.
Derivation of Threshold Voltage in MOSFET
❖Workfunctiondifference??????
��inbetweenthegateand
thechannelisgivenby
??????
��=??????
���������??????−??????
�(�??????��??????)
??????
��=??????
���������??????−??????
�(���??????��????????????�??????????????????���)
❖Forsurfaceinversion,surfacepotentialshouldchange
form??????
�to−??????
�.Sonetchangewillbe−??????
�−??????
�=
−????????????
�.
❖Whenvoltageisappliedatgate,itrepelledholesdeeper
insidesubstrate,anditformsdepletionregion.This
regionhasionswhichformsoffsetvoltageduetocharges
ofionsnearthesurface.
❖Sodepletionregionchargedensityatsurfaceinversion
(??????
�=−??????
�)isgivenby
??????
��=−??????��
�??????
�??????−????????????
�
❖Ifsubstratebiasisgivenwith??????
��thendepletionregion
chargedensityisgivenby
??????
�=−??????��
�??????
�??????−????????????
�+??????
��
❖So,thecomponentofvoltagewhichnullifythevaluewill
be−??????
�/�
�??????,where�
�??????isgateoxidecapacitanceper
unitarea.
❖Thereisalsofixedpositivechargedensity??????
�??????,itisdue
tolatticeimperfectionsattheinterface.
❖Sotheforthcomponentforthresholdvoltagewillbe
−??????
�??????/�
�??????.
❖So,forzerosubstratebias,thresholdvoltageisgivenby
??????
��=??????
��−????????????
�−
??????
��
�
�??????
−
??????
�??????
�
�??????
❖Fornonzerosubstratebias,thresholdvoltageisgivenby
??????
�=??????
��−????????????
�−
??????
�
�
�??????
−
??????
�??????
�
�??????
??????
�=??????
��−????????????
�−
??????
��
�
�??????
−
??????
�??????
�
�??????
−
??????
�−??????
��
�
�??????
??????
�=??????
��−
??????
�−??????
��
�
�??????
❖Here,
??????
�−??????
��
�
�??????
=
−??????��
�??????
�??????
�
�??????
(−????????????
�+??????
��−−????????????
�)
❖SoThresholdvoltageisgivenby
??????
�=??????
��+??????(−????????????
�+??????
��−−????????????
�)
❖Where,ϒissubstratebiasor
bodyeffectcoefficient
??????=
??????��
�??????
�??????
�
�??????
��inbetweenthegateand
thechannelisgivenby
??????
��=??????
���������??????−??????
�(�??????��??????)
??????
��=??????
���������??????−??????
�(���??????��????????????�??????????????????���)
❖Forsurfaceinversion,surfacepotentialshouldchange
form??????
�to−??????
�.Sonetchangewillbe−??????
�−??????
�=
−????????????
�.
❖Whenvoltageisappliedatgate,itrepelledholesdeeper
insidesubstrate,anditformsdepletionregion.This
regionhasionswhichformsoffsetvoltageduetocharges
ofionsnearthesurface.
❖Sodepletionregionchargedensityatsurfaceinversion
(??????
�=−??????
�)isgivenby
??????
��=−??????��
�??????
�??????−????????????
�
❖Ifsubstratebiasisgivenwith??????
��thendepletionregion
chargedensityisgivenby
??????
�=−??????��
�??????
�??????−????????????
�+??????
��
❖So,thecomponentofvoltagewhichnullifythevaluewill
be−??????
�/�
�??????,where�
�??????isgateoxidecapacitanceper
unitarea.
❖Thereisalsofixedpositivechargedensity??????
�??????,itisdue
tolatticeimperfectionsattheinterface.
❖Sotheforthcomponentforthresholdvoltagewillbe
−??????
�??????/�
�??????.
❖So,forzerosubstratebias,thresholdvoltageisgivenby
??????
��=??????
��−????????????
�−
??????
��
�
�??????
−
??????
�??????
�
�??????
❖Fornonzerosubstratebias,thresholdvoltageisgivenby
??????
�=??????
��−????????????
�−
??????
�
�
�??????
−
??????
�??????
�
�??????
??????
�=??????
��−????????????
�−
??????
��
�
�??????
−
??????
�??????
�
�??????
−
??????
�−??????
��
�
�??????
??????
�=??????
��−
??????
�−??????
��
�
�??????
❖Here,
??????
�−??????
��
�
�??????
=
−??????��
�??????
�??????
�
�??????
(−????????????
�+??????
��−−????????????
�)
❖SoThresholdvoltageisgivenby
??????
�=??????
��+??????(−????????????
�+??????
��−−????????????
�)
❖Where,ϒissubstratebiasor
bodyeffectcoefficient
??????=
??????��
�??????
�??????
�
�??????
Gradual Channel
Approximation, Drain
Current Equation &
MOSFET Characteristics
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Approximation, Drain
Current Equation &
MOSFET Characteristics
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Gradual Channel Approximation in MOSFET
�
??????�>�
�??????
Depletion Region
Inversion Layer (Channel)
�
��small
X
Y
Y=0 Y=L
�
??????�>�
�??????
Depletion Region
Inversion Layer (Channel)
�
��small
X
Y
Y=0 Y=L
❖�
??????�>�
�??????and�
??????�>�
�??????,toformachannel.
�
��=??????=�
�=??????
❖ElectricfieldcomponentinYdirectionisdominant
comparedtoXdirection,socurrentflowonlyconfinedin
Ydirection.
�
??????(�)=−�
??????��
??????�−�
��−�
�??????
❖ChannelVoltage�
�(??????)willchangewithrespecttoY.
❖Thresholdvoltage�
�??????isassumedtobeconstant.
�
��=??????=�
��
❖Let�
??????(�)isthechargedensityinchannel,
❖Netvoltageatsourceis(�
??????�−�
�??????)maximumandNet
voltageatdrainis(�
??????�−�
��−�
�??????)minimum.So,fordy
thickness,wewillcalculationincrementalresistancedR.
??????�=−
????????????
�.??????
??????.�
??????(�)
❖Channelcurrentdensityisassumedtobeconstant,??????
�
currentflowsfromsourcetodrain.SoasperOhm’slaw
??????�
�=??????
�.??????�=−
??????
�
�.??????
??????.�
??????�
.????????????
∴න
??????
??????
??????
�.????????????=−�.??????
??????න
??????
���
�
??????�.??????�
�
❖Here,ychangesfrom0toLand�
�changesfrom0to�
��
∴??????
�.??????=�.??????
??????.�
??????�න
??????
���
[�
??????�−�
�−�
�??????].??????�
�
∴??????
�=
??????
??????.�
??????�
??????
.
�
??????
??????�
??????�−�
�??????�
��−�
��
??????
??????�>�
�??????and�
??????�>�
�??????,toformachannel.
�
��=??????=�
�=??????
❖ElectricfieldcomponentinYdirectionisdominant
comparedtoXdirection,socurrentflowonlyconfinedin
Ydirection.
�
??????(�)=−�
??????��
??????�−�
��−�
�??????
❖ChannelVoltage�
�(??????)willchangewithrespecttoY.
❖Thresholdvoltage�
�??????isassumedtobeconstant.
�
��=??????=�
��
❖Let�
??????(�)isthechargedensityinchannel,
❖Netvoltageatsourceis(�
??????�−�
�??????)maximumandNet
voltageatdrainis(�
??????�−�
��−�
�??????)minimum.So,fordy
thickness,wewillcalculationincrementalresistancedR.
??????�=−
????????????
�.??????
??????.�
??????(�)
❖Channelcurrentdensityisassumedtobeconstant,??????
�
currentflowsfromsourcetodrain.SoasperOhm’slaw
??????�
�=??????
�.??????�=−
??????
�
�.??????
??????.�
??????�
.????????????
∴න
??????
??????
??????
�.????????????=−�.??????
??????න
??????
���
�
??????�.??????�
�
❖Here,ychangesfrom0toLand�
�changesfrom0to�
��
∴??????
�.??????=�.??????
??????.�
??????�න
??????
���
[�
??????�−�
�−�
�??????].??????�
�
∴??????
�=
??????
??????.�
??????�
??????
.
�
??????
??????�
??????�−�
�??????�
��−�
��
??????
❖Here,ifconsider,??????
′
=??????
??????.�
??????�,thendraincurrentwillbe
∴??????
�=
??????′
??????
.
�
??????
??????�
??????�−�
�??????�
��−�
��
??????
❖Here,ifconsider,??????=??????′
�
??????
,thendraincurrentwillbe
∴??????
�=
??????
??????
??????�
??????�−�
�??????�
��−�
��
??????
❖Thisequationofdraincurrent??????
�isvalidinlinearregionof
MOSFET.
❖InsaturationregionofMOSFET,
∴�
��≥�
��??????�=�
??????�−�
�??????
❖Soforsaturationregiondraincurrent??????
�willbe
∴??????
��??????�=
??????
??????
??????�
??????�−�
�??????(�
??????�−�
�??????)−(�
??????�−�
�??????)
??????
∴??????
��??????�=
??????
??????
.(�
??????�−�
�??????)
??????
∴??????
��??????�=
??????
??????.�
??????�
??????
.
�
??????
.(�
??????�−�
�??????)
??????
′
=??????
??????.�
??????�,thendraincurrentwillbe
∴??????
�=
??????′
??????
.
�
??????
??????�
??????�−�
�??????�
��−�
��
??????
❖Here,ifconsider,??????=??????′
�
??????
,thendraincurrentwillbe
∴??????
�=
??????
??????
??????�
??????�−�
�??????�
��−�
��
??????
❖Thisequationofdraincurrent??????
�isvalidinlinearregionof
MOSFET.
❖InsaturationregionofMOSFET,
∴�
��≥�
��??????�=�
??????�−�
�??????
❖Soforsaturationregiondraincurrent??????
�willbe
∴??????
��??????�=
??????
??????
??????�
??????�−�
�??????(�
??????�−�
�??????)−(�
??????�−�
�??????)
??????
∴??????
��??????�=
??????
??????
.(�
??????�−�
�??????)
??????
∴??????
��??????�=
??????
??????.�
??????�
??????
.
�
??????
.(�
??????�−�
�??????)
??????
Channel Length
Modulation of MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Modulation of MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of Channel Length Modulation
❖Channel length Modulation in MOSFET
❖Derivation of drain current for channel length modulation
❖Characteristics of MOSFET with channel length modulation
❖Basics of Channel Length Modulation
❖Channel length Modulation in MOSFET
❖Derivation of drain current for channel length modulation
❖Characteristics of MOSFET with channel length modulation
Basics of Channel length Modulation
❖InsaturationregionofworkingwithMOSFET,thereischannellength
ModulationwithMOSFET.
❖Inthatchannellengthwillchangewithrespecttodrainvoltageof
MOSFET.
❖Channellengthwilldecreasewithrespecttoincreaseindrain
voltageinsaturationregion.
❖InsaturationregionofworkingwithMOSFET,thereischannellength
ModulationwithMOSFET.
❖Inthatchannellengthwillchangewithrespecttodrainvoltageof
MOSFET.
❖Channellengthwilldecreasewithrespecttoincreaseindrain
voltageinsaturationregion.
Channel Length Modulation in MOSFET
�
??????�>�
��
Depletion Region
Inversion Layer (Channel)
�
�small�
�=�
��??????�
Pinch Off Point
�
�>�
��??????�
Pinch Off Point
LL’
∆L
�
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��
Depletion Region
Inversion Layer (Channel)
�
�small�
�=�
��??????�
Pinch Off Point
�
�>�
��??????�
Pinch Off Point
LL’
∆L
❖Totalchargedensityinchannelisgivenby
??????
??????(�)=−�
??????��
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��−�
�??????
❖Inversionlayerchargeatsource(Y=0)endisgivenby
??????
??????(�=�)=−�
??????��
??????�−�
�??????
❖InversionlayerchargeatDrainend(Y=L)endisgivenby
??????
??????(�=??????)=−�
??????��
??????�−�
��−�
�??????
❖Attheedgeofsaturation�
��=�
��??????�
�
��=�
��??????�=�
??????�−�
�??????
❖InversionlayerchargeatDrainend(Y=L)insaturation
regionisgivenby
??????
??????(�=??????)≈�
❖Effectivechannellengthinsaturationregionwillbecome
??????
′
=??????−∆??????
❖Atpinchoffpointofchannel,channelvoltagewillbe�
��??????�
❖Gradualchannelapproximationisonlyvalidinchannel,
asperthatdraincurrentindeepsaturationisgivenby
∴??????
�(�??????�)=
�
??????.�
??????�
�
.
�
??????′
.(�
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�??????)
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∴??????
�(�??????�)=
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.
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(??????−∆??????)
.(�
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�
∴??????
�(�??????�)=
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∆??????
??????
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.
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.(�
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�
❖Here,
∆??????∝�
��−�
��??????�
❖Tosimplifythisdraincurrentequation,wewilltakeλ
(Channellengthmodulationcoefficient)
∴�−
∆??????
??????
=�−��
��⇒
�
�−
∆??????
??????
=�+��
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❖Sodraincurrentisgivenby
∴??????
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.
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.(�+��
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??????
??????(�)=−�
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❖Inversionlayerchargeatsource(Y=0)endisgivenby
??????
??????(�=�)=−�
??????��
??????�−�
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??????
??????(�=??????)=−�
??????��
??????�−�
��−�
�??????
❖Attheedgeofsaturation�
��=�
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�
��=�
��??????�=�
??????�−�
�??????
❖InversionlayerchargeatDrainend(Y=L)insaturation
regionisgivenby
??????
??????(�=??????)≈�
❖Effectivechannellengthinsaturationregionwillbecome
??????
′
=??????−∆??????
❖Atpinchoffpointofchannel,channelvoltagewillbe�
��??????�
❖Gradualchannelapproximationisonlyvalidinchannel,
asperthatdraincurrentindeepsaturationisgivenby
∴??????
�(�??????�)=
�
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??????�
�
.
�
??????′
.(�
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.
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(??????−∆??????)
.(�
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�
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.
�
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.(�
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�
❖Here,
∆??????∝�
��−�
��??????�
❖Tosimplifythisdraincurrentequation,wewilltakeλ
(Channellengthmodulationcoefficient)
∴�−
∆??????
??????
=�−��
��⇒
�
�−
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=�+��
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❖Sodraincurrentisgivenby
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.
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.(�+��
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❖Draincurrentisgivenby
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.
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.�
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.(�+��
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Drain Current
Drain Voltage
�
??????��with λ=0
�
??????��with λ=0
with λ≠0
with λ≠0
∴??????
��??????�=
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.
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.�
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�
.(�+��
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Drain Current
Drain Voltage
�
??????��with λ=0
�
??????��with λ=0
with λ≠0
with λ≠0
Examples on Drain
Current Calculation
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Current Calculation
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Draincurrent??????
�isgivenby
∴??????
�=
??????
�.�
??????�
�
.
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�isgivenby
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.
�
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��
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�
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Draincurrent??????
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Example2:ForannchannelMOStransistorwith??????
�=���??????�
�
/��????????????,�
??????�=
���
−�
�/??????�
�
,�=��??????�,??????=�??????�and�
�??????=��.
Herebiasingvoltagesfordrain,Sourceandsubstratearegivenby3V,0Vand0V,
respectively.Fordraincurrenttobe1mA,whatshouldbegatebiasvoltage?
kisgivenby
∴�=??????
�.�
??????�.
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×
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Draincurrent??????
�isgivenby
∴�=
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.
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=
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Example2:ForannchannelMOStransistorwith??????
�=���??????�
�
/��????????????,�
??????�=
���
−�
�/??????�
�
,�=��??????�,??????=�??????�and�
�??????=��.
Herebiasingvoltagesfordrain,Sourceandsubstratearegivenby3V,0Vand0V,
respectively.Fordraincurrenttobe1mA,whatshouldbegatebiasvoltage?
kisgivenby
∴�=??????
�.�
??????�.
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??????
∴�=���×��
−�
×
���
−�
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−�
×
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−�
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�
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�isgivenby
∴�=
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.��
�−��−�
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∴�
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∴�
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∴�
��≥�
��−�
�??????
Part-1forpMOSFET
∴(�−�)↔(�−�)−(−�.�)
∴−�↔−(�.�)
∴−�>−�.�(so Linear region)
Part-2fornMOSFET
∴(�−�)↔(�−�)−(�.�)
∴�↔(�.�)
∴�<�.�(so Linear region)
∴�
��≤�
��−�
�??????
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∴�
��≥�
��−�
�??????
Part-1forpMOSFET
∴(�−�)↔(�−�)−(−�.�)
∴−�↔−(�.�)
∴−�>−�.�(so Linear region)
Part-2fornMOSFET
∴(�−�)↔(�−�)−(�.�)
∴�↔(�.�)
∴�<�.�(so Linear region)
Substrate Bias Effect
in MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
in MOSFET
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of Substrate Bias Effect in MOSFET
❖Substrate Bias Effect with MOSFET characteristics
❖Threshold voltage under substrate bias voltage
❖Drain Current under substrate bias voltage
❖Basics of Substrate Bias Effect in MOSFET
❖Substrate Bias Effect with MOSFET characteristics
❖Threshold voltage under substrate bias voltage
❖Drain Current under substrate bias voltage
Basics of Substrate Bias Effect
❖WehavestudiedMOSFETcharacteristicswithsubstratebias
voltage�
��=�.
❖Forzerosubstratebiasvoltage,thresholdvoltageisreferredas
�
��.
❖Inmanydigitalcircuitapplications,thesourcepotentialofnMOS
transistorcanbelargervalues,whichresultsinto�
��>�.
❖Inthatcases,Thresholdvoltagewillchangewithrespectto�
��
andthatleadstochangeindraincurrent,itmeansdraincurrentisa
functionof�
��,�
��and�
��.
??????
�=??????(�
��,�
��,�
��)
❖WehavestudiedMOSFETcharacteristicswithsubstratebias
voltage�
��=�.
❖Forzerosubstratebiasvoltage,thresholdvoltageisreferredas
�
��.
❖Inmanydigitalcircuitapplications,thesourcepotentialofnMOS
transistorcanbelargervalues,whichresultsinto�
��>�.
❖Inthatcases,Thresholdvoltagewillchangewithrespectto�
��
andthatleadstochangeindraincurrent,itmeansdraincurrentisa
functionof�
��,�
��and�
��.
??????
�=??????(�
��,�
��,�
��)
Substrate Bias Effect
Threshold Voltage under substrate bias voltage
❖Thresholdvoltageundersubstratebiasvoltageisgivenby
❖Where,ϒissubstratebiasorbodyeffectcoefficient
�
�(�
��)=�
��+??????(−�??????
�+�
��−−�??????
�)
??????=
�??????�
�??????
�??????
�
��
❖Thresholdvoltageundersubstratebiasvoltageisgivenby
❖Where,ϒissubstratebiasorbodyeffectcoefficient
�
�(�
��)=�
��+??????(−�??????
�+�
��−−�??????
�)
??????=
�??????�
�??????
�??????
�
��
Drain Current under substrate bias voltage
❖Draincurrentinlinearandsaturationregionwithsubstratebias
voltageisgivenby
❖Where,λisChannellengthModulationcoefficient
∴??????
��??????�=
�
??????.�
��
�
.
�
??????
.�
��−�
�(�
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�
.(�+��
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�(??????????????????)=
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�
.
�
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��
��−�
�(�
��)�
��−�
��
�
❖Draincurrentinlinearandsaturationregionwithsubstratebias
voltageisgivenby
❖Where,λisChannellengthModulationcoefficient
∴??????
��??????�=
�
??????.�
��
�
.
�
??????
.�
��−�
�(�
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�
.(�+��
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.
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�(�
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MOSFET
Capacitances
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Capacitances
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of MOSFET Capacitances
❖Structural overview of MOSFET Capacitances
❖MOSFET capacitance Model
❖MOSFET Capacitances in different regions of MOSFET
❖Basics of MOSFET Capacitances
❖Structural overview of MOSFET Capacitances
❖MOSFET capacitance Model
❖MOSFET Capacitances in different regions of MOSFET
Basics of MOSFET Capacitances
❖SpeedofintegratedcircuitislimitedbyCapacitances.
❖Thesecapacitancesarenotlumpedbutdistributed.
❖It’svaluescanbecalculatedbythreedimensional
overviewofMOSFET.
❖Here,wehavealreadystudied�
??????�,whichisgateoxide
capacitance,it’sunitisൗ
�
�??????
�.
�
??????�=
??????
??????�
??????
??????�
❖SpeedofintegratedcircuitislimitedbyCapacitances.
❖Thesecapacitancesarenotlumpedbutdistributed.
❖It’svaluescanbecalculatedbythreedimensional
overviewofMOSFET.
❖Here,wehavealreadystudied�
??????�,whichisgateoxide
capacitance,it’sunitisൗ
�
�??????
�.
�
??????�=
??????
??????�
??????
??????�
Structural Overview of MOSFET Capacitances
MOSFET Capacitances in different regions
Cut Off region
�
��=�
??????��??????
�
��=�
??????��??????
�
�
�??????=�
??????��??????
�
Linear region
�
��=�
�
��=
�
�
�
??????��??????+�
??????��??????
�
�
�??????=
�
�
�
??????��??????+�
??????��??????
�
Saturation region
�
��=�
�
��=�
??????��??????
�
�
�??????=
�
�
�
??????��??????+�
??????��??????
�
Cut Off region
�
��=�
??????��??????
�
��=�
??????��??????
�
�
�??????=�
??????��??????
�
Linear region
�
��=�
�
��=
�
�
�
??????��??????+�
??????��??????
�
�
�??????=
�
�
�
??????��??????+�
??????��??????
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Saturation region
�
��=�
�
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??????��??????
�
�
�??????=
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�
�
??????��??????+�
??????��??????
�
BIST
(Built In Self Test)
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
(Built In Self Test)
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of BIST
❖Types of BIST
❖Architecture of BIST
❖Working of BIST
❖Issues of designing BIST
❖Advantages of BIST
❖Disadvantages of BIST
❖Basics of BIST
❖Types of BIST
❖Architecture of BIST
❖Working of BIST
❖Issues of designing BIST
❖Advantages of BIST
❖Disadvantages of BIST
Basics of BIST
❖Itistechniqueofdesigningadditionalhardwareandsoftwareinto
integratedcircuitstoallowthemtoperformselftesting.
❖AimofBISTtechniqueistoavoidcostlyuseofATE(AutomatedTest
Equipment)testing.
❖AsIC’saregettingcomplex,manyblocksareinterfacedinICwith
analoganddigitalports,inthatATEtestingisdifficultandcostly
service.
❖BISTisalsousefultothoseblocksofICwhichhasnodirect
connectionwithexternalpins.
❖AsIC’sareupgrading,infutureconventionaltesterswillnolongerbe
adequateforthelatestandfastestchip.
❖Itistechniqueofdesigningadditionalhardwareandsoftwareinto
integratedcircuitstoallowthemtoperformselftesting.
❖AimofBISTtechniqueistoavoidcostlyuseofATE(AutomatedTest
Equipment)testing.
❖AsIC’saregettingcomplex,manyblocksareinterfacedinICwith
analoganddigitalports,inthatATEtestingisdifficultandcostly
service.
❖BISTisalsousefultothoseblocksofICwhichhasnodirect
connectionwithexternalpins.
❖AsIC’sareupgrading,infutureconventionaltesterswillnolongerbe
adequateforthelatestandfastestchip.
Types of BIST
❖Here,IwillgivebasicexplanationabouttwodifferentBIST
1.LogicBIST(LBIST)
2.MemoryBIST(MBIST)
❖Here,IwillgivebasicexplanationabouttwodifferentBIST
1.LogicBIST(LBIST)
2.MemoryBIST(MBIST)
Logic BIST (LBIST)
❖Itisdesignedfortestingrandomlogic.
❖Hereweusepseudorandompatterngeneratortogeneraterandom
inputpattern.
❖MultipleInputsignatureregister(MISR)givesresponseofinput
patternandMISRoutputindicatesdefectinthedevice.
❖Itisdesignedfortestingrandomlogic.
❖Hereweusepseudorandompatterngeneratortogeneraterandom
inputpattern.
❖MultipleInputsignatureregister(MISR)givesresponseofinput
patternandMISRoutputindicatesdefectinthedevice.
Memory BIST (MBIST)
❖Itisusedfortestingmemories.
❖Ithasacircuitthatapply,readandcomparetestpatterns.
❖TherearesomeindustrystandardforMBIST
❑TheMarchAlgorithm
❑ThecheckerboardAlgorithm
❑ThevariedpatternbackgroundAlgorithm
❖Itisusedfortestingmemories.
❖Ithasacircuitthatapply,readandcomparetestpatterns.
❖TherearesomeindustrystandardforMBIST
❑TheMarchAlgorithm
❑ThecheckerboardAlgorithm
❑ThevariedpatternbackgroundAlgorithm
Basic Architecture of BIST
Test
Test Controller
Hardware
Pattern
generator
MUX
Normal
Input
CUT
(Circuit Under Test)
Output
Response
Compactor
Signature
ROM
Reference
Signature
Comparator
Good/Faulty
Test
Test Controller
Hardware
Pattern
generator
MUX
Normal
Input
CUT
(Circuit Under Test)
Output
Response
Compactor
Signature
ROM
Reference
Signature
Comparator
Good/Faulty
Issues of BIST designing
❖howmanyfaultstobecovered
❖howmuchchipareaoccupiedbyBIST
❖TestTime
❖Flexibilitybysoftwareandhardware
❖howmanyfaultstobecovered
❖howmuchchipareaoccupiedbyBIST
❖TestTime
❖Flexibilitybysoftwareandhardware
Advantages of BIST
❖Itlowerstestingcost
❖Testingisindependentonfuturetechnology
❖betterfaultcoverage
❖shortertesttime
❖Easiercustomersupport
❖Itlowerstestingcost
❖Testingisindependentonfuturetechnology
❖betterfaultcoverage
❖shortertesttime
❖Easiercustomersupport
Disadvantages of BIST
❖Additionalcircuit(Siliconarea)forBISTtestinginIC
❖AdditionalPinrequiredforBISTtestinginIC
❖Onchiptestingmaygetfailedthenhowtotestit.
❖Additionalcircuit(Siliconarea)forBISTtestinginIC
❖AdditionalPinrequiredforBISTtestinginIC
❖Onchiptestingmaygetfailedthenhowtotestit.
Resistive Load
Inverter
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Inverter
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Circuit of resistive load inverter
❖Working of resistive load inverter
❖Voltage transfer characteristics of resistive load inverter
❖Parameters of resistive load inverter
❖Circuit of resistive load inverter
❖Working of resistive load inverter
❖Voltage transfer characteristics of resistive load inverter
❖Parameters of resistive load inverter
Circuit of Resistive load Inverter
�
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��
R
�
��
�
���=�
��
�
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��
R
�
��
�
���=�
��
Working of Resistive load Inverter
�
�
�
�
❖Duetocapacitanceofgateoxidelayer,gate
currentiszero.
❖So,�
�=�
�
❖So,Outputvoltage�
���equationwillbe
∴�
���=�
��−�
��
∴�
���=�
��−�
��
❖Ifinputislowervoltage(logic0),then
inversionlayerwillnotgetformed,SoDrain
currentwillbezero
∴�
���=�
��(logic1)
❖Ifinputishighervoltage(Logic1),then
inversionlayerwillgetformed,Sodrain
currentwillincrease,whichwilldecrease
outputtologic0.
�
�
�
�
❖Duetocapacitanceofgateoxidelayer,gate
currentiszero.
❖So,�
�=�
�
❖So,Outputvoltage�
���equationwillbe
∴�
���=�
��−�
��
∴�
���=�
��−�
��
❖Ifinputislowervoltage(logic0),then
inversionlayerwillnotgetformed,SoDrain
currentwillbezero
∴�
���=�
��(logic1)
❖Ifinputishighervoltage(Logic1),then
inversionlayerwillgetformed,Sodrain
currentwillincrease,whichwilldecrease
outputtologic0.
Working of Resistive load Inverter
❖So,draincurrentequationwillbe
∴�
�=
�
��−�
���
�
❖Here,IfMOSFETisthereinlinearregionthen�
????????????−�
��>�
���
❖Draincurrent�
�inlinearregionwillbe
∴�
�=
??????
�
��
��−�
���
��−�
��
�
∴�
�=
??????
�
��
��−�
���
���−�
���
�
❖Here,IfMOSFETisthereinsaturationregionthen�
????????????−�
��<�
���
∴�
�=
??????
�
.(�
��−�
��)
�
∴�
�=
??????
�
.(�
��−�
��)
�
❖So,draincurrentequationwillbe
∴�
�=
�
��−�
���
�
❖Here,IfMOSFETisthereinlinearregionthen�
????????????−�
��>�
���
❖Draincurrent�
�inlinearregionwillbe
∴�
�=
??????
�
��
��−�
���
��−�
��
�
∴�
�=
??????
�
��
��−�
���
���−�
���
�
❖Here,IfMOSFETisthereinsaturationregionthen�
????????????−�
��<�
���
∴�
�=
??????
�
.(�
��−�
��)
�
∴�
�=
??????
�
.(�
��−�
��)
�
Voltage Transfer Characteristics of Resistive load Inverter
�
���
�
��
�
��
�
�??????
��
���
��
��
=−�
�
�??????
��
���
��
��
=−�
�
��
�
��
�
���
�
��
�
��
�
�??????
��
���
��
��
=−�
�
�??????
��
���
��
��
=−�
�
��
�
��
Calculation of �
��
❖Inputvoltageisless,sodraincurrentiszero,
soper
∴�
���=�
��−�
��
∴�
���=�
��
��
❖Inputvoltageisless,sodraincurrentiszero,
soper
∴�
���=�
��−�
��
∴�
���=�
��
Calculation of �
�??????
❖Here,�
????????????−�
��>�
���,soMOSFETistherein
linearregion,sodraincurrentwillbe
∴�
�=
??????
�
��
��−�
���
���−�
���
�
❖Draincurrentisalreadyderived
∴�
�=
�
��−�
���
�
❖Fromaboveequation
∴
�
��−�
�??????
�
=
??????
�
��
��−�
���
�??????−�
�??????
�
∴�
�??????
�
−��
��−�
��+
�
??????�
�
�??????+
�
??????�
�
��=�
❖Solutionofthisequationis
∴�
�??????=�
��−�
��+
�
??????�
−�
��−�
��+
�
??????�
�
−
��
��
??????�
�??????
❖Here,�
????????????−�
��>�
���,soMOSFETistherein
linearregion,sodraincurrentwillbe
∴�
�=
??????
�
��
��−�
���
���−�
���
�
❖Draincurrentisalreadyderived
∴�
�=
�
��−�
���
�
❖Fromaboveequation
∴
�
��−�
�??????
�
=
??????
�
��
��−�
���
�??????−�
�??????
�
∴�
�??????
�
−��
��−�
��+
�
??????�
�
�??????+
�
??????�
�
��=�
❖Solutionofthisequationis
∴�
�??????=�
��−�
��+
�
??????�
−�
��−�
��+
�
??????�
�
−
��
��
??????�
Calculation of �
�??????
❖Here,�
????????????−�
��<�
���,soMOSFETistherein
saturationregion,sodraincurrentwillbe
❖Draincurrentisalreadyderived
∴�
�=
�
��−�
���
�
❖Fromaboveequation
∴
�
��−�
���
�
=
??????
�
.(�
��−�
��)
�
❖Ifdifferentiategivenequationwithrespectto�
????????????
∴�
�=
??????
�
.(�
��−�
��)
�
∴−
�
�
.
��
���
��
��
=??????.�
��−�
��
∴−
�
�
.(−�)=??????.�
�??????−�
��
∴�
�??????=�
��+
�
??????�
�??????
❖Here,�
????????????−�
��<�
���,soMOSFETistherein
saturationregion,sodraincurrentwillbe
❖Draincurrentisalreadyderived
∴�
�=
�
��−�
���
�
❖Fromaboveequation
∴
�
��−�
���
�
=
??????
�
.(�
��−�
��)
�
❖Ifdifferentiategivenequationwithrespectto�
????????????
∴�
�=
??????
�
.(�
��−�
��)
�
∴−
�
�
.
��
���
��
��
=??????.�
��−�
��
∴−
�
�
.(−�)=??????.�
�??????−�
��
∴�
�??????=�
��+
�
??????�
Calculation of �
��
❖Here,�
????????????−�
��>�
���,soMOSFETistherein
linearregion,sodraincurrentwillbe
❖Draincurrentisalreadyderived
∴�
�=
�
��−�
���
�
❖Fromaboveequation
∴
�
��−�
���
�
=
??????
�
��
��−�
���
���−�
���
�
❖Ifdifferentiategivenequationwithrespectto�
????????????
∴−
�
�
.
��
���
��
��
=
??????
�
��
��−�
��
��
���
��
��
−��
���
��
���
��
��
∴�
�??????=�
��+��
���−
�
??????�
∴�
�=
??????
�
��
��−�
���
���−�
���
�
∴�
�??????=�
��+
??????
�
�
��
??????�
−
�
??????�
��
❖Here,�
????????????−�
��>�
���,soMOSFETistherein
linearregion,sodraincurrentwillbe
❖Draincurrentisalreadyderived
∴�
�=
�
��−�
���
�
❖Fromaboveequation
∴
�
��−�
���
�
=
??????
�
��
��−�
���
���−�
���
�
❖Ifdifferentiategivenequationwithrespectto�
????????????
∴−
�
�
.
��
���
��
��
=
??????
�
��
��−�
��
��
���
��
��
−��
���
��
���
��
��
∴�
�??????=�
��+��
���−
�
??????�
∴�
�=
??????
�
��
��−�
���
���−�
���
�
∴�
�??????=�
��+
??????
�
�
��
??????�
−
�
??????�
Average DC Power consumption
❖Power consumption is voltage into current.
❖Here duty cycle is 50%, so voltage = ൗ
??????????????????
2
❖Here current =
??????????????????−??????????????????
??????
❖So average DC power dissipation is given by
∴�
��(????????????�??????????????????�)=
�
��
�
×
�
��−�
�??????
�
❖Power consumption is voltage into current.
❖Here duty cycle is 50%, so voltage = ൗ
??????????????????
2
❖Here current =
??????????????????−??????????????????
??????
❖So average DC power dissipation is given by
∴�
��(????????????�??????????????????�)=
�
��
�
×
�
��−�
�??????
�
Ion Implantation
and it’s Advantage
over Diffusion
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
and it’s Advantage
over Diffusion
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Ion Implantation
❖It is alternative to diffusion process in IC fabrication.
❖Diffusion Process is done at high temperature, but Ion implantation
is done at low temperature.
❖In Ion Implantation, high energy dopant ions are accelerated, so that
ions can easily penetrate the Si wafer.
❖The depth of penetration can be increased by increasing accelerating
voltage.
❖It is alternative to diffusion process in IC fabrication.
❖Diffusion Process is done at high temperature, but Ion implantation
is done at low temperature.
❖In Ion Implantation, high energy dopant ions are accelerated, so that
ions can easily penetrate the Si wafer.
❖The depth of penetration can be increased by increasing accelerating
voltage.
Faults in Integrated
Circuit
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Circuit
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Outlines
❖Basics of Faults
❖Types of Faults
❑Permanent fault
❑Non Permanent fault
❖Basics of Faults
❖Types of Faults
❑Permanent fault
❑Non Permanent fault
Basics of Faults in IC
❖ItleadstoimproperoutputofIC.
❖ItmaygivefalseoutputinICorItmayreducespeedofIC.
❖TherearebasicallytwotypesoffaultsinIC
❑PermanentFault
❑NonPermanentFault
❖ItleadstoimproperoutputofIC.
❖ItmaygivefalseoutputinICorItmayreducespeedofIC.
❖TherearebasicallytwotypesoffaultsinIC
❑PermanentFault
❑NonPermanentFault
Permanent Fault
❖Itchangesfunctionalbehaviorpermanently.
❖Mostlyithappensduetophysicalfault.
❖Examples
❑IncorrectICMask
❑WrongConnectionsinIC’s
❑PCBheating
❖Itchangesfunctionalbehaviorpermanently.
❖Mostlyithappensduetophysicalfault.
❖Examples
❑IncorrectICMask
❑WrongConnectionsinIC’s
❑PCBheating
Non Permanent Fault
❖Ithappensatrandommoments
❖Iteffectssystembehaviorforrandomtimeperiod
❖Itiscomparativelydifficulttodetect.
❖Therearetwotypes
❑TransientFaults:Itiscausedbyenvironmentalconditionssuchashumidity,
Pressure,vibrations,αparticlesetc.
❑IntermittentFaults:Itiscausedbynonenvironmentalconditionssuchas
looseconnections,Ageingofcomponentsetc.
❖Ithappensatrandommoments
❖Iteffectssystembehaviorforrandomtimeperiod
❖Itiscomparativelydifficulttodetect.
❖Therearetwotypes
❑TransientFaults:Itiscausedbyenvironmentalconditionssuchashumidity,
Pressure,vibrations,αparticlesetc.
❑IntermittentFaults:Itiscausedbynonenvironmentalconditionssuchas
looseconnections,Ageingofcomponentsetc.
Photolithography
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Photolithography
❖Itisaprocesstoproducecircuit/patternontheSiLayer.
❖UVlightexposureisused.
❖Twoimportantstepsarethereinphotolithography
1.PhotographicMasking:Itcontainsinformationwhichwewanttoprojecton
Siwafer.
2.PhotographicEtching:Itcontainspatterninformationwhichwewantsto
removefromlayer.
❑Therearetwotypesofphotographicetching
➢WetEtching(ByChemical)
➢DryEtching(ByUVlightexposure)
❖Itisaprocesstoproducecircuit/patternontheSiLayer.
❖UVlightexposureisused.
❖Twoimportantstepsarethereinphotolithography
1.PhotographicMasking:Itcontainsinformationwhichwewanttoprojecton
Siwafer.
2.PhotographicEtching:Itcontainspatterninformationwhichwewantsto
removefromlayer.
❑Therearetwotypesofphotographicetching
➢WetEtching(ByChemical)
➢DryEtching(ByUVlightexposure)
Stuck at Fault
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
By Prof. Hitesh Dholakiya
Engineering Funda
VLSI Lecture series
Stuck at fault
❖Anyterminalmaystuckatlogic‘0’orLogic‘1’isreferredasstuckat
fault.
❖Atthatterminal,ithasnodependencyonI/PandO/P.
❖Examples
❑Stuckatlogic‘1’
❑Stuckatlogic‘0’
A
B
Y
Stuck at ‘1’
A B Correct YActual Y
0 0 0 0
0 1 0 1
1 0 0 0
1 1 1 1
A
B
Y
Stuck at ‘0’
A B Correct YActual Y
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 0
❖Anyterminalmaystuckatlogic‘0’orLogic‘1’isreferredasstuckat
fault.
❖Atthatterminal,ithasnodependencyonI/PandO/P.
❖Examples
❑Stuckatlogic‘1’
❑Stuckatlogic‘0’
A
B
Y
Stuck at ‘1’
A B Correct YActual Y
0 0 0 0
0 1 0 1
1 0 0 0
1 1 1 1
A
B
Y
Stuck at ‘0’
A B Correct YActual Y
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 0
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