Esd

electrostatic discharge

1. ELE863/EE8501 VLSI Systems
Electrostatic Discharge Protection
BOND
PAD
SOURCE
GATE
Fei Yuan, Ph.D, P.Eng.
Department of Electrical & Computer Engineering
Ryerson University
Copyrightc2012
Copyright (c) F. Yuan (1)

2. OUTLINE
•Introduction to ESD
•Principle Sources of ESD in ICs
•ESD Models
•ESD Protection Mechanisms
•ESD Protection Devices
•ESD Protection Circuits
Copyright (c) F. Yuan (2)

3. Introduction to ESD
•What is ESD ?
⊲ESD - Electro-Static Discharge.
⊲ESD is a transient discharge of static charge that arises from either
human handling or a machine contact.
⊲Although ESD is the result of a static potential in a charged object,
the energy dissipated and damages made are mainly due to the
current flowing through ICs during discharge.
⊲Most ESD damages are thermally initiated in the form of device /
interconnect burn-out or oxide break-down. The basic phenomenon
of ESD is that is a large amount of heat is generated in a localized
volume significantly faster than it can be removed, leading to a
temperature in excess of the materials’ safe operating limits.
⊲ESD Damages
pn-junction may melt.
Gate oxide may have void formation.
Metal interconnects & Vias may melt or vaporization, leading to
shorts or opens.
⊲Gate-oxide breakdown is another form of ESD damage.
Copyright (c) F. Yuan (3)

4. Introduction to ESD (cont’d)
•Why is ESD Critical ?
⊲The aggressive decrease in physical dimensions and increase in
doping in modern CMOS technology result in a significant decrease
in gate-oxide thickness and pn-junction width−→Require less
energy and lower voltages to destroy MOS devices.
0 0.5 1 1.5 2 2.5 3
50
100
150
200
250
300
350
400
450
500
L
min
[μm]
t
ox
[A]
Figure 1: Scaling of gate oxide thickness of MOS transistors.
Copyright (c) F. Yuan (4)

5. Introduction to ESD (cont’d)
0 0.5 1 1.5 2 2.5 3
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
L
min
[μm]
Junction depth [μm]
Student Version of MATLAB
Figure 2: Scaling of junction depth of MOS transistors.
20 40 60 80 100
5
10
15
20
Gate oxide thickness, t
ox
[A]
V
t1
, V
ox
[V]
V
t1
V
ox
Figure 3: Scaling of the breakdown voltage of gate oxide (Vox) and the avalanche breakdown voltage
(Vt1) of pn-junctions.
⊲The level of ESD stress, however, does not scale down with the
technology.
Copyright (c) F. Yuan (5)

6. Principle Sources of ESD in ICs
•Human Handling
⊲A person walking on a synthetic floor can accumulated up to 20 kV.
This voltage is discharged when the person touches an objectthat is
sufficiently at ground. Charge exchange occurs between the person
and the object in a very short time duration (10 ns - 100 ns). The
charging current is approximately 1A - 10A, depending upon the
time constant.
•Test and Handling Systems
⊲Equipment can accumulate static charge due to improper
grounding. The charge is transmitted through ICs when it is picked
up for placement in test sockets.
•IC Itself is Charged During Transport / Contact
With Charged Objects
⊲ICs remain charged until they come into contact with a grounded
surface (large metal plates /test sockets). Charge is discharged
through the pins of ICs. Large currents in the internal interconnects
can result in high voltage inside the devices which can cause
damage to thin dielectrics and insulators.
Copyright (c) F. Yuan (6)

7. ESD Models
•Human Body Model (HBM)
⊲HBM models the ESD of a human body.
⊲Peak current≈1.3A, rise time≈10-30ns.
DUT
R=1.5kW
C=100pFV (0 )
C
-
Human body model
Figure 4: Equivalent circuit of the human body model of ESD. The switch closes upon an ESD event.
Copyright (c) F. Yuan (7)

8. ESD Models (cont’d)
•Machine Model (MM)
⊲MM models the ESD of manufacturing / testing equipment.
⊲Peak current≈3.7A, rise time≈15-30ns, bandwidth≈12 MHz.
DUT
C=200pF
V (0 )
C
-
Machine model
Figure 5: Equivalent circuit of the machine model of ESD. Theswitch closes upon an ESD event.
⊲ESD stress caused by charged machines is sever because of zero
body resistance. Most ESD protection circuits can only protect
HBM and MM.
Copyright (c) F. Yuan (8)

9. ESD Models (cont’d)
•Charge Device Model (CDM)
⊲CDM models the ESD of charged integrated circuits.
⊲Inductance in the model is mainly due to the inductance of bond
wires.
⊲Peak current≈10A, rise time≈1ns.
⊲Gate oxide breakdown is the signature failure of CDM stress,in
contrast to the thermal failure signature of HBM and MM stress.
⊲CDM stress has the fastest transient and has the max. peak current.
⊲CDM stress is the most difficult ESD stress to protect against.
DUT
R<10W L<10 nH
Charged device model
Figure 6: Equivalent circuit of charged device model of ESD.The switch closes upon an ESD event.
Copyright (c) F. Yuan (9)

10. ESD Protection Mechanisms (cont’d)
•Current Limiting Characteristics of n-well Resistors
•Impact Ionization
•Avalanche Multiplication of pn-junctions
•First Breakdown (Avalanche Breakdown) of nMOS
•Second Breakdown (Thermal Breakdown) of nMOS
Copyright (c) F. Yuan (10)

11. ESD Protection Mechanisms (cont’d)
•Current Limiting Characteristics of n-well Resistors
⊲Conductivity
⊲Majority charge carriers in n-well resistors are free electrons.
⊲At low voltages, the velocity of free electrons (majority charge
carriers) and that of holes (minority charge carriers) in a n-well
resistor are linearly proportional to the field intensity ofthe applied
electric field−→a linear resistor with a constant resistance.
vn=nE, vp=pE, (1)
wherevnandvpare the velocity of free electrons and that of holes,
respectively,nandpare the bulk mobility of free electrons and
holes, respectively.
⊲The total charge crossing a cross-section of areaAper second is
given by
Q= (vnn+vpp)Aq, (2)
wherenandpare the concentration of free electrons and holes,
respectively, andqis the charge of an electron.
⊲Thecurrent densityis obtained from
J=
Q
A
= (nn+pp)qE=σE, (3)
Copyright (c) F. Yuan (11)

12. where
σ= (nn+pp)q (4)
is the conductivity.
⊲Current Density
⊲For n-type, the concentration of free electronics is approximately
the doping of the donors, i.e.n≈nn, wherennis the doping of
donors, we havevn≈nE. Consequently
J≈Jn= (nnnE)q=nnvnq=σE (5)
Jis linearly proportional toEor equivalently the voltage across the
semiconductors.
Copyright (c) F. Yuan (12)

13. ESD Protection Mechanisms (cont’d)
⊲Velocity Saturation
⊲At high voltages, the velocity of free electrons saturates due to the
increasing collision with silicon lattices. As a result, the current
through n-well resistors remains nearly constant regardless of
voltage increase
Jsat=nnvn,satq (6)
vn,sat≈10
7
cm/s,nn= 10
17
/cm
3
−→Jsat= 1.6×10
5
A/cm
2
.
E
vn
v
sat
10
4
V/cm
0
Ohmic region Saturation region
(10 cm/s)
7
Figure 7: Velocity saturation
⊲n-well resistors exhibit a large resistance in the saturation region
shown above.
⊲n-well resistors in the saturation region can be used as
current-limiting devices for ESD protection by limiting the amount
of ESD discharging current that can pass through the devices.
Copyright (c) F. Yuan (13)

14. ESD Protection Mechanisms (cont’d)
•Avalanche Multiplication in pn-junctions
⊲When a pn-junction is reverse biased, the reverse current (leakage
current) is solely due to (i) the movement of thermally generated
charge carriers in the depletion region and (ii) the diffusion of
charge carriers in the neutral regions.
⊲When the reverse biasing voltage exceedsVsat= 10
5
V/cm, the
carriers in the depletion region can impart enough energy inthe
collision with the silicon lattices to generate electron-hole pairs,
which become free charge carriers. These charge carriers are then
accelerated, collide with the silicon lattices, and createmore free
charge carriers−→Avalanche Multiplication.
Si Si
Si
Si
Si
Si Si Si
Si
Si
Covalent bonds
Si Si
Si
Si
Si
Si Si Si
Si
Si
Si Si
Si
Si
Si
Si Si Si
Si
Si
-
Free electron
Hole
-
-
Holes
Covalent bond
destroyed
Strike the covalent bond
and destroy it
Figure 8: Avalanche multiplication
Copyright (c) F. Yuan (14)

15. ESD Protection Mechanisms (cont’d)
•Avalanche Breakdown of nMOS
⊲Parasitic Lateral Bipolar Transistor in nMOS
p+
PAD
n+ n+
R
sub
Isub
p-substrate
D
G
S
V
B
Figure 9: Parasitic lateral BJT in nMOS transistors.
⊲nMOS is used as ESD protection devices.
⊲Gate is grounded to ensure nMOS is off under normal operation
conditions.
⊲Drain-substrate/source-substrate pn-junctions are reverse biased.
⊲A parasitic lateral BJT as shown exists in the substrate.
⊲Under normal operation conditions, this parasitic BJT is off
because both the pn-junctions of the nMOS transistor are reverse
biased−→Isub= 0,−→VB= 0.
Copyright (c) F. Yuan (15)

16. ESD Protection Mechanisms (cont’d)
⊲Avalanche Breakdown of Drain pn-junction of nMOS
⊲WhenVDincreases, the electric field across the drain-substrate
depletion region becomes high enough such that avalanche
multiplication occurs at the drain-substrate junction−→free
electron-hole pairs are generated.
⊲The generated free electrons go to the drain due to its high
potential, whereas the generated holes go to substrate due to its low
potential−→It gives rise toIsub−→The base potential
VB=RsubIsubis increased subsequently.
⊲WhenVBis sufficiently high, the source-substrate pn-junction
becomes forward biased−→electrons in the source (emitter) are
emitted to the substrate (base)−→the parasitic lateral BJT is ON
−→Avalanche Breakdown of MOSFETs−→Static charge on pads
is discharged via the BJT to the ground. Current capacity is
determined by the width of the MOSFETs (the width of the BJT).
⊲The turn-on time of the parasitic BJT is determined by the base
transit time (τb= 250ps for 1m channel length).
⊲Note the fundamental differences between the parasitic BJT and
normal BJTs. The base width of the parasitic BJT equals to the
channel length of the nMOS transistor (in the range ofm),
whereas that of a normal BJT is very small (in the range of˚ A)−→
This BJT has a small current gain as the emitter and collectorhave
the same dimension.
Copyright (c) F. Yuan (16)

17. ESD Protection Mechanisms (cont’d)
⊲Snapback
VD
I
D
Vsh
(V , I )t2 t2
Snapback region
(ESD protection
operation region)
Thermal
breakdown
region
Avalanche
breakdown
Thermal
breakdown
Slope=1/R
sh
(V , I )t1 t1
Figure 10: Avalanche breakdown, snap back, and thermal breakdown of nMOS transistors.
⊲When the BJT is ON, more electrons flows from the source to the
drain−→ID↑andVDdecreases sharply until the snapback holding
voltageVspis reached. The snapback holding voltage is mainly
across the drain-substrate pn-junction. The marginal increase of the
drain voltage is due to voltage drop across the drain diffusion,
source diffusion, and contact resistance.
⊲During snapback, the resistance haspositivetemperature
coefficients. This implies that if the current in any region increases,
the temperature of the region will increase, thereby increasing the
resistance, which encourages the current to flow elsewhere−→
current is conducted uniformly by all figures of nMOS transistors.
Copyright (c) F. Yuan (17)

18. ESD Protection Mechanisms (cont’d)
•Thermal Breakdown of nMOS
⊲During snapback, the current of nMOS increases with the external
voltageVDS.
⊲IfVDScontinues to increase, the device enters the thermal
breakdown−→with the onset of the thermal breakdown, the
resistance of the current path hasnegative temperature coefficients,
encourages current to concentrates in certain localized fingers of
nMOS and eventually destroys the fingers.
⊲The concentration of ESD current into a few fingers indicatesthat
no matter how many fingers are used, only a few will be activated
in case of an ESD strike−→ESD current capability of the device
does not scale with its size.
⊲To enhance the self-protection of ESD protection devices, the
current must flow UNIFORMLY in all fingers of ESD protection
devices.
Copyright (c) F. Yuan (18)

19. ESD Protection Mechanisms (cont’d)
•Avalanche Breakdown versus Thermal Breakdown
⊲If the avalanche breakdown voltage of ESD protection devices is
LESS THAN their thermal breakdown voltage, then the avalanche
breakdown occurs before the thermal breakdown−→ESD stress
will be released by the avalanche breakdown and the devices will
not enter the thermal breakdown.
⊲If the avalanche breakdown voltage of ESD protection devices is
GREATER THAN their thermal breakdown voltage, the avalanche
breakdown will occur at a voltage higher than the thermal
breakdown voltage. After the avalanche breakdown occurs,VDSwill
still higher than the thermal breakdown voltage−→the devices will
enter thermal breakdown and concentrate currents in a localized
area due to negative temperature coefficients−→device will be
destroyed.
V
D
I
D
V
sp V
D
I
D
V
sp V
D
I
D
V
sp
Avalanche
breakdown
Thermal
breakdown
Thermal
breakdown
Avalanche
breakdown
VV < V
t1 t2
VV < V
t2 t1
(A) Avalanche breakdown voltage is less than
thermal breakdown voltage
(B) Avalanche breakdown voltage is greater then
thermal breakdown voltage
Figure 11: Avalanche breakdown/thermal breakdown voltages
Copyright (c) F. Yuan (19)

20. ESD Protection Devices
•n-well Resistors
•Gate-Grounded nMOS Transistors (GGNMOS)
•Gate-Coupled nMOS Transistors (GCNMOS)
•Silicon Controlled Rectifiers (SCR)
•Medium Voltage Triggered SCR
Copyright (c) F. Yuan (20)

21. ESD Protection Devices (cont’d)
•n-well Resistors
P-substrate
SiO2
Poly
SiO2
M1 M1
P-substrate
M1 M1
SiO2
N-well
n+
Poly-resistor
N-well resistor
Figure 12: Poly and n-well resistors
⊲Poly-resistors in general should not be used as ESD protection
devices due to their poor heat dissipation capability (Polyresistors
are isolated from the substrate by the SiO2 layer). Note thatthe
heat generated by ICs is taken away via two paths (i)
PADs/traces/pins and (ii) substrate/ground plate.
⊲n-well resistors have a good contact with the substrate. They are
used as primary current-limiting devices.
⊲When a n-well resistor is used as the current-limiting device,
together with a nMOS (primary ESD protection device), it is
essential to make sure that the n-well resistor will not enter its
thermal breakdown when the nMOS is in its avalanche breakdown.
Copyright (c) F. Yuan (21)

22. ESD Protection Devices (cont’d)
•Diodes
p-substrate
n-well
p+ n+
PAD
Internal
circuits
Rn-well
p-substrate
p-welln+ p+
Rp-well
(a) p+/n-well diodes
(b) n+/p-well diodes
p+/n-well diode
n+/p-well diode
pn-junction
Figure 13: Diodes in CMOS. (a)p
+
/n-well diodes; (b)n
+
/p-well diodes; (c) ESD protection using
diodes.
⊲Two main types of diodes :n
+
/p-well diodes andp
+
/n-well diodes.
p
+
/n-well diodes have a pn-junction between the n-well and
p-substrate whereas there is no isolation between the diodeand the
p-substrate inn
+
/p-well diodes.
⊲When forward-biased, diodes can sustain a large current with a
small device dimension.
⊲Diodes are widely used for ESD protection at radio frequencies due
to the small junction capacitance, which has a less impact onthe
bandwidth of RF circuits.
Copyright (c) F. Yuan (22)

23. ESD Protection Devices (cont’d)
•Gate-Grounded nMOS Transistors
PAD
p-substrate
n+
DS SS
D G S
R
D
R
S
R
sub
Figure 14: Drain contact-gate spacing (DS) and source contact-gate spacing (SS) of ESD protection
nMOS transistors.
⊲During a ESD strike, the pn-junction at the drain undergoes an
avalanche breakdown. Holes flow to the substrate, resultingin an
increase inVB−→parasitic BJT will be turned on−→ESD
current flows from the collector the (drain of nMOS) to the emitter
(the source of nMOS that is connected to the ground)−→ESD
stress at the drain of the nMOS transistor (PAD) is released.
⊲The dimensions of ESD nMOS should be large enough to handle
large ESD currents−→multiple fingers structure is used to
implement ESD nMOS.
⊲The main design parameters of nMOS are (i) channel length, (ii)
drain contact-to-gate spacing, and (iii) device width. Thesource
contact-to-gate spacing is not critical and is kept at its minimum
design value.
Copyright (c) F. Yuan (23)

24. i) The minimum channel length is good for efficient turn-on butthe
punch-through limit will be reduced.
ii) Drain contact-to-gate spacing affects the resistance ofballast
resistors. For silicided processes, the minimum drain contact-to-gate
spacing is used.
iii) Device width determines the maximum current that the device
can conduct.
Copyright (c) F. Yuan (24)

25. ESD Protection Devices (cont’d)
•Gate-Grounded nMOS Transistors (cont’d)
G
S
D
n+
1 2 3 4
Metal-1Metal-2
Contact/via
n-well ballasting
resistor
Figure 15: Lumped ballast resistors are added at the drains to ensure a uniform ESD current distri-
bution among the fingers of ESD protection transistors.
⊲During an avalanche breakdown, the current flowing through the
drain increases. However, the positive temperature coefficient of the
resistance ofn
+
-diffusion (calledBallast Resistors) at the drain
prevents current from concentrating in a localized region−→it
forces the ESD current to flow into other fingers−→uniform
current distribution is achieved.
⊲The effect ofn
+
-diffusion resistance is virtually eliminated in
silicided CMOS processes because in these processesn
+
is silicided
and the resistance of silicidedn
+
is small (a few ohms).
⊲To preserve the current-limiting ability of ballast resistors, explicit
n-well ballast resistors at the drain are added. Note that the sheet
resistance of n-well is much higher than that ofn
+
-diffusion.
Copyright (c) F. Yuan (25)

26. ESD Protection Devices (cont’d)
•Gate-Coupled nMOS Transistors
⊲In most applications, the gate of ESD nMOS is grounded to ensure
that the ESD nMOS will not cause any extra leakage at the pin
during normal operation (Without ESD).
⊲The avalanche breakdown voltage is reduced if the gate of nMOS is
properly biased during a ESD strike.
⊲The gate voltage helps reduce the width of the pn-junction atthe
drain−→increase the electric field in the junction and lower the
avalanche breakdown voltage of the junction.
⊲The value ofCandRmust be such that (i) they have no effect on
the operation of the circuit when there is no ESD stress, (ii)they
must couple a sufficient voltage to the gate during a ESD strike
such that the avalanche breakdown voltage of nMOS is effectively
reduced.
Copyright (c) F. Yuan (26)

27. ESD Protection Devices (cont’d)
•Gate-Coupled nMOS Transistors (cont’d)
V
D
I
D
V
sp
Avalanche breakdown
Thermal breakdown
Reduced avalanche breakdown
Internal
circuits
C
R
PAD
V
G
V
DS
(Avalanche
breakdown
voltage)
Figure 16: Gate-coupled nMOS
⊲C behaves as a short-circuit for ESD strikes (high frequencies).
⊲Gate voltage helps reduce the width of the pn-junction at thedrain
(connected to the pad) as the potential of the substrate underneath
the gate oxide is increased−→drain pn-junction will undergo an
avalanche breakdown at a lower junction voltage−→ESD
protection occurs at a lower drain voltage (better ESD protection).
Copyright (c) F. Yuan (27)

28. ESD Protection Devices (cont’d)
⊲Drawbacks of nMOS-based ESD Protection
⊲Effective for non-silicided processes. Less effective for silicided
processes.
⊲Need additional ballast n-well resistors to increase ESD protection.
⊲Need gate-coupling circuitry to improve ESD protection.
Copyright (c) F. Yuan (28)

29. ESD Protection Devices (cont’d)
•Silicon-Controlled Rectifiers (SCR)
p+
PAD
R
sub
Ic2
p-substrate
n+ n+ p+
Internal
circuits
T1
T2
n-well
R
nwell
pn-junction
Figure 17: Silicon-controlled rectifiers (SCRs).
⊲Under normal operation, the pn-junction between n-well and
p-substrate is reverse biased and SCR has no effect on the operation
of the protected circuits.
⊲During a ESD strike, the pn-junction between n-well and substrate
undergoes an avalanche breakdown−→currents flow from n+
throughRnwellto the substrate−→a sufficient voltage drop across
Rnwellturns on T2−→a large current flows fromp
+
-diffusion
throughRsubto the ground−→T1 turns on−→T1 and T2 latch
up to release ESD stress.
⊲SCR has a high ESD breakdown voltage (≈40V with the latch-up
time≈1ns) as compared with that of nMOS because the breakdown
voltage of n+/p-sub is lower than that of n-well/p-sub (large
pn-junction width)−→internal circuits might have already been
destroyed even before ESD protection circuits are activated.
⊲SCR is not affected by silicidation−→attractive for modern CMOS
processes where silicidation is common.
Copyright (c) F. Yuan (29)

30. ESD Protection Devices (cont’d)
•Medium-Voltage Triggered SCR
⊲An additional n+ is added at the edge of the n-well to reduce the
junction width.
p+
PAD
R
sub
Ic2
p-substrate
n+ n+ p+
Internal
circuits
T1 T2
n-well
R
nwell
n+
n+-diffusion
is added
Figure 18: Modified silicon-controlled rectifiers (MSCRs).
⊲During an ESD strike, pn-junction in this region undergoes an
avalanche breakdown at a LOWER voltage.
⊲Breakdown voltage : 25V for 0.35m CMOS (40V for conventional
SCR).
Copyright (c) F. Yuan (30)

31. ESD Protection Devices (cont’d)
•Low-Voltage Triggered SCR
⊲An additional n+ is added at the edge of the n-well to reduce the
junction width.
p+
PAD
R
sub
Ic2
p-substrate
n+ n+ p+
Internal
circuits
T1
T2
n-well
Rnwell
n+
Grouded-gate
is added
Figure 19: Low-voltage silicon-controlled rectifiers (LVTSCRs).
⊲The added gate-grounded nMOS enters avalanche breakdown first.
⊲Avalanche voltage is similar to gate-grounded nMOS (10V
approximately).
Copyright (c) F. Yuan (31)

32. ESD Protection Circuits
•Requirements of ESD Protection Circuits :
⊲Provide a low-impedance path from input pads to the ground during
an ESD strike to release the static charge accumulated on thepads.
⊲Clamp the voltage of the pads at a level that is below the dielectric
breakdown voltage of thin transistors during an ESD strike.
⊲Provide a very high impedance and a low capacitance during
normal operation such that it has a little effect on the operation of
the protected circuits.
Copyright (c) F. Yuan (32)

33. ESD Protection Circuits
•Basic Configuration
Primary ESD
Elements
Current
limiting
resistor
Secondary ESD
ElementsPAD
Internal
circuits
Figure 20: Configuration of ESD protection circuits
⊲Primary ESD protection elements shunt most of ESD currents.
Primary ESD protection elements have large width and need more
time to turn on.
⊲Secondary ESD protection elements serve to limit the voltage at the
circuit being protected until the primary ESD protection devices are
fully operational. Secondary ESD protection devices have smaller
width.
⊲The effectiveness of the primary ESD protection devices is
determined by the secondary protection stage. Note that dueto the
small dimensions, the secondary protection devices enter avalanche
breakdown before the primary protection devices are activated. It is
critical to ensure that the avalanche breakdown of the primary
protection devices is activated before the secondary protection
devices enter their thermal breakdown so that the secondaryESD
protection devices will not be destroyed by ESD stress.
⊲Current-limiting resistor has two functions (i) limit the current
flowing into the internal circuits. (ii) withstand some ESD voltage
so that the secondary protection circuit will not be damagedin an
ESD strike.
Copyright (c) F. Yuan (33)

34. ESD Protection Circuits (cont’d)
•Basic Circuits
PAD
Internal
circuits
R
Primary ESD elements Secondary ESD elements
Current-limiting
resistor
Figure 21: Basic ESD protection circuits
⊲Both nMOS and pMOS are used for positive and negative ESD
strikes.
⊲Under normal operation conditions, ESD devices are off−→
minimize the leakage current of these devices.
Copyright (c) F. Yuan (34)

35. •ESD of 0.35m CMOS Processes
⊲In sub-micron CMOS, the onset of damage has been observed at
between 1 kV and 2kV.
⊲Design rules are set for 2 kV HBM and 200V MM.
⊲Min. resistance of the isolation n-well resistor : 200 Ω.
⊲Soft-pull is used to balance the breakdown voltage and the speed of
I/O fingers under ESD zapping.
Copyright (c) F. Yuan (35)

36. ESD Protection Circuits (cont’d)
•Distributed ESD Protection Circuits
⊲De-centralize a large capacitance into a set of small capacitances
separated by inductors - a transmission line is constructed−→
capable of transmitting high-frequency signals.
PAD
Internal
circuits
PAD
Internal
circuits
zo
zozo zozo
C
zo
C
zo
C
zo
C
zin
Figure 22: Top - Distributed ESD protection with equal sections; Bottom - small-signal equivalent
circuit.
Copyright (c) F. Yuan (36)

37. ESD Protection Circuits (cont’d)
•Multi-Finger Turn-On (MFT)
⊲Thermal breakdown voltage of each finger of a large ESD protection
transistor is made higher than the avalanche breakdown voltage of
the finger.
⊲Lumped resistors are added at source and drain. The one at drain
functions as ballast resistors while the one at source sensethe ESD
current and generates a voltage that is applied to the gate ofthe
adjacent finger−→behave as a gate-coupled nMOS transistor−→
to initiate ESD protection earlier, better ESD protection.
PAD
Internal
circuitsR
d
R
d
R
d
R
d
RsRsRsRs
Figure 23: Equivalent circuit of poly back-end ballast withsegmentation.
Copyright (c) F. Yuan (37)

38. ESD Protection Circuits (cont’d)
•Soft-Ground-Gate nMOS MFT
⊲Based on substrate pick-up technique−→when an ESD strike
occurs, the potential of substrate increases because ESD currents
flow to the substrate. The gate potential increases subsequently−→
behaves as gate-coupled nMOS transistor that have a low avalanche
breakdown voltage (better ESD protection).
PAD
Internal
circuitsR
d
R
d
R
d
R
d
RsRsRsRs
Figure 24: Equivalent circuit of a soft-grounded-gate nMOSMFT.
Copyright (c) F. Yuan (38)

39. ESD Protection Circuits (cont’d)
•Domino nMOS MFT
⊲Lumped resistors are added at source and drain. The one at drain
functions as ballast resistors while the one at source sensethe ESD
current and generates a voltage that is applied to the gate ofthe
adjacent finger−→behave as a gate-coupled nMOS transistor.
PAD
Internal
circuitsR
d
R
d
R
d
R
d
Rs1Rs1Rs1Rs1
Rs2Rs2Rs2Rs2
Macro-ballasting
resistors
Figure 25: Equivalent circuit of domino nMOS MFT.
Copyright (c) F. Yuan (39)

40. References
⊲For details on ESD protection and references, please read Chapter 8
ofCMOS Current-Mode Circuits for Data Communications(Fei
Yuan, Springer : New York, 2007).
Copyright (c) F. Yuan (40)