Floorplanning Power Planning and Placement

Floorplanning Power Planning and Placement

1. 1
Power Planning and Placement
Floorplanning

2. RTL
Logic Synthesis
Gatelevel
netlist
Place and Route
Placed and Routed design
-Structural Verilognetlistconsists
of connected cells from the used
SC library.
-Timing, power and area requirements
are met under some assumptions:
→Clock skew = 0!
→Ideal voltage is supplied to all cells!
[IR drop = 0]
→Estimated interconnect parasitics,
regardless to actual placement and
routing!
Behavioral, verified, DFT-
friendly and synthesizable
RTL Verilogcode
-Timing, area, power requirements are met
with signoff criteria obtained from foundary
and customer.
-Design rules are met.
--LVS clean
--IR drop and electromigrationrequirements
are met.
Removing all ideal assumptions!
→Actual clock skew is calculated and taken into
account for timing analysis.
→Actual interconnect parasiticsis calculated
after placement and routing.
→Actual IR drop is calculated and checked.
Design rules are considered.
Congestion and cell density are considered.
Moving from Logical to Physical
The Big Picture..
2

3. PnR: a process view
PnR(ICC)
SC .libs
SC MW libraryConstraints
Legally placed and routed
design MW Cell
Prefloorplannetlist(.v)Floorplan
constraints
.TLUplusfiles
-Post-layout .v netlist.
-LEF.
-GDS.
Tech. file
3

4. Floorplanning
Timing
Constraints
Prefloorplan
netlist
.TLUplusfiles
Power Planning & boundary cell insertion
Placement
CTS
Post-CTS optimization
Routing
Floorplan
constraints
SC .libs
SC MW library
Tech. file
4

5. Floorplanning
5

6. Floorplanning
Floorplannningis deciding the major design objects size and placement!
Who is involved in
Floorplanning?
Digital Frontend
Digital Backend
Analog-mixed signal designer
Project Manager
……
6

7. Floorplanning
Chip floorplanning
IO cellsplacement
Macro placement
Bump placement (for flip chip designs)
RDL routing (for flip chip designs)
Power Delivery Network
7

8. MultipleDomainDesign
core
IP
RAM
ROM
PD1
PD2
PD3
8

9. IO Pads
Input/Output circuits used as intermediate structures
connecting internal signals from the core of the IC to
the external pins of the chip package.
Typically organized into an IO ring at the
periphery of the chip. IO pins are
connected to each other through
abutment.
Multiple power pads are often used for core
voltage(s) and IO voltage.
IOs usually consists of:
Level shifters and buffers
ESD protection circuitry.
9

10. IO Pads
Types of IOs:
Signal IOs: in, out, or inout.
Power IOs: core supply/ground, IO supply
ground.
Corner IOs: used for IO ring continuity at
the corners.
Filler IOs: used to keep continuity of IO
ring.
10

11. IO Pads
11

12. IO Pads
12
PAD limited design
The area of die is determined by the
periphery needed for the IO ring.
This can increase the chip size
significantly even if logic is small ->
placement utilization is very low!
Avoided by using IO clusters/area IO
floorplanning.
Core limited design
•The area of the die is determined by the needed
area for the core logic and for macros.
•Small number of IOs, plenty of space for IO ring.
•Usually chips of this type has large number of
macros or logic is implemented in huge count of
gates.

13. Floorplanning
Chip floorplanning
Typical Power network for an SoC.
For our lectures, we will focus
only on IP floorplanning!
13

14. Floorplanning
IP floorplanning
Die area and core area
Hard IPs/Macros placement
Power delivery
Voltage domains
Pin placement
14

15. Floorplanning: Port Locations
Ports can be placed automatically by ICC around the boundary (Die area), or explicitly set by the designer.
The core area is where cells are placed.
Die area represents the boundary of the IP, where ports area placed.
Terminals are physical representation of the ports. A
Terminals (ports implementation )
Core
Die area
Core area
15

16. Creation of Site Rows
Placement requires grid in which cells will be placed: Site Rows.
Site Rows are created based on ‘unit tile’, to fill the core area. They are used later by the placement engine to
place cells.
‘unit tile ’is defined by a library developer and library cells are designed to be multiple of unit tile
Creation of sites for
detailed placement
FF
BUF
INV
NOR
unit tile
(site)
16

17. Standard Cell Placement
Cells are placed in rows, next to each other
One cells structure continue previous one
Cells on neighbor rows are flipped so that they can share same supply
Placement Rows
INV1
VSS
VDD
AND2
VSS
VDD
DFFSR1
VSS
VDD
AOI221
VSS
VDD
JKFF
VSS
VDD
BUF2B
VDD
VSS
VDD
VSS
INV1
VDD
VSS
NOR3
VDD
VSS
XOR2
VDD
VSS
INV1
VDD
VSS
NA21
VDD
VSS
MUX21
17

18. Routing Tracks (Wire Tracks)
Minimu
m width
Minimum
spacing
Metal Routing Tracks
Layers have
perpendicular
directions
Routing is done
on tracks
Insufficient number of
tracks bring congestion
Metal pitch
18

19. Floorplanning: Aspect Ratio
Aspect ratio is the height to width ratio of a block
Defines the block shape
Default aspect ratio is 1
height height
width
width
19

20. Floorplanning: Area Utilization
•Utilizationreferstothepercentageofcoreareathatis takenupbystandardcells
•High Utilization can make it difficult to close routing!
•It will make it also difficult to change the design in the future..CoreArea
cellArea
nUtilizatio

=
Lowstandard-cell
utilization
Highstandard-cell
utilization
20

21. Exercise
Please find out an initial floorplan and
calculate the required area accordingly for
your IP; knowing that:
You usually have total area of 125,000 um2 after
synthesis.
You have 1 analog Macro with area of:
400um*400um, required to have a blockage
surrounding it by 20um from all sides.
Required initial floorplan utilization is 35%.
21
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22. PlacementBlockagesandHalos
•Placementblockageareareasthat
thetoolsshouldnotplaceanycells.
•These,too,haveseveraltypes:
•PartialBlockage–anareawithlower
utilization.
•Halo(padding)–anareaoutsidea
macrothatshouldbekeptclearof
standardcells.
DesignImport
Floorplan
Placement
CTS
Route
FinishDesign
RAM5
Pinsareonleft
andright
Keepoutmargin
22

23. RoutingBlockage
•A routing blockage
isdefinedfora
givenlayer, in a
specific area.
Routing
blockage
CTS
Route
FinishDesign
(75,95)
(20,20)
23

24. RoutingBlockage
http://www.signoffsemi.com/floorplan-placement-2/
24

25. Guidelinesforagoodfloorplan
Finish
PLL
RAM
•q
RAM
RAM
MY_SUB_BLOCK
Standardcellsarea
Singlelarge
corearea
Macros outof
thewayinthe
corner
Large
routing
channels
Pinsaway
fromcorners
RAM1 RAM2 RAM3
RAM4 RAM5 RAM6
RAM7
Useblockageto
improvepin
accessibility
Avoidmanypins
inthenarrow
channel.
Rotateforpin
accessibility
25
RAM8

26. Macro placement
http://www.signoffsemi.com/floorplan-placement-2/
26

27. How to qualify Macro placement?
1.All macros should be placed at the boundaries.
2.Check the orientation and pin direction of all macros, all pins should
point towards the core logic.
3.Spacing between macros should be sufficient for routing and power
grid.
4.Good congestion and QoRresults.
27

28. Technology File
It contains physical information
required for physical synthesis.
•Physical characteristics of each
layer/via,
•Design rules for each layer/via,
•Units (example: time, capacitance,
distance),
•And more
A technology file, as a rule, is provided
by vendor.
The file extension used is .tf
Technology {
unitTimeName= "ns"
timePrecision= 1000
unitLengthName = "micron"
...
}
Layer“M1" {
layerNumber= 16
defaultWidth= 0.23
minWidth= 0.23
...
}
ContactCode "VIA_1_2" {
contactCodeNumber = 31
cutLayer= "VIA1"
lowerLayer = "M1"
upperLayer = "M2"
...
}
28

29. MW Techfile: Technology Section
Unit Precision and Range
To measure capacitance down to 0.0001 picofarad(pF), need
to set unit capacitance to pF and capacitance precision to
10,000.
Defining Routing Rule Modes
Attributes to control physical synthesis
Technology{
/* define units */
dielectric= 0.000000e+00
unitLengthName = "micron"
lengthPrecision = 1000
gridResolution = 50
unitTimeName= "ns"
timePrecision= 100
unitCapacitanceName = "pf"
capacitancePrecision = 10000
...
/* routing rule modes */
minLengthMode= 0
minAreaMode= 0
fatTblMinEnclosedAreaMode = 0
minEdgeMode= 0
cornerSpacingMode = 0
fatTblSpacingMode = 0
parallelLengthMode = 0
fatWireExtensionMode = 0
}
29

30. MW Techfile: Layer Section
Layout attributes
Layout attributes associate a physical layer in the layout with the display
layer.
Display attributes
Display attributes specify how objects on the layer are displayed.
Design rule attributes
Design rule attributes define the layer-specific design rules associated with
objects on the layer.
Physical attributes
Physical attributes define physical characteristics of the layer and need to
be specified if you are using timing-driven layout.
Layer“M1" {
/* layout attributes */
layerNumber= 8
isDefaultLayer = 0
maskName= "metal1"
pitch= 2.2
/* display attributes */
color= "blue"
lineStyle= "solid"
pattern= "dot“
/* design rule attributes */
maxWidth= 1.0
minWidth= 1.0
minArea= 1.0
...
/* physical attributes */
unitMinThickness = 0
unitNomThickness = 0
unitMaxThickness = 0
...
}
31

31. MW Techfile: VIA
ContactCode“VIA12" {
/* physical attributes */
contactCodeNumber = 1
contactSourceType = 0
cutLayer= “VIA1"
lowerLayer= "M1"
upperLayer= "M2"
isDefaultContact = 1
cutWidth= 0.8
cutHeight= 0.8
/* design rule attributes */
upperLayerEncWidth = 0.05
upperLayerEncHeight = 0.1
lowerLayerEncWidth = 0.1
lowerLayerEncHeight = 0.05 ...
/* parasitic attributes */
unitMinResistance = 0.00025
unitNomResistance = 0.00025
...
}
Metal 1
Metal 2
0.8
0.05
0.1
x
y
32

32. A3
MW Techfile: Design Rules
Via
X
1
X
2
L
Metal
W <= Q
if min {X1, X2} <= S0,
then L >= E0
if S0 < min {X1, X2} <= S1 ,
then L >= E1 (E1 < E0)
DesignRule{
layer1 = "Metal2"
layer2 = "Via1"
endOfLineEncWidthThreshold = Q
endOfLineEncTblSize = 2
endOfLineEncSideThreshold = (S0, S1)
endOfLineEncTbl = (E0, E1)
}
33

33. Modeling Parasitics
TLUPlus Models contain C/R look-up tables
Interconnect
Technology File
(ITF)
TLU+
(ICC)
nxtgrd
(StarRC)
010
100
010
100
34

34. tech2itf Map File Creation
metal1
metal2
metal3
via1
via2a
M1
M2
M3
v1
v2
conducting_layers
metal1 M1
metal2 M2
metal3 M3
via_layers
via1 v1
via2 v2
remove_layers
Milkyway
Techfile
Map File ITF
35

35. Synopsys MilkywayDatabase/Library
The Milkywaydatabase was originally developed by Avanti Corporation,
which has since been acquired bySynopsys. It was first released in
1997.
Milkywayis the database underlying most of Synopsys' physical design
tools.
Milkywaystores topological, parasitic and timing data. Having been used
to design thousands of chips, Milkywayis very stable and production
worthy.
36

36. MilkywayDatabase
•A milkywaydatabase contains both Layout and
Abstract views
1.Layout (CEL view)contains drawn mask layers
required for fabrication.
2.Abstract (FRAM view) contains only minimal data
needed for PnRtools. [pin shapes, obstructions]
The difference between both views is like the
difference between .GDS and .LEF views.
37

37. Resolving References
Gate-level netlists contain references to standard cells and macros which are stored
in the logical libraries as well as other hierarchical logic blocks
Before placing one must ensure that all references can be resolved
Checking of all references
Gate-Level Netlist(s)
risc_core
nand nor
inv ff
sdram, ..
pci_core
38

38. FRAM (Abstract) View Content
Abstract view contain physical information of standard and macro cells necessary for placement
A B
Y
NAND_1
GND
VDD
Abstract View
Layout View
B
VDD
GND
Y
A
origin
(typically 0,0)
Blockage
Symmetry
(X, Y, or 90º)
⌟
Pins
(direction, layer
and shape)
PR Boundary
39

39. Preparing the Design
The IC Compiler tool uses a Milkywaydesign library to store your design and
its associated library information.
40

40. Setting Up the Logic Libraries
The IC Compiler tool uses logic libraries to provide timing and functionality
information for all standard cells. In addition, logic libraries can provide timing
information for hard macros, such as RAMs.
In each session, you must set up the logic libraries by defining the search path,
link libraries, and target libraries.
41

41. Setting Up the Physical Libraries
The IC Compiler tool uses Milkywayreference libraries and technology files
to obtain physical library information.
TheMilkywayreference libraries contain physical information about the
standard cells and macro cells in your logic library.
The technology file providestechnology-specificinformation, such as the
name and characteristics of each metal layer.
42

42. Power planning
43

43. Power planning
Power planning is deciding how we will deliver power to the
design’s standard cells!
What is the importance of having a power network with low
impedance?
All analysis and optimization done in logic synthesis and PnRare based on that cells are
supplied with ideal voltage..
If the actual circuit supply is different significantly, cell operation will be different than
the behavior characterized in the .libs, which will cause all types of timing violations!
44

44. IRDrop
•Thedropinsupplyvoltageoverthelengthofthesupplyline
•Aresistancematrixofthepowergridisconstructed
•Theaveragecurrentofeachgateisconsidered
•Thematrixissolvedforthecurrentateachnode,
todeterminetheIR-drop.
Minimum
Tolerance
Level
Actualvoltagelevel
Idealvoltagelevel
45

45. IRDrop
•The power supply (VDD and VSS) in a chip is uniformly distributed through the
metal rails and stripes which is called Power Delivery Network (PDN).
•Each metal layers used in PDN has finite resistivity.
V2 = V1 -I.R
Consequences of IR drop
A.poor performance of the chip due to the increase of delay of standard cells
B.functional failure of the chip due to setup/hold timing violation.
46

46. IRDrop
Possible reasons of IR drop
1.Poor design of power delivery network.
1.lesser metal width and more separation in the power stripes).
2.inadequate via in power delivery network.
2.Inadequate number of decapcells availability.
3.High cell density and high switching in a particular region.
A.Insufficient number of voltage sources.
B.High RC value of the metal layer used to create the power delivery network.
47

47. HotSpots
•WegenerallymaptheIRdropofachipusingacolormapto
highlight“hotspots”,wheretheIRdropisbad.
InitialIRDropMapping
48

48. Electromigration(EM)
•Electromigrationreferstothegradualdisplacementofthe
metalatomsofaconductorasaresultofthecurrentflowing
throughthatconductor.
•Transferofelectronmomentum
•Canresultincatastrophicfailuredotoeither
•Open:voidonasinglewire
•Short:bridgingbetweentowires
•Evenwithoutopenorshort,
EMcancauseperformancedegradation
•Increase/decreaseinwireRC
DesignImport
Floorplan
Placement
CTS
Route
FinishDesign
49

49. Electromigration(EM)
•When a high current density passes through a metal interconnect, the momentum of current-
carrying electrons may get transferred to the metal ions during the collision between them.
•Due to the momentum transfer, the metal ions may get drifted in the direction of motion of
electrons. Such drift of metal ions from its original position is called the electromigration effect.
•Depending on the current density, the subjected metal ion started drifting in the opposite direction
of the electric field. If the current density is high, the interconnect may get affected of EM instantly
or some times the effect may come after months/years of operation depending on current density.
•Mean-time-to-failure [MTTF]
Where A = Cross-Section area
J = Current density
N = Scaling factor (normally set to 2)
Ea= Activation energy
K = Boltzmann's constant
T = Temperature in Kelvin
50

50. Top-level Power Network
User can specify
Number of straps: Min, max
Width of straps: Min, Max
Width of ring
Layers
More(Wider)PowerLines:
•LessStatic(IR)drop
•LessDynamic(dI/dt)drop
•LessElectromigration
More(Wider)PowerLines:
•Fewer(signal)routing
resources
(i.e.,highercongestion)
BUT
51

51. PowerandGroundRouting
•Eachstandardcellormacrohaspowerandground
signals,i.e.,VDD(power)andGND(ground)
•Power/Groundmeshwillallowmultiplepaths
fromP/Gsourcestodestinations
•Lessseriesresistance
•Hierarchicalpowerandgroundmeshes
fromuppermetallayerstolowermetallayers
•Multipleviasbetweenlayers
•Ingeneral,P/Groutingsareprettyregular
•P/Groutingresourcesareusuallyreserved
DesignImport
Floorplan
Placement
CTS
Route
FinishDesign
52

52. Signalroutingarea
PowerGridCreation
•TradeoffIRdropandEMversusroutingresources
•Requirepowerbudget
•Initialpowerestimation
•Averagecurrent,maxcurrentdensity
•Needtodetermine
•Generalgridstructure(gatingormulti-voltage?)
•Numberandlocationofpowerpads(pervoltage)
•Metallayerstobeused
•Widthandspacingofstraps
•Viastacksversusavailableroutingtracks
•Rings/norings
•Hierarchicalblockshielding
•Runinitialpowernetworkanalysistoconfirmdesign
Mx
Mx-1
Mx-2
Mx
Mx-1
Mx-2
Powerlines
53

53. Placement
54

54. Placement
•Placementisthestageofthedesignflow,duringwhich
eachinstance(standardcell)isgivenanexactlocation.
•Inputs:
•Netlistofgatesandwires.
•FloorplanandTechnologyconstraints
•Output:
•Allcellslocatedinthefloorplan.
•Goal
•Providelegallocationofentirenetlist
•Avoiding routing congestion, to enable
easy detailedroutingofallnets
•Meettiming,area,andpowertargets
55

55. Placement
•Placement is the process of placing the standard cells inside the core
boundary in an optimal location.
•The tool tries to place the standard cell in such a way that the design should
have minimal congestions and the best timing.
56
Placement
SynthesisNetlist

56. PlacementFlow
•Ingeneral,mosttoolspartitiontheplacementtaskintotwostages:
•Globalplacement:
•Quicklydivideeachcellinto“bins” totryandminimizethenumberof
connectionsbetweengroups.
•In this stage, the tool will not check any overlap of instances
•Detailedplacement:
•Providealegalplacementforeachinstance
•Tryandminimizewirelength(orothercostmetrics)
•Trytofinishwithuncongesteddesign.
Coarse
Placement
7
GoodPlacement
Legalized
Placement
57

57. High Fanout Synthesis [HFS]
•Initially, there are some nets which have very high numbers of fanout.
•We have a constraint of maximum fanout, so we need to distribute the sinks on
nets to different drivers.
•The process of adding buffers and splitting the fanout is called high fanout
net synthesis (HFNS).
7
58

58. Placement Optimizations
Global placement aims to get a rough placement solution that may violate some placement constraints
[there might be overlaps or cells not assigned to a row.]
Optimize timing and reduce transition
Placement has huge impact one timing closure.
High input transition leads to increased delay, being more prone to crosstalk, and getting inaccurate calculations
for STA.
Global placement enhances timing and fixes high transition nets using:
Reducing wirelength, placing cells close to each other.
Dividing long nets using buffers/inverters.
Layer promotion: setting extra NDR rules for some nets.
Resizing gates to meet timing, reduce power, or reduce high transition.
Advanced techniques in recent PnRtools: logical restructuring, CCD everywhere.
Fix high Fanout nets
Tie Cell insertion
Scan-chain reordering
59

59. Tie-cell insertion
•Why can’t we use power network to connect 1b’1/1b’0?
•To avoid damaging the gate oxide under the poly gate .
•if the polysilicon gate connects directly to VDD or VSS it can be damaged due to power
noise.
•Connecting an input of logic cell that is the gate of a transistor directly to vddor vssis not
recommended to avoid power noise. [drop in VDD and bounce in VSS]
•So In this step tool places tie high and tie low cells which is basically a single output logic cell,
and it connects the input of the logic gate which needs to connect vddor vssrespectively.
7
60

60. Tie-cell insertion
Tie cell schematic
•The tie cell has no input pin and only one output pin.
•The output of the tie-high cell is always high and the output of the tie-low cell is always low and it
is the glitch-free output that connects to the input of any logic gates.
•In this step tool places tie high and tie low cells which is basically a single output logic cell, and it
connects the input of the logic gate which needs to connect vddor vssrespectively.
7
61

61. Scan-chain reordering
7
62
•It’s the process of reconnecting the scan chains in a
design to optimize for routing by reordering the scan
connection which improve timing and congestion.
•Logic synthesis arbitrarily connects the scan chain
•Based on timing and congestion PnRtool optimally
places standard cells.
•While doing so, if scan chains are detached, it can
break the chain ordering originally made by DFT
compiler, and reorder to optimize it & it maintains
the number of flops in a chain.
•This way; we get easier routing of scan chain and
reduced congestion.
•Because of scan chain reordering patterns generated
earlier is of no use. But this is not a problem as ATPG
can be redone by reading the new netlist.

62. Logical restructuring
7
63
•Restructuring means gate composition or decomposition.
•Placement engine can use it to enhance WNS or TNS.
•It can be used also if there is a power gain.

63.  AdamTeman,
2018
Congestion
•Congestionoccurswhenthenumberofrequired
routingtracksexceedsthenumberofavailabletracks.
•Congestioncanbeestimatedfrom
theresultsofaquickglobalroute.
•Globalbinswithroutingoverflow
canbeidentified.
Routingdemand=3
Assumeroutingsupplyis1,
overflow=3-1=2.
Overflowoneachedge=
RoutingDemand-RoutingSupply
0(otherwise)
TotalOverflow
=
overflow
alledges
GlobalBin
Edge
GlobalBin
29/28
28/28
39/35 40/35
Netscrossingthe
globalroutingcell
(GRC)edgeper
availablerouting
tracks
Global
routinggrid
Routingtracks
64

64. •Notroutableorseverelycongesteddesign
•Itisimportanttominimizeoreliminatecongestionbeforecontinuing
•Severecongestioncancauseadesigntobeun-routable
DesignImport
Floorplan
Placement
CTS
Route
Finish
Desig
n
Congestion
•IssueswithCongestion
•Ifcongestionisnottoosevere,theactualroute
canbedetouredaroundthecongestedarea
•ThedetourednetswillhaveworseRCdelay
•Inhighlycongestedareas,delayestimatesduring
placementwillbeoptimistic.
Congestion
hotspot
CongestionMap
≥2 ≥3 ≥4 ≥5 ≥6 ≥7
Detour
65

65. CongestionMaps
•Congestionmapsaredisplayedbythebackendtooltohelpusevaluate
thetotalcongestion,identifyandfixcongestionhotspots.
66

66. Congestion-drivenPlacement
•CongestionReduction
•Thetooltriestoevaluatecongestionhotspots
andspreadthecells(lowerutilization)inthe
areatoreducecongestion.
•Thetoolcanalsochoosecelllocationbased
oncongestion,ratherthanwire-length.
(channelcapacities:2)
UnroutableLayout
LongerWirelength
ChannelDensity:2
(track:2)
D
E F G H
ACB
A
E F G H
DCB
ShorterWirelength
ChannelDensity:3
(track:3)
67

67. Reasons for congestion
oHigh standard cell density in a small area
oPlacement of standard cells near macros
oHigh pin density at the edge of the macro
oHigh utilization inside power domain fence in muti-voltage
designs
oMacro pins near core area boundary
oBlind double spacing/width for ctsin lower metal layers near
pins (hard pin access)
oBad floorplan
68

68. Placement Constraints
Used to reduce/avoid congestion, or to enhance timing.
1)Placement blockages
Area where standard cell placement is prevented in.
A)Hard PB: all cells are prevented in the specified bbox.
Ex.create_placement_blockage-boundary {10 20 100 200} –name pb0
B)Soft PB: during optimizations; bufs/invscan be placed in it.
Ex.create_placement_blockage-boundary {10 20 100 200} –name pb1 –type soft
C)Partial PB: limits the cell density in the specified bbox.
Ex. create_placement_blockage–boundary {10 20 100 200} –type partial \
-blocked_percentage40
D)Keepoutmargins: It is a region around the boundary of fixed cells in a block
in which no other cells are placed.
69
2)Placement bounds
It is a fixed region in which we placed a set of cells. Usually useful for cells of
timing critical paths.
Ex. create bound –name b1 –type soft –boundary {10 10 20 20} instance_2

69. CTS
RouteFinishDesign
StrategiestoFixCongestion
Modifythefloorplan:
•Markareasforlowutilization.
•Alignmentofbussignalpins
•Increaseofspacingbetweenmacros
•Addblockagesandhalos
•Coreaspectratioandsize
•Makingblocktallertoaddmorehorizontalroutingresources
•Increaseoftheblocksizetoreduceoverallcongestion
•Powergrid
•Fixinganyroutedornon-preferredlayers
x1y1
 AdamTeman,
2018
39
70

70. Congestion recommendations in Floorplanning
oPlacement of standard cells near macros
oMacro pins near core area boundary
ocreate_placement_blockage-bbox$bbox-type hard -name $name
71

71. Congestion recommendations in Floorplanning
oCheckerboard blockages: use hard placement blockages between
cells
oblockageslimitsites availablefor cellplacement
72

72. No Hold Time Fixing in Placement
◼By default place_opttries to fix only setup time
violations -No hold time fixing
◼Hold time will be addressed during clock tree synthesis
◼All timing calculations are based on ideal
clocks (clock skew = 0). Therefore, it is a
common practice to give more constrainted
timing to placement engine with:
A.Extra uncertainty
B.Frequency Overdrive
73

73. Thank You!
74