Formal Verification Engineer, M.S. in Electrical Engineering at ASU, looking for a job Opportunity in U.S.Opportunities in U.S

Formal Verification Engineer

1. Shweta Sarap

669-263-4779 • [email protected] • linkedin.com/in/shweta-sarap

EDUCATION

Master of Science in Electrical Engineering Dec 2025
Arizona State University, Tempe, Arizona, USA GPA: 3.94 / 4.00
Coursework: Hardware Design Language, Digital Design & Computer Architecture, Microelectronics
Manufacturing, Software Process & Quality Management, Software Verification & Testing
Planned Coursework: VLSI Design, VLSI Architecture, Digital Systems and Circuits, VLSI Design for Reliability

Master of Technology in Computer Engineering
University of Pune, Pune, India GPA: 3.20 / 4.00

Bachelor of Engineering in Computer Engineering
University of Pune, Pune, India GPA: 3.40 / 4.00

PROFESSIONAL EXPERIENCE

TIAA: Associate Jan 2022 – May 2024
• Responsible for designing, executing, and maintaining manual and automated test cases.
• Led cross-functional defect triage sessions, bug identification and root-cause analysis, and leveraged
JIRA to track issues-improving defect resolution efficiency by 50%.
• Collaborated with design teams, ensuring alignment between test cases and product requirements.
• Integrated automated test cases into Continuous Integration/Continuous Delivery (CI/CD) pipelines
with Jenkins and Git, optimizing parallel test execution using Selenium Grid for faster delivery.

Atos Syntel: Associate Consultant Nov 2018 - Jan 2022
• Developed formal properties, constraints, and cover points to ensure comprehensive coverage and accurate
validation of design intent.
• Verified functional features of RTL modules including CPU control path operations, control logic, FSMs,
counters, and cache controller read/write behavior using formal verification techniques, ensuring functional
correctness across all modules.
• Developed and executed comprehensive assertion-based test plans using JasperGold Formal Property
Verification App, achieving high property completeness and coverage closure.
• Debugged counterexamples through waveform analysis, RTL code review, and close collaboration with
designers to refine assumptions and setups.
• Applied convergence techniques such as Initial Value Abstraction, Counter Abstraction and Design
Reduction to improve proof depth and verification efficiency.
• Closed formal coverage (Stimuli, COI, ProofCore) to ensure property completeness and sign-off quality
across modules.
• Executed JasperGold Sequential Equivalence Checking (SEC) and maintained automated regressions to
validate defeature-related changes.
• Owned formal verification tasks end-to-end, maintaining detailed documentation of test plans, convergence
status, and complexity reports.

2. ACADEMIC PROJECTS

Impact of various Branch Predictors on Processor Performance using CBP6 Simulator
• Implemented multiple branch predictors, including global history, local history, tournament, and
perceptron-based predictors.
• Conducted a comprehensive evaluation of these predictors using SPEC benchmarks, analyzing accuracy,
performance trade-offs.
• Automated large-scale simulation runs, log parsing, and visualization using Python to generate key
performance metrics, producing comparative analysis reports across multiple SPEC workloads.

Implementation of 5-Stage Pipelined Microprocessor with Simulation & Verification (System Verilog)
• Designed and implemented a 5-stage custom microprocessor using System Verilog, including ALU,
instruction ROM, register file, and FSM-based control logic.
• Built and simulated a 16-operation ALU (ADD, SUB, MUL, DIV, etc.) with a 16:1 MUX using five 4:1
MUXes, verified execution via waveform analysis.
• Deployed the design on an FPGA , demonstrating real-time instruction decoding, PC updates, and data
routing using 7-segment displays and LEDs.

4-bit Arithmetic Logic Unit (ALU) Design Using Verilog
• Designed a Verilog-based 4-bit ALU with support for arithmetic (ADD, SUB) and logic (NAND, XOR,
NOT, shift) operations using a modular ripple-carry architecture.
• Verified correctness using a custom testbench and waveforms; deployed on DE10-Lite FPGA board with
hardware-mapped switches and LEDs.
• Implemented overflow and carry detection logic, reinforcing RTL-level debugging and formal analysis
skills.

TECHNICAL SKILLS

• Tools: Jasper Gold (Formal Property Verification App, Coverage App, Sequential Equivalence Checking
(SEC) App), ModelSim, Synopsys VC Formal, JIRA, Git, Confluence
• Formal Verification: Property Checking, Assertion-Based Verification (SVA), Constraint Modeling,
Formal Coverage, Abstraction Techniques - Initial Value Abstraction, Counter Abstraction, Convergence
Techniques - Design Reduction, Black boxing
• Languages: System Verilog / System Verilog Assertions (SVA), Verilog, Python, C++, Java, Tcl, Bash
• Verification Techniques: Formal Property Planning, Assertion Development, Counterexample Analysis,
Root Cause Isolation, Regression, Bug Triage & Defect Tracking.

CERTIFICATIONS

• Cadence Certified: SystemVerilog Assertions, Jasper Formal Fundamentals.