fpga2024munichwebinarversionfinal1720462330803.pdf

FPGA

1. A Leading Provider of Smart, Connected and Secure Embedded Control Solutions
The Golden Age of Computer
Architecture with Microchip and
RISC-V®
July 11, 2024
Ted Speers

2. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
Agenda
•RISC-V® Open ISA and Eco-system
•Looking Back: Golden Age of Computer Architecture
•What’s Next? Golden Age of Compilers
•RISC-V Vector Processing
•What Does Power Look and Sound Like
•Microchip Leadership in Technical Innovation and Implementation
2

3. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
The Magic of RISC-V®
3
Software ecosystem
(OSes, platforms, libraries,
domain specific applications)
ISA: Instruction set architecture
(Interface between
hardware & software)
Implementation: IP
X86
Implementation: SoC
Open ISA accelerates innovation

4. PolarFire®SoC FPGA Shows The Magic in Action

5. Looking Back
What progress have we made?

6. 2017 Turing Award Lecture

7. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
Enter Domain Specific Architecture (DSA)
Software
Productivity
Hardware
Productivity

8. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
Use domain-specific language
NA
Enter Domain Specific Languages (DSL)
Software
Productivity
Hardware
Productivity

9. Recipe For The Future
•Open hardware standards (e.g. RISC-V®)
•More investment in hardware = start-ups
•Major reduction in time and cost to develop new
hardware
•More hardware engineers – make hardware cool
again
Domain-specific languages
▪More focus on compiler technology
▪Keep doing what you’re doing




RISC-V® Vector “V” Extensions

10. Where Are We Going?
Next level of investment

11. The Golden Age of Compilers

12. Summary: The Golden Age of Compilers
Source: Golden Age of Compilers

13. The Golden Age of Compilers
Source: Golden Age of Compilers

14. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
What is MLIR?
Clang
LLVM IR
Backend
RTL
C/C++
Analysis /
Optimizations
GCC
frontend
IR
(Gimple)
Backend
RISC-V binary
C/C++
PyTorch
IR
Backend
Binary
Python
Clang
Backend
RTL
C/C++
Backend
GCC
frontend
Multiple levels of IR
Backend
RISC-V binary
C/C++
PyTorch
Binary
Python
Analysis /
Optimizations
Current Compilers
Single level of abstraction, lose information, difficult
to analyze and perform high-level operations
MLIR
Different levels of abstractions allow
different types of optimizations.
A heterogenous device needs compilers for different parts (sequential, vector ops, ML, HLS, etc)
MLIR allows integration into single compiler

15. 2021 Recipe For The Future
•More investment in hardware = start-ups
•Open hardware standards (e.g. RISC-V®)
•Major reduction in time and cost to develop new
hardware
•More hardware engineers – make hardware cool
again
Domain-specific languages
▪More focus on compiler technology
▪Keep doing what you’re doing
MLIR

16. 2021 Recipe For The Future (updated)
Others
powered DSAs
Others
Others
Others
DSLs
Interpreted Compiled
Others
Compilers
DSAs

17. powered DSAs
2021 Recipe For The Future (updated)
Others Others
Others
Others
DSLs
Interpreted Compiled
Others
Compilers
DSAs

18. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
Does Mojo Complete The Puzzle?
•Mojo is designedto solve a
variety of AI development
challenges that no other
language can, because Mojo is
the first programming language
built from the ground-up
withMLIR
•Designed Mojo as a superset of
Python because we love Python
and its community, but we
couldn't realistically enhance
Python to do all the things we
wanted.
18
Matmul Speed-up
Python 1
Mojo version of Python 8.6
Add types to Python 2364
Vectorize the inner loop12384
Parallelize Matmul 381421
Tiling Matmul 455126
DSL

19. powered DSAs
Recipe for the future (updated)
Others Others
Others
Others
DSLs
Interpreted Compiled
Others
Compilers
DSAs

20. Vector Processing
Key component of DSAs

21. I See Vector Processors, They’re Everywhere!

22. A Look At The RISC-V®
Vector ISA
22
https://github.com/riscv/riscv-v-spec

23. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
RISC-V Vectors: One Simple Instruction
23
VLEN
VLEN <= 10
16
v0
v1
v2
v31
v4
vadd.vv vd, vs1, vs2

24. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
RISC-V Vectors: Optimized Hardware
24
v0
v1
v2
v31
v4
v0
v1
v2
v31
v4
vadd.vv vd, vs1, vs2
VLEN = 64b
VLEN = 128b

25. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
RISC-V Vectors: Dynamic Register Configuration
25
v0
v1
v2
v31
v4
v0
v1
v2
v31
v4
v0
v1
v2
v31
v4
VSEW = 32b
VSEW = 16b
VLEN = 64b
Element Width
vadd.vv vd, vs1, vs2
https://github.com/riscv/riscv-v-spec

26. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
RISC-V Vectors: Dynamic Register Configuration
26
v0
v1
v2
v31
v4
EW = 32b
v0
v1
v2
v31
v4
v0
v1
v2
v31
v4
LMUL = 1
LMUL = 2
v0
v1
v2
v31
v4
VLEN = 64b
Length Multiplier
vadd.vv vd, vs1, vs2

27. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
RISC-V Vectors: Results
•Simple ISA
•Optimizable HW
•One binary
27
v0
v1
v2
v31
v4
EW = 32b
a0 b1v0
v1
v2
v31
v4
c2 d3
09 0a
0b 0c
LMUL = 2
v0
v1
v2
v31
v4
VLEN = 64b
vadd.vv v2, v0, v4

28. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
Microchip Extending Reach of RISC-V® Innovation
PolarFire®
FPGA
2016 Summit
Soft RISC-V®
MCUs32-bit Microcontroller with
Custom Cache Size
µC
Open. Flexible. Secure.
PolarFire®SoC
FPGA
2019 SummitIPs / CPUs
RISC-V®
Ecosystem
Mi-V
Linux + Real-time
Asymmetric RISC-V®
Multi-Processing
RV64IMAC
Monitor Core
RV64GC
Core
Coherent Switch
Deterministic L2 Memory Subsystem
Deterministic, Coherent CPU Cluster
High-Performance
Spaceflight
Computing
PolarFire®2
FPGA
2022 Summit
EDGE Compute
Platform
NASA JPL

29. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
Microchip: Open Hardware Leader
29
Arduino® - 2007 Beagle V® - 2023
$150
MSRP

30. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
75% of enterprise-
generated data will be created
and processed outside a
centralized data center or
cloud by 2025
– Analyst
The Intelligent Edge: A Massive DSL/DSA OpportunityAerospace &
Defense
Space Compute
Autonomous
Vehicles
Precision Diagnostics in
Medical Imaging
AI/ML in the IoT
Industrial Edge
5G & Data
Networks
And it is also a massive power problem

31. 8 July 2024 Microchip Technology Inc. and its subsidiaries©
What Low Power Looks and Sounds Like?
•Actual customer quotes:
•“Is this on?”
•“I think I’m entering data in your Power Estimator incorrectly; the numbers are too low”
•“We can’t give you a customer quote because PolarFire is our low power secret sauce.”
•“PolarFire allows us to create products that would not be possible with competing FPGAs.”
•“Are you insane?! Running that without a fan!”
Polarfire® FPGA 3.5W, 60C, 24FITCompetitor FPGA 6.0W, 81C, 96FIT
•Which is cheaper to build?
•Which is more reliable?
•Which will sell more?
•Which is cooler?

32. Open and flexible ISA
Expanded eco-system
Roadmap to Next Golden Age
32
Leading On Low Power, Open Standards, Open-source hardware
Industry Investments Needed
+

33. Thank-you!