Fully depleted silicon insulator

FDSOI and PDSOI

1. Fully Depleted Silicon Insulator(FD-SOI) R Sandeepkumar 17M405

2. Introduction 1. Over the past decades, transistors have been continuously scaled down in size to increase performance and reduce power consumption, leading to better electronics devices, able to do more useful, important, and valuable things faster, more clearly, and more efficiently; what the marketers call “an enhanced user experience. 2. In recent years, as the transistor has shrunk to a size now below a few tens of nanometers , the effort has increased the challenges for every new generation of technology. One example is leakage current, which because transistors are so small, now represents a significant proportion of its power consumption. 3. In order to continue to deliver higher performance--while keeping the leakage under control--bulk-silicon transistors have become ever more complex, adding additional manufacturing steps and more recently considering a move to a new, expensive, 3D architecture.

3. Types of SOI Devices Partially depleted SOI(PDSOI): For a n-type PDSOI MOSFET the sandwiched p-type film between the gate oxide(GOX) and buried oxide(BOX) is large, so the depletion region can’t cover the whole p region. So to some extent PDSOI behaves like bulk MOSFET. Fully Depleted SOI (FDSOI): the film is very thin in FDSOI devices so that the depletion region covers the whole film. In FDSOI the front gate(GOX) support less depletion charges than the bulk so an increase in inversion charges occour resulting in higher switching speeds.

4. The FD-SOI innovation 1. Fully Depleted Silicon On Insulator, or FD-SOI, is a planar process technology that relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon. 2. Then, a very thin silicon film implements the transistor channel. There is no need to dope the channel, thus making the transistor Fully Depleted. 3. The combination of these two innovations is called “ultra-thin body and buried oxide Fully Depleted SOI” or UTBB-FD-SOI. 4. By construction, FD-SOI enables much better transistor electrostatic characteristics versus conventional bulk technology. The buried oxide layer lowers the parasitic capacitance between the source and the drain. It also efficiently confines the electrons flowing from the source to the drain, dramatically reducing performance-degrading leakage currents.

5. PD-SOI

6. FD-SOI

7. Structures

8. Bandgap

9. Fully Depleted

10. Fully Depleted

11. Transfer characteristics

12. FDSOI In FDSOI case, the front and back channels are electro-statically coupled during device operation. This electrostatic coupling, makes the front channel FD device parameters dependent on the back gate voltage, including drain current, threshold voltage, sub-threshold slope etc. 30% higher performance in FDSOI than others 45% lower power consumption in FDSOI

13. Benefits for Analog and high-speed designs FD-SOI also brings many advantages to analog design. The total dielectric isolation of the channel allows for lower gate capacitance and leakage currents, as well as the benefit of total latch-up immunity. Moreover, the absence of channel doping and pocket implants in the fully depleted transistor produce lower noise specifications and higher gains (up to +15dB) when compared to bulk technologies.

14. Outstanding power efficiency The improved electrostatic characteristics in FD-SOI bring two main advantages: faster operation at low voltage and better management of the energy. Body biasing is much more effective for controlling the transistor channel, allowing the optimization of static and dynamic power consumption.

15. Body-biasing AN EXTREMELY POWERFUL AND FLEXIBLE CONCEPT IN FD-SOI Body-biasing, also often referred to as back biasing, controls the threshold voltage ( VT) of a transistor to optimize: • Drive current (for higher performance) at the expense of increased leakage current (Forward Back Bias, FBB) • Or, leakage current, with somewhat lower performance (Reverse Back Bias, RBB) Body-biasing facilitates a wide Dynamic Voltage Frequency Scaling (DVFS) range (0.7 V – 1.1 V) • Performance boost wherever needed • Reduce power consumption at a given performance requirement • Process compensation reducing the margins to be taken at design

16. PDSOI FDSOI Insulating BOX thickness is 100 to 200nm Insulating BOX thickness is 5 to 50nm Top Silicon layer 50 t o 90nm Top Silicon 5 to 20nm Used in analog circuit Low power applications Easy to manufacture Leakage and power consumption reduced drastically Drawbacks: Packaging scalability Complex fabrication process