Hardware description languages

As per calicut university syllabus for EEE

1. Hardware description languages Akhila P Das Asst. Prof, ECE Dept., AIT, Palakkad

2. Hardware description languages HDL is a language that describes the hardware of digital systems in a textual form. It resembles a programming language, but is specifically oriented to describing hardware structures and behaviors. ECE Dept,Aryanet Institute of Technology 2

3. Hardware description languages The main difference with the traditional programming languages is HDL’s representation of extensive parallel operations whereas traditional ones represents mostly serial operations. The most common use of a HDL is to provide an alternative to schematics. ECE Dept,Aryanet Institute of Technology 3

4. Hardware description languages HDL can be used to represent logic diagrams, Boolean expressions, and other more complex digital circuits. Thus, in top down design, a very high-level description of a entire system can be precisely specified using an HDL. This high-level description can then be refined and partitioned into lower-level descriptions as a part of the design process. ECE Dept,Aryanet Institute of Technology 4

5. Hardware description languages There are two standard HDL’s that are supported by IEEE. VHDL ( Very-High-Speed Integrated Circuits Hardware Description Language ) - Sometimes referred to as VHSIC HDL, this was developed from an initiative by US. Dept. of Defense. Verilog HDL – developed by Cadence Data systems and later transferred to a consortium called Open Verilog International (OVI). ECE Dept,Aryanet Institute of Technology 5

6. HDL based digital design Why HDLs? Support larger system designs By describing the design in a high-level (=easy to understand) language, we can simulate our design before we manufacture it. This allows us to catch design errors ECE Dept,Aryanet Institute of Technology 6

7. HDL tool suites Text editor Allows you to write, edit and save an HDL program Compiler Finds syntax errors Creates an intermediate file that describes the interconnections and logic operations ECE Dept,Aryanet Institute of Technology 7

8. HDL tool suites Synthesizer Targets the design to a specific hardware technology such as PLD, FPGA or ASIC Refers to one or more libraries having gates, flip-flops, registers, adders, counters etc. By analyzing the intermediate design description, synthesizer “infer” the opportunity to map portions of the design into these larger-scale library components ECE Dept,Aryanet Institute of Technology 8

9. HDL tool suites Simulator Inputs: HDL program and test bench/ waveform editor Test bench is the timed sequence of inputs for the hardware described by HDL Waveform editor used to graphically represent the inputs Simulator runs the specified input sequence on the described hardware and determines the values of hardware’s internal signals and its outputs over a specified period of time Outputs are viewed graphically through waveform editor and also a text file that lists signal values, errors and warnings ECE Dept,Aryanet Institute of Technology 9

10. HDL tool suites Template generator Creates text file with the outline of commonly used program structure so that the designer can “fill in the blanks” to create source code for a particular purpose Schematic viewer Creates schematic diagram corresponding to an HDL program, based on output of compiler May differ from final synthesized result ECE Dept,Aryanet Institute of Technology 10

11. HDL tool suites Translator Targets the compiler’s intermediate-language output to a real device such as PLD, FPGA or ASIC There is also an associated fitter and chip viewer Fitter fits the translated realization into available resources on the real device Chip viewer lets the designer see how the design has been laid out on the chip ECE Dept,Aryanet Institute of Technology 11

12. HDL tool suites Timing analyzer Calculates delays through some or all of the signal paths in the final chip and produces a report showing the worst case paths and their delays Back annotator Inserts delay clauses or statements in the original HDL source program, corresponding to delays calculated by the timing analyzer ECE Dept,Aryanet Institute of Technology 12

13. HDL-based design flow ECE Dept,Aryanet Institute of Technology 13

14. Front-end steps Block diagram : define modules and their interfaces Coding : writing of HDL code for modules, their interfaces and their internal details Compilation : the HDL compiler analyzes the code for syntax errors and compatibility with other modules on which it relies Simulation : define and apply inputs to the design and observe its outputs. ECE Dept,Aryanet Institute of Technology 14

15. Front-end steps Verification : Functional verification : study the circuit’s logical operation Timing verification : study circuit’s operation including estimated delays ,and verify setup, hold and other timing requirements ECE Dept,Aryanet Institute of Technology 15

16. Back-end steps Synthesis : converts the HDL description into a set of primitives or components that can be assembled in the target technology. E.g.: with PLDs and CPLDs, the synthesis tool may generate two-level SOP equations. With ASICs, it may generate a list of gates and a netlist that specifies how they should be connected ECE Dept,Aryanet Institute of Technology 16

17. Back-end steps Fitting : a fitter maps the synthesized primitives or components onto available device resources For PLD or CPLD, this means assigning equations to available AND-OR elements For FPGA or ASIC, it means selecting macrocells or laying down individual gates in a pattern and finding ways to connect them within the physical constraints of the FPGA or ASIC die--- place-and-route process ECE Dept,Aryanet Institute of Technology 17

18. Back-end steps Timing verification : actual circuit delays due to wire lengths, electrical loading and other factors can be calculated with reasonable precision ECE Dept,Aryanet Institute of Technology 18