hazards.pdf

Hazards

1. Race Conditions and
Hazards
Prepared By
Mr.T.Rajavenkatesan
AP/EEE/KSRCT
K.S.RANGASAMY COLLEGE OF TECHNOLOGY
(An Autonomous Institution, Affiliated to Anna University, Chennai.)
TIRUCHENGODE - 637215

2. Race Condition
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A race condition is an undesirable situation that occurs when a device or system
attempts to perform two or more operations at the same time.
A race condition can also occur if instructions are processed in the incorrect
order.
In general, race condition refers to a situation in which the result depends upon
the sequence in which events happen.
In logic gates, it happens when the inputs arrive at the gate in a sequence not
assumed while deriving the function.
This results, sometimes, in the anomalous behavior of the logic gate because of
the unexpected dependence on the sequence of arrival of inputs. 
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3. Cont.,
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Since, the function of the logic gate is calculated assuming static
inputs;
The order of arrival may have impact on the output.
We can consider race condition as a situation in which two or more
signals are racing to have their effect on the output.
For a very simple example, consider the following logic function.
Z = A . A’
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4. Race Condition
Theoretically, the output will always be ‘0’. However, this is true only if the non-inverted portion of the signal has
greater delay in reaching the AND gate. (considered ‘0’ -> ‘1’ transition of the input signal ‘A’).

The signal passing through inverter will have some delay of its own.

If the signal through inverter reaches the AND gate later than the one without inverter, there will be a glitch as
shown in the figure.

For ‘1’ -> ‘0’ transition, the opposite will happen.

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5. Consequences
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If the condition for race is violated, the design may enter an
undefined state, the one which might not have been considered while
designing.
Hence, the whole system will malfunction in such a scenario leading
to failure.
It might be the case that some elements in the design enter
metastable state, which can further cause problems.
Hence, it is very important to give proper consideration to race
conditions.
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6. Prevention of Race Condition
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Normally, in digital designs, as long as setup and hold checks are met for each flip-flop,
we do not need to worry about the race conditions in the design under consideration.
But, there are some conditions like the output of the above AND gate might be used as a
clock for some flop.
In that case, we need to consider the race condition. We need to have proper sequencing
of signals so as to have the desired output.
The above case been in reality, it might be wise to delay the non-inverted signal.
Race conditions in the design can be eliminated by using proper design techniques (e.g.
K-map).
Using these, designers recognize and eliminate the race conditions before they cause
problems.
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7. Hazards
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In digital logic, a hazard in a system is an undesirable effect caused by either a deficiency in the system or
external influences.
Logic hazards are manifestations of a problem in which changes in the input variables do not change the
output correctly because of some form of delay caused by logic elements (AND, NOT, OR gates, etc.).
This results in the logic not doing its function properly.
The 3 different most common hazards are usually referred to the
Static Hazard
Dynamic Hazard
Essential or function hazards.
Hazards are the temporary problem, as the logic circuit will gradually settle to the desired function.
But, despite logic arriving at correct output, it is imperative that hazards be removed as they can have an
effect on the other connected systems.
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8. Static Hazard
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A static hazard is situation where, when 1 input variable changes, the output
changes momentarily before stabilizing to correct value.
These disturbances or fluctuations occur when different paths from the input to
output have different delays and due to this fact.
Changes in input variables do not change the output instantly but do appear at
output after a small delay caused by the circuit building elements
There are 2 types of static hazards:
Static – 0 Hazard.
Static – 1 Hazard.
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9. Static Hazard
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Static-0 Hazard: the output is 0 and after the inputs change, the
output momentarily changes 1 before settling on 0.
Static-1 Hazard: the output is currently one and after the inputs
change, the output momentarily changes to zero before settling on
one.


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10. Dynamic Hazard
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A dynamic hazard is possibility of an output changing more than once which is a
result of a single input change.
Dynamic hazards occur often in larger logic circuits where there are present
different routes to the output.
If each route has a different delay, then it rapidly becomes clear that there is
potential for changing the output values which differ from the expected output.
For example A logic circuit is meant to change output state
From 1 to 0, but instead changes from 1 to 0, then 1 and then rests at the correct
value 0. This is called as dynamic hazard
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11. Detection of Static hazards using K-map
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Lets consider static-1 hazard first. To detect a static-1 hazard for a
digital circuit following steps are used:
Step-1: Write down the output of the digital circuit, say Y.
Step-2: Draw the K-map for this function Y and note all adjacent 1’s.
Step-3: If there exists any pair of cells with 1’s which do not occur to
be in the same group ( i.e. prime implicant), it indicates the presence
of a static-1 hazard. Each such pair is a static-1 hazard.
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12. Static 1 Hazard Free Realization
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13. Static – 0 Hazard
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Similarly for Static-0 Hazards we need to consider 0’s instead of 1’s.
If any adjacent 0’s in K-map are not grouped into same group that may
cause a static-0 hazard.
The method to detect and resolve the static-0 hazard is completely
same as the one we followed for static-1 hazard except that instead
of SOP, POS will be used as we are dealing with 0’s in this case.
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14. Static – 0 Hazard free Realization
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15. Circuit Implementation
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16. Essential Hazard
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A fundamental mode asynchronous circuit may malfunction even after avoiding the critical races
and eliminating static and dynamic hazards.
This is due to the fact that fundamental mode asynchronous circuits are prone to another type of
hazard, called as the essential hazard.
This is another type of hazard that is likely to occur in the asynchronous sequential circuits.
It results from unequal delays along two or more paths with originate from the same point.
If such thing happens in the feedback path of the asynchronous sequential circuit then it is called
as essential hazard, because for asynchronous sequential circuits, the feedback loop is essential.
It is possible to eliminate such hazards by adjusting the delays of the involved paths so that they
become exactly equal.
Due to essential hazards, the asynchronous sequential circuit may become stable in some other
state than intended.
The existence of essential hazard can be detected directly from the flow table
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17. Hazard free Realization
Y = x
1
x
2
 + x
2
′ x
3
Y = x
1
x
2
 + x
2
′ x
3
 + x
1
x
3
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18. Hazard free Logic Diagram
Y = x
1
x
2
 + x
2
′ x
3
 + x
1
x
3
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