Internal memory

Types of internal memory

1. Internal MEMORY

2. Semiconductor Memory RAM Misnamed as all semiconductor memory is random access Read/Write Volatile (contents are lost when power switched off) Temporary storage Ram is of two types i.e., Static or dynamic Dynamic is based on capacitors Static is based on flip-flops – no leaks, does not need refresh

3. Dynamic RAM Dynamic random-access memory  ( DRAM ) is a type of random-access memory that stores each bit of data in a separate  capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1

4. Dynamic RAM Stores data as charge on capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Used in main memory

5. Static RAM Static random-access memory  ( SRAM  or  static RAM ) is a type of semiconductor memory that uses  bistable  latching circuitry to store each bit. The term  static  differentiates it from dynamic RAM (DRAM) which must be periodically refreshed.

6. Static RAM Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital Uses flip-flops

7. DRAM and SRAM Structure

8. SRAM v/s DRAM Both volatile DRAM is simpler and smaller than SRAM DRAM is less expensive than SRAM DRAM is favored for large memory requirements SRAM are faster than DRAM SRAM is used for cache memory and DRAM is used for main memory

9. Types of ROM Programmable ROM Erasable Programmable ROM Electrically Erasable Programmable ROM Flash Memory

10. Programmable ROM A memory chip on which data can be written only once. The difference between a PROM and a ROM ( r ead- o nly  m emory) is that a PROM is manufactured as blank memory, whereas a ROM is programmed during the manufacturing process

11. Erasable Programmable ROM E rasable programmable read only memory , is a type of memory chip that retains its data when its power supply is switched off. Once programmed, an EPROM can be erased by exposing it to strong ultraviolet light source 

12. Electrically Erasable Programmable ROM It  is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed.  EEPROMs can be programmed and erased in-circuit, by applying special programming signals .  the number of times it could be reprogrammed i s limited.

13. Flash memory Flash memory  is an electronic non-volatile computer storage medium that can be electrically erased and reprogrammed . F lash memory is a specific type of EEPROM where large amounts of static data are stored (such as in USB flash drives )

14. Module Organisation 256-KB Memory Organization Multiple chips make up the entire memory. 1 bit per chip system org. 8 256K x 1 bit chips.

15. Module Organisation (2) 1-MB Memory Organization

16. Hard Failure Permanent defect Soft Error Random, non-destructive No permanent damage to memory Present in all materials Detected using Hamming code Can be also repaired using error correcting code SEC-DED code: single error correcting - double error detecting code can detect 2 errors, can correct 1 Error Correction

17. Error Correcting Code Function

18. Example of Error Correction: Hamming Code Operation

19. Interleaved Memory In an interleaved memory, the memory is divided into a set of  banks . One way of allocating virtual addresses to memory modules is to divide the memory space into contiguous blocks. In an interleaved memory, however, consecutive addresses reside in different banks.

20. For example, suppose there are 4 banks, each containing 256 bytes. The interleaved scheme would assign addresses 0, 4, 8,  to the first bank, 1, 5, 9,  to the second bank, and so on. 

21. Interleaved Memory (2) However the memory space is split up among the banks, as long as requests are sent to two different banks they can be handled simultaneously. The processor can request a transfer from location  i  on one cycle, and on the next cycle request information from location j  . If  i  and  j  are in different banks, the information will be returned on successive cycles.

22. Advanced DRAM Organization In recent years ,a number of enhancements to the basic DRAM architecture have been explored , and the schemes that currently dominate the market are – SDRAM DDR – DRAM RDRAM

23. Synchronous DRAM Synchronous dynamic random access memory  ( SDRAM ) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to pipelines incoming commands. The data storage area is divided into several  banks , allowing the chip to work on several memory access commands at a time. This allows higher data access rates than an asynchronous DRAM.

24. Rambus DRAM Rambus Dynamic Random Access Memory (RDRAM) is a memory subsystem designed to transfer data at faster rates. RDAM is made up of a random access memory (RAM), a RAM controller and a bus path that connect RAM to microprocessors and other PC devices.  RDRAM was introduced in 1999 by Rambus, Inc. RDRAM technology was considerably faster than older memory models, like the Synchronous DRAM (SDRAM). Typical SDRAM has a data transfer rate of up to 133 MHz, while the RDRAM can transfer data at a speed of upto 800 MHz. RDRAM is also known as Direct RDRAM or Rambus.

25. DDR SDRAM T he enhanced version of SDRAM is DDR SDRAM (double data rate SDRAM) that overcomes the once-per-cycle limitation. It can send data to the processor twice per clock cycle. DDR SDRAM (double data rate SDRAM) is synchronous dynamic RAM (SDRAM) that can theoretically improve memory clock speed to at least 200 MHz*. It activates output on both the rising and falling edge of the system clock rather than on just the rising edge, potentially doubling output.

26. Cache DRAM Cache DRAM, integrates a small SRAM cache (16Kb) onto a generic Dram chip. The SRAM on the DRAM can also be used as a buffer to support the serial access of a block of data.

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