Interrupts

1. Interrupts
Copyright © 2012 Embedded Systems
Committee
Eman Aboelatta

2. Copyright © 2012 Embedded Systems
Committee
Agenda:
•Introduction
•Interrupts
•Interrupt sequence
•So how to we define an ISR?
•Interrupt Vector Table
•Modifying Interrupt Vector Table of ATmega16
•Registers Used
•Interrupt priorities
•Interrupt nesting
•Nested Interrupt Priorities

3. Copyright © 2012 Embedded Systems
Committee
At first we have two methods for receiving data or get status

Introduction:
Polling Interrupt

4. Copyright © 2012 Embedded Systems
Committee
which involves reading the status of the port at fixed intervals to
determine whether any data has been received or a change of status
has occurred. If so, then we can branch to a routine to service the
ports requests.

oTakes CPU time even when no requests pending.

oOverhead.




Other alternative would be to use Interrupts.


“Polling is like picking up your phone every few seconds to see if
you have a call. …”

Polling :
Introduction:con’t

5. Copyright © 2012 Embedded Systems
Committee

 Interrupts can be used to interrupt the sequential execution of
the program flow(called asynchronous processing - that is, we are
processing the interrupt events outside the regular execution of the
main program.)

 Interrupt sources can be
- external events (e.g. change of signal at PORTB2).
- internal events.



Interrupts (IR):
Hardware interrupt
(e.g. timer
overflow).
Software interrupt
(which occur in response
to a command issued in
software-Exception
Handling )

6. Copyright © 2012 Embedded Systems
Committee
Non Maskable Interrupts :

doesn’t depend on global interrupt enable in processor status word
Usually it’s external interrupt(Ex : Reset).

Maskable Interrupts:

Depends on global interrupt enable in processor status word
May be :
External interrupt from external pin
Internal interrupt from peripheral
Interrupts (IR):con’t

7. Copyright © 2012 Embedded Systems
Committee
Interrupts (IR):Con’t
In the case of an interrupt event
the execution of the main
routine is interrupted and the
interrupt service routine (ISR)
of the according event is
executed.


After executing the ISR the
execution proceeds where it has
been interrupted.

8. Copyright © 2012 Embedded Systems
Committee
When the CPU detects
The CPU finishes its current instruction.
The contents of the program counter and the condition code
register(status register or Processor status word) are pushed
onto the stack(because the interrupt routine will almost
certainly modify the condition code bits).
Further interrupts are disabled to avoid an interrupt being
interrupted.
The CPU deals with the cause of the interrupt by executing
a program called an interrupt handler(ISR)(Interrupt service
routine).
The CPU executes a return from interrupt instruction at the
end of the interrupt handler. Executing this instruction pulls
the PC and PSW off the stack and execution then continues
normally—as if the interrupt had never happened.

Interrupt sequence:

9. Copyright © 2012 Embedded Systems
Committee
Interrupt sequence: con’t
o PSR : Processor Status
Register ==status
register==Condition Code
register

o PC : Program Counter
(contains Address of next
instruction to be executed)

10. Copyright © 2012 Embedded Systems
Committee
For an ISR to be called, we need three conditions to be
true:

Firstly, the AVR's global Interrupts Enable bit (I) must be set in
the MCU control register SREG.

Secondly, the individual interrupt source's enable bit must be
set. Each interrupt source has a separate interrupt enable bit in
the related peripheral's control registers, which turns on the
ISR for that interrupt.

Thirdly, The condition for the interrupt must be met - for
example, for the USART Receive Complete (USART RX)
interrupt, a character must have been received(i.e flag that
indicate interrupt raised)

So how to we define an ISR?

11. Copyright © 2012 Embedded Systems
Committee
So how to we define an ISR?con’t
Execute ISR
Enable Global interrupt (I)
Enable peripheral interrupt
Interrupt occurred (flag
raised)

12. Copyright © 2012 Embedded Systems
Committee
•Constant table in ROM.

•Special addresses with respect to CPU.

•Each interrupt has specific address in interrupt vector
table .

•This specific address should be programmed to have the
address of ISR of this interrupt.

•At interrupt processing PC will contain this address or it
will be an instruction to jump to this address

13. Copyright © 2012 Embedded Systems
Committee
Interrupt Vector Table:cont
•From Datasheet ATmega32/16.

14. Copyright © 2012 Embedded Systems
Committee
 Assembly 






 C 

Modifying Interrupt Vector Table of
ATmega16:
.org $000
rjmp Reset
.
.
.
.
.
Reset:
//instructions
ISR ({Vector Source}_vect)
{
// ISR code to execute here
}

15. Copyright © 2012 Embedded Systems
Committee
• The status register contains:
– Six bits status indicators ( Z,C,H,V,N,S )
– One bit for global interrupt enable ( I )

• The status bits reflect the results of CPU operation as it executes
instructions
Status Register (SREG):To Enable Global Interrupt
Registers Used

16. Copyright © 2012 Embedded Systems
Committee
•Clear global interrupt enable: (prevent)
•Set global interrupt enable: (Allow)
To Set/Clear global interrupt enable:
The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable
subsequent interrupts.
Registers Used with Atmega32/16:

17. Copyright © 2012 Embedded Systems
Committee
GICR (General Interrupt Control Register):P.no 47
Registers Used with Atmega32/16:

18. Copyright © 2012 Embedded Systems
Committee
MCUCR (MCU Control Register) P.66
Registers Used with Atmega32/16:

19. Copyright © 2012 Embedded Systems
Committee
MCUCSR (MCU Control and Status Register) P67
Registers Used with Atmega32/16:

20. Copyright © 2012 Embedded Systems
Committee
GIFR (General Interrupt Flag Register)
Registers Used with Atmega32/16:

21. Copyright © 2012 Embedded Systems
Committee
• ISR(Interrupt Service Routine)
Defining ISR :
#include <avr/interrupt.h>

ISR({Vector Source}_vect)
{
// ISR code to execute here
}

22. Copyright © 2012 Embedded Systems
Committee
Interrupt priorities:
•Each interrupt has default priority by its location in
interrupt vector table

•Some controllers provide more intelligent interrupt
controller which give interrupt priority level for each
interrupt

•If two interrupts have a same priority level then the rule
to return to the default priority

23. Copyright © 2012 Embedded Systems
Committee
Interrupt nesting:
•Interrupt Nesting: ability to leave the current interrupt
and serve another interrupt

•Usually done if global interrupt is enabled and this
interrupt has more priority

•Some controllers support the nesting of context switching
in hardware and others leave it to be done in software

24. Copyright © 2012 Embedded Systems
Committee
Nested Interrupt Priorities:

25. References
Copyright © 2012 Embedded Systems
Committee
•ATmega16 Datasheet.


•http://www.avrfreaks.net/

26. [email protected]
Copyright © 2012 Embedded Systems
Committee