Intro to Intel how tgheu are usinginreal rime system

Intro to Intel how tgheu are usinginreal rime system

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X86
Session_01
Introduction to Intel
processors

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The 8086 Family
•16 bit processor
•Can address up to 1MB of memory
–If the first byte of a word is at even address,
8086 reads the entire word in one bus
operation
–If the first byte of a word is at odd address,
8086 reads the entire word in two bus
operation

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8086 Internal Features
•Two independent functional parts
–Bus Interface Unit
•BIU sends out addresses,fetches
instructions, reads/writes data from/to
ports and memory
–Execution Unit
•EU tells the CPU where to fetch instructions
from,decodes and executes the instructions

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The Execution Unit
•Contains the control circuitry
•A decoder
•A 16 bit ALU
• A 16 bit Flag Register with nine flags
•General Purpose Registers
–AH, AL, BH, BL, CH, CL, DH, DL
•16 bit stack pointer, base pointer,
source index register and destination
index register

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Flag Register
U U U U OF DF IF TF SF ZF U AF U PF U CF
8085 compatible flags
U - unused
Overflow flag
Direction flag
Interrupt flag
Single step flag

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Bus Interface Unit
•A set of 16 bit segment registers
–data segment,stack segment,code
segment & extra segment
•A FIFO 6 byte register set called
queue
-Pipelining
•A 16 bit instruction pointer
•A memory interface

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8086 Signals
•It comes in a 40 pin DIP package
•AD15 - AD0 form a time multiplexed address
and data bus
•A19 - A16 / S6 - S3 form the higher order
address bits as well as 4 status signals that
identify the type of operation being done in
that cycle
•BHE’ indicates whether a complete word or
one byte from/to an odd byte, or one byte
from/to an even byte is being transferred

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8086 Signals
•MN/MX’ signal selects one of the two operating
modes,minimum mode and maximum mode
•S4 and S3 indicate the segment register that is
used for the access
•There are two interrupt pins INTR and NMI
•RQ’/GT0’ and RQ’/GT1’ are used for switching the
local bus between various bus masters
–A bus controller such as 8288 is used

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8086 Signals
•RESET input,if asserted takes the 8086 to the
physical address FFFF0h
•8086 in minimum mode requires
–a clock generator such as 8284
–address latches
–data bus buffers
–ROM and RAM