Introduction to HDLs

This PPT is intended to provide a thorough coverage of verilog HDL concepts based on fundamental principles of digital design. This is the basic fundamental concept for the programming of the digital electronics.

1. MATRUSRI ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
SUBJECT NAME: DIGITAL SYSTEM DESIGN WITH VERILOG HDL
FACULTY NAME: Mrs. B. Indira Priyadarshini
MATRUSRI
ENGINEERING COLLEGE

2. INTRODUCTION:
This unit is intended to provide a thorough coverage of verilogHDL concepts
based on fundamental principles of digital design.
This is the basic fundamental concept for the programming of the digital
electronics.
UNIT-I
OUTCOMES:
After successful completion of this Unit , students should be able to
1.Understand the importance of HDL (Hardware Descriptive Language)
2.Apply the knowledge of Boolean algebra to design and development digital
systems.
3.Learn conventional structural modeling of digital systems.
4.Learn Hierarchical digital system building.
5.Continuous assignment operator based model construction will be learnt.
MATRUSRI
ENGINEERING COLLEGE

3. CONTENTS:
Overview of Digital Design with VerilogHDL
Evolution of computer aided digital circuit design
Emergence of HDLs
Typical design flow
OUTCOMES:
Students will be able to know about introduction of Hardware descriptive
languages.
MODULE-I: Introduction to HDLs
MATRUSRI
ENGINEERING COLLEGE

4. Digital circuits were designed with:
1. Vacuum tubes
2. Transistors
3. Integrated circuits (ICs)
SSI : tens of gates
MSI : hundreds of gates
LSI : thousands of gates
VLSI : more than 100,000 transistors
ULSI : Ultra Large Scale Integration
Hardware Description Language (HDL)
•Allowed designed to model the concurrency of processes found in
hardware elements
•VerilogHDL originated in 1983
•VHDL was developed under contract from DARPA
•Could be used to describe digital circuits at a register transfer level (RTL)
Overview of Digital Design with Verilog
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5. Design Flow
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Design Specification
Behavioral Description
RTL Description (HDL)
Functional Verification and Testing
Logic Synthesis/ Timing Verification
Gate-Level Netlist
Logical Verification and Testing
Floor Planning
Automatic Place and Route
Physical Layout
Layout Verification
Implementation

6. 1.The full form of HDL isHardware Description Language
2.VHDL is being used for Ans: a) Documentation
b) Verification
c) Synthesis of large digital design
3.Verilogis standardised as IEEE 1364
4.The Verilogis lessflexible compared to the VHDL
5.Verilogprovide morefeatures for transistor-level descriptions compared
to VHDL.
Questions & Answers
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7. CONTENTS:
Lexical Conventions
Data types
System tasks and Compiler Directives
OUTCOMES:
Students will be able to know the
•Knowledge of language constructs
•Pertaining to Semantic and syntactical errors in programming using HDL
MODULE-II: Basic Concepts
MATRUSRI
ENGINEERING COLLEGE

8. Lexical Conventions
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Whitespace
Blank space (\b)
Tabs (\t)
Newlines (\n)
Comments
//: single line
/* … */ : multiple line
Operators
Unary: ~、!
Binary: +、-、&&
Ternary: a = b ? c : d;
String
“Hello VerilogWorld”
“a/b”
Identifiers and Keywords
regvalue;
input clk;
Number Specification
•Sized numbers: <size>’<base
format><number>
4’b1111
12’habc
16’d255
•Unsizednumbers
23456
‘hc3
‘o21
•X (unknown) and Z (high impedance)
12’h13x
6’hx
32’bz
•Negative numbers
-8’d3
•Underscore characters and
Question marks
12’b1111_0000_1010 equals to
12’b111100001010
4’b10?? equals to 4’b10zz

9. Data Types
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Value Set and Strength
Value levelCondition in HardwareCircuits
0 0,False
1 1, True
x Unknown
z High impedance,floating state
Strength Level Type Degree
supply Driving strongest
Weakest
strong Driving
pull Driving
large Storage
weak Driving
medium Storage
small Storage
highz High Impedance

10. Data Types
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Net
Used to represent connections between hardware elements
Keyword: wire, wand, wor, tri, trior, trireg
wire a;
wire b, c;
wire d = 1’b0;
Register
Storage element for data not same as “hardware register”
Similar to variables in C reg reset;
initial
begin
reset = 1’b1;
#100 reset = 1’b0;
end

11. Data Types
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Vectors
•wire and register can be defined as “vector” form format
[high#:low#] or [low#:high#]
•Subset of vector: Partial bits of vector
•Fixed width subset: [<starting_bit>+:width] or [<starting_bit>-:width]
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;
bus A[7]
bus[2:0]
virtual_addr[0:1]
reg [255:0] data1; reg [0:255] data2;
reg [7:0] byte;
byte = data1[31-:8]; // data1[31:24]
byte = data1[24+:8]; // data1[31:24]
byte = data2[31-:8]; // data2[24:31]
byte = data2[24+:8]; // data2[24:31]
for (j=0; j<=31; j=j+1) // [7:0], [15:8]…[255:248]
byte = data[(j*8)+:8];
data1[(byteNum*8)+:8] = 8’b0;

12. Data Types
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Integer, Real, and Time Register Data
Integer: can represent “signed” number
Real:
Time: Storing simulation time
integer counter;
initial
counter = -1;
real delta;
initial begin
delta = 4e10;
delta = 2.13;
end
integer i;
initial
i = delta; // rounded value of 2.13
time save_sim_time;
initial
save_sim_time = $time;

13. Data Types
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Arrays
•Type: integer, register, time, real, or vector.
•Dimension: no limit, but dimension must be constant
•Format:
<array_name>[<subscript>]
•Assignment of values to array elements
integer count[0:7];
reg bool[31:0];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][0:255];
reg [63:0] array_4d [15:0][7:0][7:0][255:0];
wire [7:0] w_array2 [5:0];
wire w_array1[7:0][5:0];
count[5] = 0;
chk_point[100] = 0;
port_id[3] = 0;
matrix[1][0] = 33559;
araay_4d[0][0][0][0][15:0] = 0;fff
port_id = 0; // error usage
matrix[1] = 0; // error usage

14. Data Types
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Memories
Array of registers
reg mem1bit [0:1023];
reg [7:0] membyte [0:1023];
membyte[511]
Parameters
Define a constant
•Can be re-defined at higher level using “defparam”
•localparam(Verilog2001 new feature)
Can not be re-defined by “defparam”
parameter port_id = 5;
parameter cache_line_width = 256;
parameter signed [15:0] WIDTH;

15. Data Types
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Strings
Can be assigned to register
Escaped CharactersCharacter Displayed
\n new line
\t tab
\% %
\\ \
\” “
\ooo Character written in 1-3 octaldigits

16. System Tasks
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Displaying information
$display (p1, p2, p3,…, pn);
Format specification list
Format Display
%d or %D decimal value
%b or %B binary value
%s or %S String
%h or %H Hexadecimal value
%c or %C ASCII character
%m or %M hierarchical name
%v or %V strength of a variable
%o or %O octal value
%t or %T current time format
%e or %E real number in scientific format (e.g., 3e10)
%f or %F real number indecimal format (e.g.,2.13)
%g or %G real number in shorter format, decimal or scientific

17. System Tasks
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Displaying information
//Include the string to be displayed within quotes
$display (“Hello World”);
//to display current simulation time
$display($time);
//to display 41-bit virtual address at current time
reg[0:40] virtual_addr;
$display(“At time %d, the virtual address is %h”,$time, virtual_addr);
/*Special Characters*/
//to display special characters, multiline and %sign
$display(“This is a \n multiline string with a %% sign”);
//output
This is a
multiline string with a % sign

18. System Tasks
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Monitoring Information
$monitor(p1,p2,…, pn); Monitor signal change and output the change
initial
begin
$monitor($time, “value of signals clock=%b reset=%b”, clock, reset);
end
0 value of signals clock=0 reset=1
5 value of signals clock=1 reset=1
10 value of signals clock=0 reset=0
Stopping and finishing
$stop: stop simulation and enter interactive mode to debug
$finish: end of simulation
initial
begin
clock=0;
reset=1;
#100 $stop; //stop at time 100 in the simulation and examine the results
#900 $finish; //finish at simulation time 1000
end

19. Compiler Directives
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`define: Define text macro, like #define in C
`include: Include the context of another file, like #include in C
//define a text macro that defines the word size
`define WORD_SIZE 32
/*define an alias such that $stop is substituted whenever`S appears*/
`define S $stop;
/*define a frequently used text string which can then be used as 32-bit
register `WORD_REG reg32; */
`define WORD_REG reg[31:0];
/*include the header file header.vwhich contains declarations in the main
verilogfile design.v*/
`include header.v
…
<verilogcode in file design.v>
…

20. 1.$stop system task to suspend simulation.
2.Unaryoperator which precedes the operand.
3.Xis the default value for register data type.
4.Parameter value can be overridden at module instance by `define.
5.#40 $finish indicates end of simulation at 40 time units.
Questions & Answers
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21. CONTENTS:
Design Methodologies
Modules
Instances
Components of a Simulation
OUTCOMES:
Students should be able to
•Understand design methodologies for digital design
•Define a stimulus block and design block
MODULE-III: Hierarchical Modeling
Concepts
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ENGINEERING COLLEGE

22. Top-down Design Methodology
Define the final (top) module
Analyze the components which are composed of top module step by step
Design Methodology
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Bottom-up Design Methodology
Design the basic components
Assemble basic components to larger design until the top design is
completed

23. Hierarchy of 4-bit Ripple Carry Counter
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Top-down
Bottom-up

24. Basic component in verilogfor describing/defining a hardware
Modules
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module<module_name> (<module_terminal_list>);
…
<module internals>
…
…
endmodule
A module for T F.F.
moduleT_FF (q, clock , reset);
…
…
<functionality of T-flipflop>
…
…
endmodule

25. Levels of functionality
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Different Levels of Abstraction
Behavioral / Architecture / Algorithm Level
Describe the functionality (behavior) of a circuit
Dataflow / Register Transfer Logic (RTL) Level
Describe the data flow of a circuit
Gate Level
Describe the connectivity (structure) of a circuit
Switch Level

26. Instances
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Individual object of module
Moduleis similar to “function declaration” in C, and instancelikes the
concept of “function call”
Instantiation
A procedure of constructing an instance using module
// Define Top-level block called ripple carry counter.
moduleripple_carry_counter(q, clk, reset);
output[3:0] q;
inputclk, reset;
//4 instances of the module T_FF are created.
T_FFtff0(q[0],clk, reset);
T_FFtff1(q[1],q[0], reset);
T_FFtff2(q[2],q[1], reset);
T_FFtff3(q[3],q[2], reset);
endmodule

27. Instances
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//Module T-FF instantiates a D-
flipflop
moduleTFF(q, clk, reset);
outputq;
inputclk, reset;
wired;
DFF dff0(q, d, clk, reset);
//Instantiate D_FF. Call it dff0
notn1(d, q);
//not gate is a verilogprimitive
endmodule
//Module of a D-flipflop
moduleD_FF (q, d, clk, reset);
outputq;
inputd, clk, reset;
regq;
always@(posedgereset or
negedgeclk)
if(reset)
q<=1´b0;
else
q<=d;
endmodule
T_FF is instantatedwithin ripple_carry_counter
D_FF and not are instantiated within T_FF
Structural interconnect is established through instantiation

28. Components of a Simulation
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Design Under Test (DUT) －Design Block
Test bench －Stimulus Block
Stimulus generation
Output checking
Stimulus Block –I
Instantiate a design under test (dut)
(Design Block)
Ripple Carry Counter
clk reset
(Stimulus Block)
q
Stimulus Block –II
Additional top module instantiating
stimulus and design block
Stimulus
Block
d_clk
d_reset
c_q
Design
Block
clk
reset
q
Top-level Block

29. Stimulus Block (Test bench)
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module stimulus;
regclk;
regreset;
wire[3:0] q;
ripple_carry_counterr1(q, clk, reset); // instantiate the design block
initial clk= 1'b0; // Control the clock
always #5 clk= ~clk;
initial // Control the reset
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $finish;
end
initial // Monitor the outputs
$monitor($time, " Output q = %d", q);
endmodule

30. Simulation results and Output Waves
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0 Output q = 0
20Output q = 1
30Output q = 2
40Output q = 3
50Output q = 4
60Output q = 5
70Output q = 6
80Output q = 7
90Output q = 8
100Output q = 9
110 Output q = 10
120Output q = 11
130Output q = 12
140Output q = 13
150 Output q = 14
160 Output q = 15
170 Output q = 0
180 Output q = 1
190 Output q = 2
195 Output q = 0
210 Output q = 1
220 Output q= 2

31. 1.The Process of creating object from a moduetemplate is called
instantiation.
2.The functionality of the design block can be tested by applyingstimulus
and checking results.
3.Modules are the basic building blocks in Verilog.
4.A module can be implemented in terms of the design algorithm without
concern for the hardware implementation is a Behaviouallevel modeling.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

32. CONTENTS:
Modules
Ports
Hierarchical Names
OUTCOMES:
Students should be able understand how to define, declare and connect the
ports for a module in verilog.
MODULE-IV: Modules and Ports
MATRUSRI
ENGINEERING COLLEGE

33. Modules
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ENGINEERING COLLEGE
Basic component in Verilogfor describing/defining a hardware
module<module_name> (<module_terminal_list>);
<I/O declaration>
<parameter declaration>
…
<module internals>
…
…
endmodule
Components of Modules
Variables Declaration
Dataflow Statement
Module Instantiation
Behavior Statement
Tasks and Functions

34. Components of Modules
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Module Name,
Port List, Port Declarations (is ports present)
Parameters (optional)
Declarations of wires,
regs and other variables
Data flow statements
(assign)
Instantiation of lower
level modules
alwaysand intialblocks
All behavioral statements
Tasks and Functions
endmodule statement

35. Ports
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I/O Interfaceused to communicate with external module
“No” port declaration if do not need to communicate with other module, such
as Top module
Module fulladd4has five ports while tophas no port.
a, b,and c_inare input ports and sumand c_outare output ports.
module fulladd4(sum, c_out, a, b, c_in);//module with a list of ports
module Top; //no port list as Top is the top-level module in simulation

36. Port Declaration
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ENGINEERING COLLEGE
Three types
input
output
inout
VerilogKeyword Type of Port
input Input port
output Output port
inout Bidirectional port
Port Declaration
module FA4(sum, c_out, a, b, c_in);
//begin port declarations
output [3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in;
//end port declarations section
<module internals>
…
endmodule
ANSI C Port Declaration
module FA4(output reg[3:0] sum,
output regc_cout, input [3:0] a, b, input
c_in);
//wire by default
…
<module internals>
…
endmodule

37. Port Connection Rules
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Input Port
Internal view－viewed as “a wire/net”
External view－can be connected to a regor wire
Output Port
Internal view－declaredas a regor wire
External view－onlybe connected to a wire
Inout Port
viewed as a wire/net regardless of internal or external module

38. Port Connection Rules
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ENGINEERING COLLEGE
Mismatch of internal and external port connections
Simulation should issue a warning for this condition
Floating of port connection
Fulladd4 fa0(sum, , a, b, c_in); // c_out floating
Illegal connection of internal and external ports
Connecting Ports to External Signals
Connecting ports by module declaration sequence
Connecting ports by name
Connecting Ports by Name
Fulladd4 fa_byname(.c_out(c_out), .sum(sum),
.b(b), .c_in(c_in), .a(a));
Fulladd4 fa_byname(.sum(sum), .b(b),
.c_in(c_in), .a(a));

39. Port Connection Rules
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Connecting Ports by Module Declaration Sequence
module Top;
reg[3:0] A, B;
regC_IN;
wire [3:0] SUM;
wire C_OUT;
//instantiate fulladd4 where signals are connected in order i.e., by position
fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN);
…
<stimulus>
…
Endmodule
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;
…<module internals>…
endmodule

40. Port Connection Rules
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Named each instance, variables and signals in hierarchical design
Root module
Never be referenced by other modules, such as stimulus
Hierarchical instances are separated by dotsign “.”
$display (“%m”)
display hierarchical level of that module
stimulus
(root level)
m1
(SR_latch)
q, qbar
set, reset
(variables)
Q, Qbar
S, R
(signals)
n1(nand )
n2(nand )

41. 1.Portsprovides he interface by which a module can communicate with its
environment.
2.Inout ports must always be of the type net.
3.Connection between signals specified in the module instantiation and the
ports in module definition is done by ordered list or by name.
4.Hierarchical name allows to denote every identifier with a unique name.
Questions & Answers
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42. CONTENTS:
Gate Type
Gate Delays
OUTCOMES:
Students should be able to
•Identify and understands how to construct a logic gate primitives provided in
verilog
•Describe delays in the gate level design
MODULE-V: Gate-level Modeling
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ENGINEERING COLLEGE

43. Gate Type
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And/OrGate Primitive
Two Types of Basic Primitives
•And/Orgate
•Buf/Not gate

44. Gate Type
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Using Gate Primitive
wire OUT, IN1, IN2;
//basic gate instantiations
and a1(OUT, IN1, In2);
nandna1(OUT, IN1, IN2);
or or1(OUT, In1, In2);
nor nor1(OUT, IN1, IN2);
xorxor1(OUT, In1, In2);
xnorxnor1(OUT, IN1, IN2);
//more than two inputs
nandna1_3ip(OUT, IN1, IN2, IN3)l
//gate instantiation without specifying instance name
and (OUT, IN1, IN2);

45. Gate Type
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Buf/Not Gate Primitive
•buf
•not
•bufif
•notif
//basic gate instantiations
bufb1(OUT1, IN);
not n1(OUT1, IN);
//more than two outputs
bufb1_2ops(OUT1, OUT2, IN);
//gate instantiation without instance name
not (OUT1, IN);

46. Gate Type
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Bufif/NotifGate Primitive
//instantiation of bufifgates
bufif1 b1(out, in, ctrl1);
bufif0 b0(out, in, ctrl1);
//instantiation of notifgates
notif1 n1(out, in, ctrl1);
notif0 n0(out, in, ctrl1);

47. Gate Type
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Array of Instances
Avoid repetition of gate instantition
wire [7:0] OUT, IN1, IN2;
nandn_gate[7:0] (OUT, IN1, IN2);
//this is equivalent to the following 8 instantiations
nandn_gate0 (OUT[0], IN1[0], IN2[0]);
nandn_gate1 (OUT[1], IN1[1], IN2[1]);
nandn_gate2 (OUT[2], IN1[2], IN2[2]);
nandn_gate3 (OUT[3], IN1[3], IN2[3]);
nandn_gate4 (OUT[4], IN1[4], IN2[4]);
nandn_gate5 (OUT[5], IN1[5], IN2[5]);
nandn_gate6 (OUT[6], IN1[6], IN2[6]);
nandn_gate7 (OUT[7], IN1[7], IN2[7]);

48. Gate Delays
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Rise delay
The delay that an output rises a logic 1
Fall delay
The delay that an output falls to a logic 0
Trun-off delay
The delay that an output turns to be a z
t_rise
0, xor z
1
t_fall
1, xor z
0

49. Gate Delays
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//delay of delay_timefor all transactions
and #(delay_time) a1(out, i1, i2);
//Rise and Fall delay specification
and #(rise_val, fall_val) a2(out, i1, i2);
//Rise, Fall, and Turn-off delay specification
bufif0 #(rise_val, fall_val, turnoff_val) b1(out, in, control);
Examples:
and #5 a1(out, i1, i2); //delay of 5 for all transactions
and #(4, 6) a2(out, i1, i2);// Rise=4, Fall=6
bufif0 #(3, 4, 5) b1(out, in, control);//Rise=3, Fall=4, Turn_off=5

50. Gate Delays
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Min/Typ/Max Delay Values
Each rise, fall and turn-off delays have three types of values
Min: The expected minimum delay
Typ: The expected typical delay
Max: The expected maximum delay
Use +maxdelays, +typdelays(default), or +mindelaysto choose delay values
when execution
//if +mindelays, delay=4, +typdelays, delay=5, +maxdelays, delay=6
and #(4:5:6) a1(out, i1, i2); //one delay
//if +mindelays, rise=3, fall=5, turn_off=min(3,5)
//if +typdelays, rise=4, fall=6, turn_of==min(4,6)
//if +maxdelays, rise=5, fall=7, turn_off=min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2); //two delays
//if +mindelays, rise=2, fall=3, turn_off=4
//if +typdelays, rise=3, fall=4, turn_off=5
//if +maxdelays, rise=4, fall=5, turn_off=66
and #(2:3:4, 4:5:6, 5:6:7) a3(out, i1, i2); //three delays

51. Gate Delays
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Define Delay Value in VerilogCompilation
//invoke simulation with maximum delay
> verilogtest.v+maxdelays
//invoke simulation with minimum delay
> verilogtest.v+mindelays
//invoke simulation with typical delay
> verilogtest.v+typdelays

52. Delay Example
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module D (out, a, b, c);
// I/O port declarations
output out;
input a, b, c;
//Internal nets
wire e;
//Instantiate primitive gates to build the circuit
and #(5) a1(e, a, b); //delay of 5 timeunitson gate a1
or #(4) o1(out, e, c); //delay of 4 time units on gate o1
endmodule
Out = (a • b) + c

53. Delay Example
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module stimulus;
//declare variables
regA, B, C;
wire OUT;
//instantiate the module D
D d1(OUT, A, B);
//stimulate the inputs. Finish the simulation at 40 time units
initial
begin
A=1´b0; B=1´b0; C=1´b0;
#10 A=1´b1; B=1´b1; C=1´b1;
#10 A=1´b1; B=1´b0; C=1´b0;
#20 $finish;
end
end module
Simulation Results:

54. 1.Min, typ, max values can be chosen at verilogrun time.
2.Verilogsupports basic logic gates as predefined primitives.
3.Setup time is the minimum time the data cannot change after active clock
edge.
4.Turn off delay means, gate output transition to Z.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

55. CONTENTS:
Continuous Assignments
Delays
Expressions, Operators and Operands
Operator Types
OUTCOMES:
Student will able to use dataflow constructs to model practical digital
circuits in verilog.
MODULE-VI: Dataflow Modeling
MATRUSRI
ENGINEERING COLLEGE

56. Continuous Assignments
MATRUSRI
ENGINEERING COLLEGE
Assign a logic value to a wire/net
Syntax
•Continuous_assign::= assign[drive_strength] [delay] list_of_assignments;
•list_of_net_assignments::=net_assignment{, net_assignment}
•net_assignment::=net_lvalue= expression
•Default drive_strength: strong1 or strong0
•Delay: propagation time from inputs to output
Constraints
•LHS of assignment (=) must be scalar net or vector net (rather than reg
or vector reg)
•Once the value of RHS expression changes, the value of assigned wire
also changes accordingly
•The expression of RHS can be reg, wire or function
•Delay controls the update time of LHS when the value of RHS has
changed like gate delay

57. Continuous Assignments
MATRUSRI
ENGINEERING COLLEGE
Example:
//continuous assignment. out is a net, i1 and i2 are nets
assign out=i1 & i2;
/* continuous assign for vector nets. addris a 16-bit vector net addr1 and
addr2 are 16-bit vector registers */
assign addr[15:0]=addr1_bits[15_0]^addr2_bits[15:0];
//concatenation. LHS is the concatenation of a scalar net and a vector net
assign {c_out, sum[3:0]}=a[3:0]+b[3:0]+c_in;
Implicit Continuous Assignment
Perform a wire assignment when declaring the wire
wire out;
assign out = in1 & in2; (equals the following)
wire out = in1 & in2;
Implicit Net Declaration
Perform assignment for an un-declared wire
•wire i1, i2;
assign out = i1 & i2; // wire out has not been declared

58. Delays
MATRUSRI
ENGINEERING COLLEGE
Regular Assignment Delay
assign #10 out = in1 & in2;
Implicit Continuous Assignment Delay
•wire #10 out = in1 & in2; (equals the following)
•wire out;
assign #10 out = in1 & in2;
Net Declaration Delay
•wire #10 out;
assign out = in1 & in2; (equals the following)
•wire out;
assign #10 out = in1 & in2;

59. Expressions, Operators and Operands
MATRUSRI
ENGINEERING COLLEGE
Expressions
Combine operator and operand to output a result
a^b, addr1[20:17] + addr2[20:17], in1 | in2
Operands
•Data type －constants, integers, real, nets, registers, times, bit-select, part-
select, memory or function calls
•Integer count, final_count;
final_count= count + 1;
•real a, b, c;
c = a –b;
•reg[15:0] reg1, reg2;
reg[3:0] reg_out;
reg_out= reg1[3:0] ^ reg2[3:0];
•regret_value;
ret_value= calculate_parity(A, B);
Operators
Perform an operation on operands
•d1 && d2 // && operates on operands d1 and d2
•!a[0]
•B1>>1

60. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Operator TypeOperator
Symbol
Operation
Performed
Number of
operands
Arithmetic *
/
+
-
%
**
Multiply
Divide
Add
Subtract
Modulus
exponent
two
two
two
two
two
two
Logical !
&&
||
Logical negation
Logical and
Logical or
one
two
two
Relational >
<
>=
<=
greater than
less than
greater than or
equal
less than or equal
two
two
two
two

61. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Operator TypeOperator
Symbol
Operation
Performed
Number of
operands
Equality ==
!=
===
!==
equality
inequality
case equality
case inequality
two
two
two
two
Bitwise ~
&
|
^
^~ or ~^
bitwise negation
bitwise and
bitwise or
bitwise xor
bitwise xnor
one
two
two
two
two
Reduction &
~&
|
~|
^
^~ or~^
reduction and
reduction nand
reduction or
reduction nor
reduction xor
reduction xnor
one
one
one
one
one
one

62. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Operator TypeOperator
Symbol
Operation
Performed
Number of
operands
Shift >>
<<
>>>
<<<
right shift
left shift
arithmetic right
shift
arithmetic left
shift
two
two
two
two
Concatenation
Replication
{ }
{ { } }
concatenation
Replication
any number
any number
Conditional ? : conditional three

63. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Arithmetic Operators
Binary Operator (+, -, *, /, **, %)
•in1 = 4’b101x; in2 = 4’b1010;
sum = in1 + in2; // 4’bx
•13 % 3
•16 % 4
•-7 % 2
•7 % -2
Unary Operator (+, -)
•-4
•+5
Logical Operators
&&(logic-and), ||(logic-or), !(logic-not)
A = 3; B = 0;
A && B
A || B
!A
!B
A = 2’0x; B = 2’b10;
A && B
( a == 2) && (b == 3)
Relational Operators (>, <, <=, >=)
A = 4, B = 3, X = 4’b1010, Y = 4’b1101, Z = 4’b1xxx
A <= B
A > B
Y >= X
Y < Z

64. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Equality Operators: Logic Equality (==, !=)
Case Equality (===, !==)
ExpressionDescription Possible Logical value
a==b a equal to b, result unknown if xor z
in a,b
0,1,x
a!=b a not equal to b, result unknown if x
or zin a,b
0, 1, x
a===b a equal to b, including x and z0,1
a!==b a not equal to b, including x and z0,1
A = 4, B = 3, X = 4’b1010, Y = 4’b1101, Z = 4’b1xxz, M = 4’b1xxz, N = 4’b1xxx
•A == B // 0
•X != Y // 1
•X == Z // x
•Z === M // 1
•Z === N // 0
•M !=== N // 1

65. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Bitwise Operators
~(Negation), & (and), | (or), ^ (xor), ^~ (xnor)
X = 4’b1010, Y = 4’b1101, Z = 4’b10x1
•~X // 4’b0101
•X & Y // 4’b1000
•X | Y // 4’b1111
•X ^ Y // 4’b0111
•X ^~ Y // 4’b1000
•X & Z // 4’b10x0
X = 4’b1010, Y = 4’b0000
•X | Y // 4’b1010
•X || Y // 1

66. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Reduction Operator
&, ~&, |, ~|, ^, ~^
X = 4’b1010
•&X // 1’b0
•|X // 1’b1
•^X // 1’b0, can be used to count even parity
Shift Operator
>>(right shift), <<(left shift), >>>(arithmetic right shift), <<<
X = 4’b1100
•Y = X >> 1; // 4’b0110
•Y = X << 1; // 4’b1000
•Y = X << 2; // 4’b0000
Integer a, b, c;
a = 0;
b = -10;
c = a + (b >>> 3);

67. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Concatenation Operator
{, }
A = 1’b1, B = 2’b00, C = 2’b10, D = 3’b110
•Y = { B, C }
•Y = { A, B, C, D, 3’b001 }
•Y = { A, B[0], C[1] }
Replication Operator
regA;
reg[1:0] B, C;
reg[2:0] D;
A = 1’b1; B = 2’b00; C = 2’b10; D = 3’b110;
Y = {4{A}}
Y = {4{A}, 2{B}}
Y = {4{A}, 2{B}, C}

68. Operation Types
MATRUSRI
ENGINEERING COLLEGE
Operator Precedence
Operators Operator Symbols Precedence
Unary
Multiply,Divide, Modulus
+ -! ~
* / %
Highest Precedence
Add, Subtract
Shift
+ -
<< >>
Relational
Equality
< <= > >=
== != === !==
Reduction
Logical
&, ~&, |, ~|, ^,~^
&& ||
Conditional ?: Lowest precedence
Conditional Operator
Condition_expr? ture_expr: false_expr;
•assign addr_bus= drive_enable? Addr_out: 36’bz;
•assign out = control ? in1 : in0;
•assign out = (A == 3) ? (control ? x : y) : (control ? m : n);

69. 1.The left hand side of procedural continuous assignment can be Register or
concatenation of registers.
2.The "shift right" (>>) operator inserts zeroson the left end of its argument.
3.The two types of "or" operators are "logical"and "bitwise“.
4.The expression of RHS can be reg, wire or function.
5.a === b, includingx and z
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

70. CONTENTS:
Types of Delay Models
Path Delay Modeling
Timing Checks
Delay Back -Annotation
OUTCOMES:
Student will able to
•Identify types of delay models used in verilogsimulation
•Define system task from timing checks
•Understand delay back-annotation
MODULE-VII: Timing and Delays
MATRUSRI
ENGINEERING COLLEGE

71. Delay Models
MATRUSRI
ENGINEERING COLLEGE
Distributed Delay
//Gate-level modules
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Delay is distributed to each gate.
and #5 a1(e, a, b);
and #7 a2(f, c, d);
and #4 a3(out, e, f);
endmodule
//Data flow definition of a module
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Distributed delay in each expression
assign #5 e = a & b;
assign #7 f = c & d;
assign #4 out = e & f;
endmodule

72. Delay Models
MATRUSRI
ENGINEERING COLLEGE
Lumped Delay
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
and a1(e, a, b);
and a2(f, c, d);
and #11 a3(out, e, f);
//delay only on the output gate
endmodule
Pin-to-pin delays
•Also known as path delays
•Delay from any input to any output
port
•Gate-level, dataflow, and behavioral
delays: Distributed or Lumped
Path a-e-out, delay = 9
Path b-e-out, delay = 9
Path c-f-out, delay = 11
Path d-f-out, delay = 11

73. Specify Block
Assign pin-to-pin delays
Define specparamconstants
Setup timing checks in the design
Path Delay Modeling
MATRUSRI
ENGINEERING COLLEGE
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Specify block with path delay statements
specify
(a => out) = 9;
(b => out) = 9;
(c => out) = 11;
(d => out) = 11;
endspecify
//gate instantiations
and a1(e, a, b); and a2(f, c, d); and a3(out, e, f);
endmodule

74. Parallel connection
Syntax:
specify
(<src_field> =><dest_field>)=<delay>;
endspecify
<src_field> and <dest_field> are vectors of equal length
•Unequal lengths, compile-time error
Path Delay Modeling
MATRUSRI
ENGINEERING COLLEGE
//bit-to-bit connection. both a and out are single-bit
(a => out) = 9;
//vector connection. both a and out are 4-bit vectors a[3:0], out[3:0]
(a => out) = 9;
(or)
(a[0] => out[0]) = 9;
(a[1] => out[1]) = 9;
(a[2] => out[2]) = 9;
(a[3] => out[3]) = 9;
//illegal connection. a[4:0] is a 5-bit vector, out[3:0] is 4-bit.
//Mismatch between bit width of source and destination fields
(a => out) = 9; //bit width does not match.

75. Full connection
Syntax:
specify
(<src_field> *><dest_field>)=<delay>;
endspecify
No need to equal lengths in <src_field> and <dest_field>
Path Delay Modeling
MATRUSRI
ENGINEERING COLLEGE
module M (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//full connection
specify
(a,b*> out) = 9;
(c,d*> out) = 11;
endspecify
and a1(e, a, b);
and a2(f, c, d);
and a3(out, e, f);
endmodule

76. Edge-SensitivePaths
•Anedge-sensitivepathconstructisusedtomodelthetimingofinputto
outputdelays,whichoccursonlywhenaspecifiededgeoccursatthesource
signal.
•(posedgeclock=>(out+:in))=(10:8);
Path Delay Modeling
MATRUSRI
ENGINEERING COLLEGE
specparamconstants
•Similar to parameter, but only inside specify block
•Recommended to be used instead of hard-coded delay numbers
//Specify parameters using specparamstatement
specify
//define parameters inside the specify block
specparamd_to_q= 9;
specparamclk_to_q= 11;
(d => q) = d_to_q;
(clk=> q) = clk_to_q;
endspecify

77. Path Delay Modeling
MATRUSRI
ENGINEERING COLLEGE
Conditional path delays
•Delay depends on signal values
•Also called State-Dependent Path Delay (SDPD)
module M (out, a, b, c, d);
output out; input a, b, c, d; wire e, f;
specify
if (a) (a => out) = 9;
if (~a) (a => out) = 10;
//Conditional expression contains two signals b , c.
//If b & c is true, delay = 9,
//Conditional Path Delays
if (b & c) (b => out) = 9;
if (~(b & c)) (b => out) = 13;
//Use concatenation operator & Use Full connection
if ({c,d} == 2'b01) (c,d*> out) = 11;
if ({c,d} != 2'b01) (c,d*> out) = 13;
endspecify
and a1(e, a, b); and a2(f, c, d); and a3(out, e, f);
endmodule

78. Path Delay Modeling
MATRUSRI
ENGINEERING COLLEGE
Rise, fall, and turn-off delays
//Specify one delay only. Used for all transitions.
specparamt_delay= 11;
(clk=> q) = t_delay;
//Specify two delays, rise and fall
specparamt_rise= 9, t_fall= 13; (clk=> q) = (t_rise, t_fall);
//Specify three delays, rise, fall, and turn-off
specparamt_rise= 9, t_fall= 13, t_turnoff= 11;
(clk=> q) = (t_rise, t_fall, t_turnoff);
//specify six delays.
specparamt_01 = 9, t_10 = 13, t_0z = 11;
specparamt_z1 = 9, t_1z = 11, t_z0 = 13;
(clk=> q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0);
//specify twelve delays.
specparamt_01 = 9, t_10 = 13, t_0z = 11;
specparamt_z1 = 9, t_1z = 11, t_z0 = 13;
specparamt_0x = 4, t_x1 = 13, t_1x = 5;
specparamt_x0 = 9, t_xz= 11, t_zx= 7;
(clk=> q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0, t_0x, t_x1, t_1x, t_x0, t_xz, t_zx);

79. Path Delay Modeling
MATRUSRI
ENGINEERING COLLEGE
Min, max, and typical delays
•Any delay value can also be specified as (min:typ:max)
t_rise= 8:9:10, t_fall= 12:13:14, t_turnoff= 10:11:12;
(clk=> q) = (t_rise, t_fall, t_turnoff);
Handling x transitions
•Pessimistic approach
Transition to x: minimum possible time
Transition from x: maximum possible time
specparamt_01 = 9, t_10 = 13, t_0z = 11;
specparamt_z1 = 9, t_1z = 11, t_z0 = 13;
(clk=> q) = (t_01, t_10, t_0z, t_z1, t_1z, t_z0);
TransitionDelayValue
0->x min(t_01,t_0z)
1->x min(t_10,t_1z)
z->x min(t_z0,t_z1)=9
x->0 max(t_10,t_z0)
x->1 max(t_01,t_z1)
x->z max(t_1z,t_0z)=11

80. Timing Checks
MATRUSRI
ENGINEERING COLLEGE
A number of system tasks defined for this:
$setup: checks setup-time of a signal before an event
$hold: checks hold-time of a signal after an event
$width: checks width of pulses
$setup check
Syntax:
$setup(data_event, reference_event, limit);
//Setup check is set.
//clock is the reference
//data is being checked for violations
//Violation reported
if Tposedge_clk-Tdata< 3
specify
$setup(data, posedgeclock, 3);
endspecify

81. Timing Checks
MATRUSRI
ENGINEERING COLLEGE
$hold check
Syntax:
$hold(reference_event, data_event, limit);
if Tdata-Tposedge_clk< 5 specify
$hold(posedgeclear, data, 5);
endspecify
$width check
Syntax:
$width(reference_event, limit);
if Tdata-Tclk< 6 specify
$width(posedgeclock, 6);
endspecify

82. Delay Back-annotation
MATRUSRI
ENGINEERING COLLEGE

83. 1.Surface mobility depends on effective gate voltage.
2.A fast circuit requires highgm.
3.Switching speed of a MOS device depends on
a) gate voltage above a threshold
b) carrier mobility
c) length channel
4.Increasing the substrate bias voltage Vsb, increasesthe threshold voltage.
5.The work function difference is negative for silicon substrate &
polysilicongate.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

84. CONTENTS:
Uses
Linking and Invocation
Accesses Routines
Utility Routines
OUTCOMES:
Student will able to learn how PLI is represented conceptually inside a
verilogsimulator.
MODULE-VIII: Programming Language Interface
MATRUSRI
ENGINEERING COLLEGE

85. Programming Language Interface
MATRUSRI
ENGINEERING COLLEGE
UsesofPLI
Defineadditionalsystemtasksandfunctions
•e.g.monitoringtasks,stimulustasks,…
Extractdesigninformationsuchashierarchy,connectivity,fanout,and
numberoflogicelementsofacertaintype.
Writespecial-purposeorcustomizedoutputdisplayroutines.
GeneralVerilog-basedapplicationsoftwarecanbewrittenwithPLI
routines.
•ThissoftwarewillworkwithallVerilogsimulatorsbecauseofthe
uniformaccessprovidedbythePLIinterface.ca
A simple PLI Task
#include "veriuser.h" /*include the file provided in release dir */
inthello_verilog()
{
io_printf("Hello VerilogWorld\n");
}
The io_printfis a PLI library routine that works exactly like printf.

86. Programming Language Interface
MATRUSRI
ENGINEERING COLLEGE
LinkingPLITasks
Wheneverthetask$hello_verilogisinvokedintheVerilogcode,theC
routinehello_verilogmustbeexecuted.
Thesimulatorneedstobeawarethatanewsystemtaskcalled
$hello_verilogexistsandislinkedtotheCroutinehello_verilog
•ThisprocessiscalledlinkingthePLIroutinesintotheVerilog
simulator.
•DifferentsimulatorsprovidedifferentmechanismstolinkPLIroutines.
InvokingPLITasks
Oncetheuser-definedtaskhasbeenlinkedintotheVerilogsimulator,itcan
beinvokedlikeanyVerilogsystemtaskbythekeyword$hello_verilog:
module hello_top;
$hello_verilog;
//Invoke the user-defined task hello_verilog
endmodule

87. Programming Language Interface
MATRUSRI
ENGINEERING COLLEGE
AccessRoutines
Accessroutinescanreadinformationaboutobjectsinthedesign.
Objectscanbeoneofthefollowingtypes:
oModuleinstances,moduleports,modulepin-to-pinpaths,intermodulepaths,
Top-levelmodules,Primitiveinstances,primitiveterminals,Nets,registers,
parameters,specparams,Integer,time,andrealvariables,Timingchecks,
Namedevents
Mechanics of access routines
Accessroutinesalwaysstartwiththeprefixacc_.
Auser-definedCroutinethatusesaccessroutinesmustfirstinitializethe
environmentbycallingtheroutineacc_initialize().
Whenexiting,theuser-definedCroutinemustcallacc_close().
#include"acc_user.h"
Accessroutinesusetheconceptofahandletoaccessanobject.
•Handlesarepredefineddatatypesthatpointtospecificobjectsinthe
design.
•handletop_handle;

88. Programming Language Interface
MATRUSRI
ENGINEERING COLLEGE
Typesofaccessroutines
Handleroutines:Theyreturnhandlestoobjectsinthedesign.“acc_handle_”.
Nextroutines:Theyreturnthehandletothenextobjectinthesetofa
givenobjecttypeinadesign.“acc_next_”
ValueChangeLink(VCL)routines:Theyallowtheusersystemtasktoadd
anddeleteobjectsfromthelistofobjectsthataremonitored.“acc_vcl_”
Fetchroutines:Theycanextractavarietyofinformationaboutobjects(e.g.
hierarchicalpathname,relativename)“acc_fetch_”
UtilityRoutinespopularlycalled"tf"routines
UtilityroutinesaremiscellaneousPLIroutinesthatpassdatainboth
directionsacrosstheVerilog/userCroutineboundary.
•Dolongarithmetic,Displaymessages,Halt,terminate,save,and
restoresimulation
Alwaysstartwiththeprefixtf_.
#include"veriuser.h"

89. 1.General Verilog-based application software can be written with PLI
routines.
2.The io_printfis a PLI library routine that works exactly like printf.
3.Access routines can read information about objects in the design.
4.Utility routines pass data in both directions across the Verilog.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

90. CONTENTS:
4 bit Full adder
4 bit Full adder cum Subtractor
Carry look a head adder
BCD adder
BCD adder cum Subtractor
Comparator
OUTCOMES:
Student will able to design and test a digital circuits in gateleveland dataflow
modeling.
MODULE-IX: Design of Arithmetic Circuits
using Gate level/ Data flow modeling:
MATRUSRI
ENGINEERING COLLEGE

91. Design 4-bit Full Adder
MATRUSRI
ENGINEERING COLLEGE

92. 4-bit Full Adder
MATRUSRI
ENGINEERING COLLEGE
1-bit Full Adder
module fa(sum, c_out, a, b, c_in);
output sum, c_out;
input a, b, c_in;
wire s1, c1, c2;
and (c1, a, b);
xor(sum, a, b, c_in);
and (c2, s1, c_in);
xor(c_out, c1, c1);
endmodule
Gate-level Modeling
module fa4(sum, c_out, a, b, c_in);
output [3:0] sum; output c_out;
input [3:0] a, b; input c_in;
wire c1, c2, c3;
fafa0(sum[0], c1, a[0], b[0], c_in);
fafa1(sum[1], c2, a[1], b[1], c1);
fafa2(sum[2], c3, a[2], b[2], c2);
fafa3(sum[3], c_out, a[3], b[3], c3);
endmodule
Data Modelingusing Addition and Concatenation Operator
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule

93. Testbench–4-bit Full Adder
MATRUSRI
ENGINEERING COLLEGE
module stimulus;
reg[3:0] A, B;
regC_IN;
wire [3:0] SUM;
wire C_OUT;
fa4 FA1_4(SUM, C_OUT, A, B, C_IN);
initial
begin
$monitor($time, “A=%b, B=%b, C_IN=%b, C_OUT=%b, SUM=
%b\n”, A, B, C_IN, C_OUT, SUM);
A=4´d3; B=4´d0; C_IN=1´b0;
#5 A=4´d3; B=4´d4;
#5 A=4´d2; B=4´d5;
#5 A=4´d9; B=4´d9;
#5 A=4´d10; B=4´d15;
#5 A=4´d10; B=4´d5;C_IN=1´1;
end
endmodule
Simulation Results:

94. 4-bit Full Adder Cum Subtractor
MATRUSRI
ENGINEERING COLLEGE

95. 4-bit Full Adder Cum Subtractor
MATRUSRI
ENGINEERING COLLEGE
Data flow Modelling:
module addsub4bit(
A, B, cin, sum,cout);
input [3:0] A,B;
input cin;
output [3:0] sum;
output cout;
wire [3:0]x;
assign x[0]=B[0]^cin,
x[1]=B[1]^cin,
x[2]=B[2]^cin,
x[3]=B[3]^cin;
assign {cout, sum}=A+x+cin;
endmodule
Structural Modelling:
module addsub4bit(A, B, cin, sum,cout);
input [3:0] A,B;
input cin;
output [3:0] sum;
output cout;
wire [3:0]x;
wire [3:1]c;
xor(x[0],B[0],cin);
xor(x[1],B[1],cin);
xor(x[2],B[2],cin);
xor(x[3],B[3],cin);
fa4 u0(A[0],x[0], cin, sum[0],c[1]);
fa4 u1(A[1],x[1],c[1], sum[1],c[2]);
fa4 u2(A[2],x[2],c[2], sum[2],c[3]);
fa4 u3(A[3],x[3],c[3], sum[3],cout);
endmodule

96. Carry Look Ahead Full Adder
MATRUSRI
ENGINEERING COLLEGE

97. Carry Look Ahead Full Adder
MATRUSRI
ENGINEERING COLLEGE
Gate-level Modeling
module carrylook(a, b, cin, sum, cout);
input [3:0] a,b; input cin;
output [3:0] sum; output cout;
wire [3:0]p,g,x; wire [4:1]c;
halfadderh1(a[0], b[0], p[0], g[0]); halfadderh2(a[1], b[1], p[1], g[1]);
halfadderh3(a[2], b[2], p[2], g[2]); halfadderh4(a[3], b[3], p[3], g[3]);
and (x[0], p[0], cin); and (x[1], p[1], c[1]);
and (x[2], p[2], c[2]); and (x[3], p[3], c[3]);
or (c[1], g[0], x[0]); or (c[2], g[1], x[1]);
or (c[3], g[2], x[2]); or (c[4], g[3], x[3]);
xor(sum[0], p[0], cin); xor(sum[1], p[1], c[1]);
xor(sum[2], p[2], c[2]); xor(sum[3], p[3], c[3]);
assign cout = c[4];
endmodule

98. Carry Look Ahead Full Adder
MATRUSRI
ENGINEERING COLLEGE
Dataflow Modeling
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire p0,g0, p1,g1, p2,g2, p3,g3;
wire c4, c3, c2, c1;
assign p0 = a[0] ^ b[0], p1 = a[1] ^ b[1], p2 = a[2] ^ b[2], p3 = a[3] ^ b[3];
assign g0 = a[0] & b[0],g1 = a[1] & b[1], g2 = a[2] & b[2], g3 = a[3] & b[3];
assign c1 = g0 | (p0 & c_in),
c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),
c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),
c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1
& p0 & c_in);
assign sum[0] = p0 ^ c_in,sum[1] = p1 ^ c1,sum[2] = p2 ^ c2,sum[3] = p3 ^ c3;
assign c_out = c4;
endmodule

99. BCD Adder
MATRUSRI
ENGINEERING COLLEGE

100. Design BCD Adder
MATRUSRI
ENGINEERING COLLEGE
Data flow Modelling:
module bcdadder( A, B, cin, sum,
cout);
input [3:0] A,B;
input cin;
output [3:0] sum;
output cout;
wire [3:0]Z;
wire K,X1,X2;
assign {K, Z}=A+B+cin;
assign X1=Z[3]&Z[2],
X2=Z[3]&Z[1],
Y=K|X1|X2;
assign {cout, sum} =
{1’b0,Y,Y,1’b0}+Z+1’b0;
endmodule
Structural Modelling:
module bcdadder(A, B, cin, sum, cout);
input [3:0] A,B;
input cin;
output [3:0] sum;
output cout;
wire [3:0]Z;
wire K,X1,X2;
fa4 f1(A, B, cin, Z, K);
and (X1, Z[3], Z[2]);
and (X2, Z[3], Z[1]);
or(Y, K, X1, X2);
fa4 f2({1’b0,Y,Y,1’b0}, Z, 1’b0, sum, cout);
endmodule

101. BCD Adder cum Subtractor
MATRUSRI
ENGINEERING COLLEGE
X3 = B3’B2’B1’M+B3M’
X2 = B2B1’+B2M’+B2’B1M
X1 = B1
X0 = B0M’+B0’M

102. Design BCD Adder Cum Subtractor
MATRUSRI
ENGINEERING COLLEGE
9’S COMPLIMENTER
module complimenter9( input [3:0] b, input m, output [3:0] x);
assign x[3]=(~b[3]&~b[2]&~b[1]&m) | (b[3]&~m),
x[2]=(b[2]&~b[1]) | (b[2]&~m) | (~b[2]&b[1]&m),
x[1]=b[1],
x[0]=b[0]^m;
endmodule
Structural Modelling:
module add_sub(A, B, CIN, M, F, COUT);
input [3:0]A,B;
input CIN,M;
output [3:0]F;
output COUT;
wire [3:0]X;
complementer9 c0(B,M,X);
bcdadderb0(A, X, CIN, F, COUT);
endmodule

103. 4-BIT COMPARATOR
MATRUSRI
ENGINEERING COLLEGE

104. 4-BIT COMPARATOR
MATRUSRI
ENGINEERING COLLEGE
Data flow Modelling:
module comparator4bit(a,b,
aeb, agb, alb);
output aeb,agtb,altb;
input [3:0] a, b ;
assign aeb=(a==b);
assign agtb=(a>b);
assign altb=(a<b);
endmodule
module compare1 (a, b, aeb,
agb, alb);
input a,b;
output aeb, agb, alb;
assign aeb= (a & b) | (~a & ~b);
assign agb= (a & ~b);
assign alb = (~a & b);
endmodule
Structural Modelling:
module Compare4(a, b, aeb, agb, alb);
input [3:0] a, b;
output aeb, agb, alb;
wire [3:0]e, g, l;
compare1 cp0 (a[0], b[0], e[0], g[0], l[0]);
compare1 cp1 (a[1], b[1], e[1], g[1], l[1]);
compare1 cp2 (a[2], b[2], e[2], g[2], l[2]);
compare1 cp3 (a[3], b[3], e[3], g[3], l[3]);
and(aeb, e[0], e[1], e[2], e[3]);
assign agb= (g[3] | (g[2] & e[3]) | (g[1] &
e[3] & e[2]) | (g[0] & e[3] & e[2] & e[1]));
assign alb = (~agb& ~aeb);
endmodule

105. 1.Acarry look-ahead adderreducesthe propagation delay by introducing
more complex hardware.
2.TheBCDAdderis used in the computers and the calculators that perform
arithmetic operation directly in the decimal number system.
3.In ripple carry adder eachcarrybit gets rippled into the next stage.
4.Full Adderis theadderwhich adds three inputs and produces two
outputs.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

106. CONTENTS:
Functional verification
Simulation types
Design of stimulus block
OUTCOMES:
Student will able to verify the functionality of the digital circuits.
MODULE-X: Verification
MATRUSRI
ENGINEERING COLLEGE

107. Functional Verification
MATRUSRI
ENGINEERING COLLEGE
IdenticalstimulusisrunwiththeoriginalRTLandsynthesizedgate-level
descriptionsofthedesign.Theoutputiscomparedtofindanymismatches.
module stimulus;
reg[3:0] a,b;
wire aeb, alb, agb;
//Instantiate the magnitude comparator
comp4 uut(.a(a),.b(b), .aeb(aeb), .alb(alb), .agb(agb));
initial
$monitor($time," A = %b, B = %b, A_GT_B = %b, A_LT_B = %b, A_EQ_B = %b",
a, b, agb, alb, aeb);
//stimulate the magnitude comparator.
initial
begin
a = 4'b1010; b = 4'b1001;
#10 a = 4'b1110; b = 4'b1111;
#10 a = 4'b1110; b = 4'b1110;
end
endmodule

108. Simulation types
MATRUSRI
ENGINEERING COLLEGE
Simulatorsareusuallydividedintothefollowingcategoriesorsimulation
modes:
•Behavioralsimulation
•Functionalsimulation
•Statictiminganalysis
•Gate-levelsimulation
•Switch-levelsimulation
•Transistor-levelorcircuit-levelsimulation

109. Design of stimulus block
MATRUSRI
ENGINEERING COLLEGE
Test bench －Stimulus Block
Stimulus generation
Output checking
Stimulus Block –I
Instantiate a design under test (dut)
(Design Block)
Ripple Carry Counter
clk reset
(Stimulus Block)
q
Stimulus Block –II
Additional top module instantiating
stimulus and design block
Stimulus
Block
d_clk
d_reset
c_q
Design
Block
clk
reset
q
Top-level Block

110. 1.Amultiplexeris also known as a data selector.
2.AMultiplexers(MUX) is a combinational logic component that has several
inputs and only one output.
3.Decoderis a combinational circuit that has 'n'input lines and maximum of
2^noutput lines.
4.Adecoderis a circuit that changes a code into a set of signals.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

111. CONTENTS:
4 to 1 Multiplexer
2 X 4 Decoder
OUTCOMES:
Student will able to design and test a digital circuits in gatelevel
and dataflow modeling.
MODULE-XI: Additional Topic
MATRUSRI
ENGINEERING COLLEGE

112. 4-to-1 Multiplexer
MATRUSRI
ENGINEERING COLLEGE

113. Gate-level Modeling –4-to-1 Mux
MATRUSRI
ENGINEERING COLLEGE
//module 4-to-1 multiplexer
module mux4_to_1(out, i0, i1, i2, i3, s1, s0);
//port declarations
output out;
input i0, i1, i2, i3, s1, s0;
//internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;
//Gate instantiations
not (s1n, s0);
not s0n, s0); //not gate instantiations
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n); //3-input and gate instantiations
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3); //4-input or gate instantiation
end module

114. Dataflow Modeling –4-to-1 Multiplexer
MATRUSRI
ENGINEERING COLLEGE
Using Logic Equations
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out =(~s1 & ~s0 & i0)|(~s1 & s0 & i1) |(s1 & ~s0 & i2) |(s1 & s0 & i3) ;
endmodule
Using Conditional Operators
module multiplexer4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule

115. Testbench–4-to-1 Mux
MATRUSRI
ENGINEERING COLLEGE
module stimulus;
regIN0, IN1, IN2, IN3;
regS0, S1;
wire OUTPUT;
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
initial
begin
IN0=1; IN1=0; IN2=1; IN3=0;
$display(“IN0=%b, IN1=%b, IN2=%b, IN3=%b\n”, IN0, IN1, IN2, IN3);
S1=0; S0=0;
#1 $display(“S1=%b, S0=%b, OUTPUT=%b\n”, S1, S0, OUTPUT);
S1=0; S0=1;
#1 $display(“S1=%b, S0=%b, OUTPUT=%b\n”, S1, S0, OUTPUT);
S1=1; S0=0;
#1 $display(“S1=%b, S0=%b, OUTPUT=%b\n”, S1, S0, OUTPUT);
S1=1; S0=1;
#1 $display(“S1=%b, S0=%b, OUTPUT=%b\n”, S1, S0, OUTPUT);
end
endmodule
Simulation Results:

116. 2 X 4 Decoder
MATRUSRI
ENGINEERING COLLEGE

117. 2 X 4 Decoder
MATRUSRI
ENGINEERING COLLEGE
Dataflow
module decoder24(A,B,en,Y);
input A, B;
input en;
output [3:0]Y;
assign Y[3] = A& B& en;
assign Y[2] =B& ~A& en;
assign Y[1] = ~B & A& en;
assign Y[0] = ~A& ~B& en;
endmodule
Gate level
module decoder24(A,B,en,Y);
input A, B;
input en;
output [3:0]Y;
wire Ab,Bb;
not (Ab,A);
not(Bb,B)
and (Y[3], A, B, en);
and (Y [2], Ab, B, en);
and (Y [1], A, Bb, en);
and (Y [0], Ab,Bb, en);
endmodule

118. Testbench–2 X 4 Decoder
MATRUSRI
ENGINEERING COLLEGE
module stimulus;
regA,B,en;
wire Y;
decoder24 d(A,B,en,Y);
initial
begin
en=1;
A=0; B=0;
#1 $display (“En=%b, A=%b, B=%b, Y=%b\n”, en,A,B,Y);
A=0; B=1;
#1 $display (“En=%b, A=%b, B=%b, Y=%b\n”, en,A,B,Y);
A=1; B=0;
#1 $display (“En=%b, A=%b, B=%b, Y=%b\n”, en,A,B,Y);
A=1; B=1;
#1 $display(“En=%b, A=%b, B=%b, Y=%b\n”, en,A,B,Y);
end
endmodule

119. 1.Acarry look-ahead adderreducesthe propagation delay by introducing
more complex hardware.
2.AMultiplexers(MUX) is a combinational logic component that has several
inputs and only one output.
3.In ripple carry adder eachcarrybit gets rippled into the next stage.
4.Full Adderis theadderwhich adds three inputs and produces two
outputs.
Questions & Answers
MATRUSRI
ENGINEERING COLLEGE

120. Question Bank
MATRUSRI
ENGINEERING COLLEGE
Short Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcome
1Whatisthedifferencebetweenmoduleinstantiationandgate
instantiation?
L2 CO1
2
Whatisthedifferencebetweennetdatatypeandregisterdatatype?
L2 CO1
3Writeaverilogcodefor1bitFAinstructuralmodel. L1 CO1
4
Whatisthediferencebetween$displayand$monitor?
L2 CO1
5WritetheVerilogprogramfor2bitcomparatoringatemodel? L1 CO1
6WhataretheadvantagesofverilogHDLoverC-programminglanguage? L1 CO1
7Writetheverilogdescriptionforthefullsubtractormodule. L1 CO1
8Whatisatestbench?WhatisitsrelevanceinVerilog? L1 CO1
9Writeaboutcontinuousassignmentstructures. L1 CO1
10Whatarecompilerdirectives?AretheyworksinsimilarinC
programinglanguage.
L1 CO1
11WriteaverilogprogramforthreeinputEXORlogicgateindataflow
modeling.
L1 CO1
12Explainsimulationandsynthesiswithdifferences. L2 CO1

121. Question Bank
MATRUSRI
ENGINEERING COLLEGE
Long Answer Question
S.No Question
Blooms
Taxonomy
Level
Course
Outcom
e
1Draw and explain typical design flow for VLSI IC circuit.L2 CO1
2Describeindetailthetop-downandbottom-updesign
methodologies.
L5 CO1
3Writeaverilogprogramfor16x1multiplexerusing4x1
multiplexer.
L1 CO1
4Write a verilog code for the following function.
F(A,B,C,D)= ∑m((0,3,4,5,11,12,13,15)+d(2,6,8) in gate level
model and write test bench to verify its functionality.
L4 CO1
5
Writeverilogmodulefor8-bitcomparatorwithtestbench.
L1 CO1
6Explain programming language interface. L2 CO1
7Writeaverilogprogramfor4x1Muxindataflowmodeling
usingconditionaloperator.
L1 CO1
8ExplainDelaymodelsindetail. L2 CO1
9Writeshortnotesonfunctionalverification. L1 CO1
10Design&writeVerilogcodeforBCDadderalongwithtest
benchtoverifyitsfunctionality.
L5 CO1

122. Assignment Questions
MATRUSRI
ENGINEERING COLLEGE
1.Explain about different system tasks and complier directives in verilog
with syntax.
2.What are data types which are used in verilog?
3.Write a verilogcode for the following function. F(A,B,C,D)=
∑m(0,5,7,8,9,10,12,13)+ ∑d(1,6,11,14) in gate level model and write test
bench to verify its functionality.
4.Design & write Verilogcode for Ripple carry adder cum subtractoralong
with test bench to verify its functionality.
5.Writeaverilogprogramfor8x1Muxindataflowmodelingusing
conditionaloperatorandverifyitsfunctionality.