Ring 0
Least Privileged
Most Privileged
User Space (U-Mode)
Operating System (S-Mode)
Hypervisor(H-Mode)
Firmware(M-Mode)
RISC-V Privilege Modes
X-86 Protection ring
User Space (EL0)
Operating System
(EL1)
Hypervisor(EL2)
Firmware(EL3)
ARM64 Exception Levels
SBI
•SBI stands for RISC-V Supervisor Binary Interface
•The System call type interface layer between Firmware
runtime, M-Mode to Operating system(S-Mode)
•Avoid fragmentation of various OEM silicon providers
specific runtime firmware implementations
•Standard, generic runtime firmware interface
specification across all OSes, different cpu and silicon
platforms
•Specification in SBI v0.2 in usage
•Documentation available at
–https://github.com/riscv/riscv-sbi-doc
App 1 App 2 App 3
ABI ABI ABI
OS (S-Mode)
Open SBI (M-Mode)
SBI
OpenSBI
•Berkeley Boot Loader(BBL)
•OpenSBI is an open-source implementation of the RISC-
V Supervisor Binary Interface (SBI) specifications
•Aimed at providing RUNTIME services in M-mode
•Provides support for reference platforms
•Platforms supports Andes AE350, Ariane FPGA, Kendryte
K210, Nuclei ux600, SiFive U540, Thead c910, QEMU
•firmware implementations
–FW_PAYLOAD
–FW_JUMP
–FW_DYNAMIC
OpenSBI Calling Convention
•S mode traps into M mode using ecall instructions
•Arguments are passed via registers a0-a5
•a7 encodes the SBI extension ID
•a6 encodes the Function ID
•SBI functions must return a pair of values in a0 & a1
•Unsupported SBI returns -2 (SBI_ENOTSUPP in
Linux)
[arch/riscv/include/asm/sbi.h]
…
#define SBI_SUCCESS 0
#define SBI_ERR_FAILURE -1
#define SBI_ERR_NOT_SUPPORTED -2
...
struct sbiret {
long error;
long value;
};
SBI Call
[arch/riscv/kernel/sbi.c]
struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
unsigned long arg1, unsigned long arg2,…)
{
…
register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
SBI Base Functionality
Function Name Function ID Extension ID
sbi_get_sbi_spec_version 0 0x10
sbi_get_sbi_impl_id 1 0x10
sbi_get_sbi_impl_version 2 0x10
sbi_probe_extension 3 0x10
sbi_get_mvendorid 4 0x10
sbi_get_marchid 5 0x10
sbi_get_mimpid 6 0x10
Vendor-Specific SBI Extension Space, Extension Ids 0x09000000 ~ 0x09FFFFFF
sbi_get_mvendorid = 0x31e
andes’s extension ID = 0x0900031E
RFENCE Extension
Function Name Function ID Extension ID
sbi_remote_fence_i 0 0x52464E43
sbi_remote_sfence_vma 1 0x52464E43
sbi_remote_sfence_vma_asid 2 0x52464E43
sbi_remote_hfence_gvma_vmid 3 0x52464E43
sbi_remote_hfence_gvma 4 0x52464E43
sbi_remote_hfence_vvma_asid 5 0x52464E43
sbi_remote_hfence_vvma 6 0x52464E43
Function Name Function ID Extension ID
sbi_set_timer 0 0x54494D45
Function Name Function ID Extension ID
sbi_send_ipi 0 0x735049
LinuxKernel>=5.7
Function Name Function ID Extension ID
sbi_hart_start 0 0x48534D
sbi_hart_stop 1 0x48534D
sbi_hart_get_status 2 0x48534D
Timer, IPI, Hart State Management
Extension
How to Add a New SBI Call
•Platform-specific: If the platform has an extension ID, you can direct-
contribute to OpenSBI mailing list
•Vendor-Specific SBI Extension Space, Extension Ids 0x09000000 through
0x09FFFFFF
•Step 1. Check Low bits from mvendorid
–e.g. andes’s mvendorid = 0x31e -> 0x0900031E
•Step 2. Add sbi_ext_id to Linux
•Step 3. Add a new enum about platform SBI call’s number to Linux
•Step 4. Add platform’s SBI function call by sbi_ecall()
–e.g. sbi_ecall(Platform’s sbi_ext_id, Platform’s sbi number, 0, 0, 0…);
•Step 5. Add hook function to your platform’s SBI handler
–e.g. .vendor_ext_provider = platform_vendor_ext_provider
Add Extension & Function ID
[arch/riscv/include/asm/sbi.h]
How to add a new SBI call
•non-platform-specific:
–Think about whether it fits into an existing extension or
else create a new extension
–Think about all of the details of the behaviour and
error cases
–Document that in a patch for the SBI document
–Send it to the (Mailing List] (You need to be subscribed
to be able to post) and create a PR on GitHub
–Argue for it
•How to decide Extension ID
–TIME: 0x54, 0x49, 0x4D, 0x45 - by ASCII
How to add a new SBI call
References
•Working experience on RISC-V
•SBI
•OpenSBI
•Atish Patra “RISC-V Boot Process: One step at a time”
•Atish Patra “Fixing the boot process in RISC-V”
•Anup Patel “Xvisor: Embedded Hypervisor for RISC-V”
•Anup Patel “OpenSBI Deep Dive”
•Jagan Teki “An Introduction to RISC-V Boot flow: Overview, Blob vs
Blobfree standards”