itft-Clock generator

1. Clock Generator
8284

2. Clock Generator 8284
•The8284Aisanintegratedcircuitdesigned
specificallyforusewiththe8086/8088micro-
processors.
•Withouttheclockgenerator,manyadditional
circuitsarerequiredtogeneratetheclock(CLK)in
an8086/8088-basedsystem.
•The8284isan18pinintegratedcircuit,designed
specificallyforusewith8086microprocessor.
Thiscircuitprovidesthefollowingbasicfunctionsor
signals
•clockgeneration,
•RESETsynchronization,
•READYsynchronization.
•TTLlevelperipheralclocksignal

3. Pin Diagram

4. Pin Description
•CSYNC:Theclocksynchronizationpinisused
whenevertheEFIinputprovidessynchronizationin
systemswithmultipleprocessors.Iftheinternal
crystaloscillatorisused,thispinmustbeignored.
•PCLK:Theperipheralclocksignalisone-sixththe
crystalorEFIinputfrequency,andhasa50-percent
dutycycle.ThePCKLoutputprovidesaclocksignal;
totheperipheralequipmentinthesystem.

5. •AEN1&AEN2:Theaddressenablepinsare
providedtoqualifythebusreadysignal,RDY1&
RDY2.Thesetwopinsareusedtocausewait
state,alongwithRDY1&RDY2inputs.
•WaitstatearegeneratedbytheREADYpinofthe
8086microprocessorwhichiscontrolledbythese
twopins.
•RDY1&RDY2:Thebusreadyinputsareprovided,
inconjuctionwiththeAEN1&AEN2pins,tocause
waitstatein8086basedsystem.

6. •READY: READY is an output pin that connects to the
8086/8088 READY input.
•This signal is synchronized with the RDY1 and RDY2
Inputs.
•CLK:ProvidesCLKinputsignaltothe8086/8088
microprocessorsandothercomponentsinthe
system.
•GND: Connects to ground.
•Vcc: Connects to +5.0V with a tolerance of +10
percent.

7. •RESET:TheRESEToutputconnectstothe
8086/8088RESETinputpin.
•RES(Resetinput):Activelowinput.Oftenconnects
toanRCnetworkthatprovidespower-on-
resetting.
•OSC(Oscillator):TTLlevelsignaloutput.Provides
anEFIinputtoother8284Aclockgeneratorsin
somemultipleprocessorsystems.

8. •F/C(Frequency/Crystalselect):Itchoosesthe
clockingsourceforthe8284A.
•F/C=1(high),anexternalclockisprovidedtothe
EFIinputpin.
•F/C=0(low),anexternalcrystaloscillator
connectedtoX1andX2providestheclock.
•EFI(ExternalFrequencyInput):ItisusedwhenF/C
pinissettohigh.
•ItSuppliesthetimingwhenevertheF/Cishigh.

9. ASYNC(Readysynchronization)
•Thereadysynchronizationselectioninputselects
eitheroneortwostagesofsynchronizationforthe
RDY1andRDY2inputs.
X1nadX2(Crystalinputs)
•Anexternalcrystaloscillatorisconnectedtothese
inputs.
•Itisusedasthetimingsourcefortheclock
generatorandallitsfunctions.

10. internal block diagram of 8284A clock generator
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11. Operation of Clock Section
•F/C’ = 0 : internal crystal oscillator
•crystal is attached X1, X2, oscillator generate square-
wave signal at the same frequency as crystal
•square-wave signal : fed to AND gate, inverter(OSC)
•OSC output : sometimes used as EFI to other 8284A
•AND gate : select oscillator or EFI
•F/C’=0 : oscillator output → divide-by-3 counter
•F/C’=1 : EFI → divide-by-3 counter
•output of divide-by-3 counter
•timing for ready synchronization
•signal for another divide-by-2 counter : PCLK
•CLK signal : buffered before CLK output pin
Ch.9 8086/8088 Hardware Specifications 11

12. Operation of the Reset Section
•Fig. 9-4 : crystal oscillator(F/C’=CSYNC=0)
•15MHz crystal : 5MHz clock signal, 2.5MHz
PCLK
•Reset : a Schmitt trigger buffer, a D-type FF
•D FF : ensured timing requirements of 8086
RESET
•applied RESET signal to µ on negative edge of each
clock
•8086 µ : sampled RESET at positive edge of clocks
•1. power on reset, 2. reset button
•µ RESET :
•to become logic 1 no later than 4 clocks after power
is applied, (FF make certain that RESET goes high
in4 clock) and to be held high for at least 50 ㎲(RC
time constant)
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