its so difficult to find real name if you understand this slide you do someting

okey best of luck

1. Dr. Hesham A. Omran
The gm/ID Design Methodology Demystified
www.master-micro.com

2. www.master-micro.com
The Problem
❑Since the release of Berkeley SPICE simulator in the 1970s…
▪No major change in the analog design flow!
❑Nanometer transistor models are very complex
▪Time-consuming multi-variable sweeps on simulation tools…
❑There is no systematic analog design process!
The gm/ID Design Methodology Demystified 2
Growing chip
complexity
Time-to-market
Designer’s
productivity

3. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
The gm/ID Design Methodology Demystified 3

4. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
The gm/ID Design Methodology Demystified 4

5. www.master-micro.com
Why is the Transistor Different?
❑We are used to two-terminal devices
▪Resistors, capacitors, inductors, diodes
❑The transistor is a three-terminal device
▪The voltage between two terminals controls the current flowing
into the third terminal
•�
����controls ??????
���
▪Voltage controlled current source (VCCS)
❑This feature enabled a multitude of applications that changed our
life!
▪Analog signal amplification and processing
▪Digital logic and memory circuits
The gm/ID Design Methodology Demystified 5Transistor
Iout = f(Vctrl)
Vctrl

6. www.master-micro.com
The Transistor Large Signal Model: Non-linear VCCS
The gm/ID Design Methodology Demystified 6Vctrl
Iout Transistor
Iout = f(Vctrl)
Vctrl Vctrl ro
Iout = f(Vctrl)

7. www.master-micro.com
The Small Signal Approximation: Linear VCCS
The Transconductance
�
�=
??????�
���
??????�
??????�??????�
=
�
���
�
??????�??????�
The gm/ID Design Methodology Demystified 7Vctrl
Iout Transistor
iout = gmvctrl
vctrl vctrl ro
iout = gmvctrl

8. www.master-micro.com
The Output Resistance: Early Voltage (�
�)
The gm/ID Design Methodology Demystified 8Vctrl ro
Iout = f(Vctrl) Vout Transistor
Iout = f(Vctrl)
Vctrl
Vout Vout
Iout,total
VA
The Output Resistance
??????
�=
�
�
���
=
??????�
���
??????�
���
−�
≈
�
�
�
??????

9. www.master-micro.com
The Transistor Intrinsic Gain
??????
���=−�
�??????
����×??????
�=−�
�??????
??????�×??????
�
The gm/ID Design Methodology Demystified 9vin vout
Vp
(gmro)Vp
vctrl
ro
iout = gmvctrl
|�
�|=
�
���
�
��
=�
�??????
�=
�
�
�
??????
⋅�
�

10. www.master-micro.com
�
�Controls the Speed
�
�=
??????
���
??????
??????�
=�
�??????
�
??????=??????
��
??????
��=
�
�
2??????
=
1
2????????????
=
1
2????????????
��
??????
The gm/ID Design Methodology Demystified 10vin vout
vctrl
ro
iout = gmvctrl
CL
���=|�
�|⋅��=�
�=
�
�
�??????�
??????

11. www.master-micro.com
�
�Controls the Noise
❑We can show that for both MOSFET thermal noise and BJT shot noise
The gm/ID Design Methodology Demystified 11vin vout
vctrl
ro
iout = gmvctrl
�
�,��
�
�∝
�
�
�

12. www.master-micro.com
We Must Pay �
??????to Buy �
�
The gm/ID Design Methodology Demystified 12Vctrl
Iout
The
Transistor
�
?????? �
�
The Transistor Efficiency
��=
��??????�??????���??????��
��??????�??????���????????????
=
�
�
�
??????

13. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
The gm/ID Design Methodology Demystified 13

14. www.master-micro.com
The BJT
??????
�=??????
��
??????????????????
??????�
�
�=
�??????
�
��
��
=
??????
�
�
�
�
�
??????
�
=
1
�
�
≈
1
26��
=38.5�/�
The gm/ID Design Methodology Demystified 14

15. www.master-micro.com
TE Visualized: Method #1
??????
�=??????
��
??????????????????
??????�
�
�=
�??????
�
��
��
=
??????
�
�
�
�
�
??????
�
=
1
�
�
≈
1
26��
=38.5�/�
The gm/ID Design Methodology Demystified 15

16. www.master-micro.com
TE Visualized: Method #2
log
�(�)=ln10log
10�≈2.3log
10�
�log
�(�)
��
=
��/��
�
�log
10�
��
≈
1
2.3
��/��
�
The gm/ID Design Methodology Demystified 16
�log
�??????
�
��
��
=
�??????
�/��
��
??????
�
=
�
�
??????
�
�log
10??????
�
��
��
≈
1
2.3
�
�
??????
�
∝
�
�
??????
�
TE ∝Slope of �
�on log scale
�
�
??????
�
∝
�log
�??????
�
��
��

17. www.master-micro.com
TE Visualized: Method #2
❑Slope = constant!
❑There is no gm/IC design methodology ☺!
The gm/ID Design Methodology Demystified 17
TE ∝Slope of �
�on log scale
�
�
??????
�
∝
�log
�??????
�
��
��
�
�
??????
�
=
1
�
�
≈
1
26��
=38.5�/�

18. www.master-micro.com
The Digital Perspective
�
�
??????
�
=
1
�
�
≈
1
26��
=38.5�/�
❑How much change in VBE for 10x change in IC
�=
�log
10??????
�
��
��
−1
=
1
2.3
�
�
??????
�
−1
≈2.3�
�≈60��/���??????��
The gm/ID Design Methodology Demystified 18

19. www.master-micro.com
BJT Intrinsic Gain
The gm/ID Design Methodology Demystified 19
??????
���=−�
�??????
����×??????
�=−�
�??????
??????�×??????
�
|�
�|=
??????
���
??????
??????�
=�
�??????
�=�
�⋅
�
�
??????
�
=
�
�
??????
�
⋅�
�vin vout
Vp
(gmro)Vp
vctrl
ro
iout = gmvctrl
|�
�|=
�
�
�
�

20. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
The gm/ID Design Methodology Demystified 20

21. www.master-micro.com
The Old-School MOSFET
❑N-type channel region (inversion layer) formed at
�
��>�
��
�
��=�
��+�
��
▪Threshold voltage: �
��~0.3�−1�
❑The channel is pinched off if
�
��≤�
��⟺�
��≥�
��
❑The simple long channel model (Square-law)
??????
�=
�
��
�??????
2
�
�
�
��−�
��
2
=
�
��
�??????
2
�
�
�
��
2
The gm/ID Design Methodology Demystified 21 n+n+
G
S D
p-sub
VGS > VTH VGD < VTH
VDS > Vov

22. www.master-micro.com
MOSFET IV Characteristics
❑The square law
??????
&#3627408439;=
&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
2
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408442;&#3627408454;−&#3627408457;
&#3627408455;&#3627408443;
2
=
&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
2
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408476;&#3627408483;
2
&#3627408468;
&#3627408474;=
&#3627409173;??????
&#3627408439;
&#3627409173;&#3627408457;
&#3627408442;&#3627408454;
=&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408442;&#3627408454;−&#3627408457;
&#3627408455;&#3627408443;
=&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408476;&#3627408483;
The gm/ID Design Methodology Demystified 22

23. www.master-micro.com
Short Channel MOSFET
❑Short channel effects
▪Velocity saturation
•ID has linear dependence on VGS
•ID has no (or weak) dependence on L
▪Mobility degradation
❑Linear rather than quadratic characteristics
▪&#3627408468;
&#3627408474;saturates at large &#3627408457;
&#3627408476;&#3627408483;
❑The square law fails to describe strong-
inversion (SI) accurately
The gm/ID Design Methodology Demystified 23

24. www.master-micro.com
MOSFET gm/ID
❑The square law
??????
&#3627408439;=
&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
2
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408442;&#3627408454;−&#3627408457;
&#3627408455;&#3627408443;
2
=
&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
2
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408476;&#3627408483;
2
&#3627408468;
&#3627408474;=
&#3627409173;??????
&#3627408439;
&#3627409173;&#3627408457;
&#3627408442;&#3627408454;
=&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408442;&#3627408454;−&#3627408457;
&#3627408455;&#3627408443;
=&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
&#3627408458;
&#3627408447;
&#3627408457;
&#3627408476;&#3627408483;
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
2
&#3627408457;
&#3627408442;&#3627408454;−&#3627408457;
&#3627408455;&#3627408443;
=
2
&#3627408457;
&#3627408476;&#3627408483;
The gm/ID Design Methodology Demystified 24

25. www.master-micro.com
MOSFET gm/ID
❑The square law
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
2
&#3627408457;
&#3627408442;&#3627408454;−&#3627408457;
&#3627408455;&#3627408443;
=
2
&#3627408457;
&#3627408476;&#3627408483;
❑The square law fails to describe weak-
inversion (WI) completely
❑MOSFET gm/ID depends on bias point!
▪Large in weak-inversion (WI)
▪Small in strong-inversion (SI)
❑Tuning MOSFET gm/ID (the TE) is the core
of the gm/ID design methodology
The gm/ID Design Methodology Demystified 25

26. www.master-micro.com
Square-Law End-of-Life?
❑However, …
▪For analog we use relatively long L and relatively low &#3627408457;
&#3627408476;&#3627408483;
•Short channel effects (e.g., velocity sat.) are less pronounced
▪Simple model provides a great deal of intuition that is necessary in analog design
❑You may use it to “partially” understand trends, BUT NOT to calculate sizing!
The gm/ID Design Methodology Demystified 26
The Square-Law
Weak Inversion (WI)
The square-law fails completely
Strong Inversion (SI)
The square-law is not accurate due
to short channel effects

27. www.master-micro.com
WI Revisited
❑The square law
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
2
&#3627408457;
&#3627408442;&#3627408454;−&#3627408457;
&#3627408455;&#3627408443;
=
2
&#3627408457;
&#3627408476;&#3627408483;
❑The square law fails to describe weak-
inversion (WI) completely
❑So, what happens in subthreshold?
▪Since gm/ID saturates, we expect ID
characteristics is …..
The gm/ID Design Methodology Demystified 27

28. www.master-micro.com
MOSFET in Subthreshold
❑gm/ID saturates
❑log(ID) vs VGS must be straight line
(constant slope)!
❑ID depends exponentially on VGS
❑Similar to BJT behavior?!
The gm/ID Design Methodology Demystified 28

29. www.master-micro.com
Subthreshold Operation (Weak Inversion)
❑MOSFET behaves as a BJT (npnfor an NMOS)
with its base coupled to the gate through
capacitive divider
&#3627408457;
&#3627408437;&#3627408440;=&#3627408457;
&#3627408442;&#3627408454;
&#3627408438;
&#3627408476;??????
&#3627408438;
&#3627408476;??????+&#3627408438;
&#3627408465;&#3627408466;&#3627408477;
=
&#3627408457;
&#3627408442;&#3627408454;
&#3627408475;
&#3627408475;=
&#3627408438;
&#3627408476;??????+&#3627408438;
&#3627408465;&#3627408466;&#3627408477;
&#3627408438;
&#3627408476;??????
>1
??????
&#3627408439;≈??????
&#3627408476;&#3627408467;&#3627408467;&#3627408466;
??????????????????
??????&#3627408455;=??????
&#3627408476;&#3627408467;&#3627408467;&#3627408466;
????????????&#3627408454;
&#3627408475;??????&#3627408455;
❑For bulk MOSFET: &#3627408475;≈1.2→1.5
❑For SOI and FinFET: &#3627408475;≈1.1
The gm/ID Design Methodology Demystified 29S
G
D
B
Cox
Cdep n+n+
G
S D
p-sub
VGS < VTH

30. www.master-micro.com
gm/ID in Weak Inversion (WI)
??????
&#3627408439;≈??????
&#3627408476;&#3627408467;&#3627408467;&#3627408466;
????????????&#3627408454;
&#3627408475;??????&#3627408455;
&#3627408468;
&#3627408474;=
&#3627409173;??????
&#3627408439;
&#3627409173;&#3627408457;
&#3627408442;&#3627408454;
=
??????
&#3627408439;
&#3627408475;&#3627408457;
&#3627408455;
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
1
&#3627408475;&#3627408457;
&#3627408455;
≈
38.5
&#3627408475;
❑&#3627408475;≈1.1→1.5
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
1
&#3627408475;&#3627408457;
&#3627408455;
≈25→35&#3627408454;/&#3627408436;
The gm/ID Design Methodology Demystified 30

31. www.master-micro.com
The Digital Perspective: The Subthreshold Slope &#3627408506;
❑&#3627408475;≈1.1→1.5
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
1
&#3627408475;&#3627408457;
&#3627408455;
≈25→35&#3627408454;/&#3627408436;
❑Change in VGS for 10x change in ID
&#3627408454;=
&#3627409173;log
10??????
&#3627408439;
&#3627409173;&#3627408457;
&#3627408442;&#3627408454;
−1
=
1
2.3
&#3627408468;
&#3627408474;
??????
&#3627408439;
−1
≈2.3&#3627408475;&#3627408457;
&#3627408455;≈66→90&#3627408474;&#3627408457;/&#3627408465;&#3627408466;&#3627408464;??????&#3627408465;&#3627408466;
The gm/ID Design Methodology Demystified 31

32. www.master-micro.com
MOSFET Intrinsic Gain
|&#3627408436;
&#3627408483;|=&#3627408468;
&#3627408474;??????
&#3627408476;=&#3627408468;
&#3627408474;⋅
&#3627408457;
&#3627408436;
??????
&#3627408439;
=
&#3627408468;
&#3627408474;
??????
&#3627408439;
⋅&#3627408457;
&#3627408436;
❑Longer L gives higher &#3627408457;
&#3627408436;
❑Square-law prediction
|&#3627408436;
&#3627408483;|=
&#3627408468;
&#3627408474;
??????
&#3627408439;
⋅&#3627408457;
&#3627408436;=
2&#3627408457;
&#3627408436;
&#3627408457;
&#3627408476;&#3627408483;
▪Trend is OK
▪But poor-fit even for long L!
❑Subthreshold-model prediction
|&#3627408436;
&#3627408483;|=
&#3627408468;
&#3627408474;
??????
&#3627408439;
⋅&#3627408457;
&#3627408436;=
&#3627408457;
&#3627408436;
&#3627408475;&#3627408457;
&#3627408455;
The gm/ID Design Methodology Demystified 32

33. www.master-micro.com
Operation in Weak Inversion (WI)
❑You get high gm/ID and high gm/gds
❑But current is exponentially decreasing
▪gm is exponentially decreasing
▪Speed is exponentially decreasing
❑Why not keep the same ID and gm?
▪You need exponentially increasing W
▪Exponentially increasing area and parasitics
The gm/ID Design Methodology Demystified 33

34. www.master-micro.com
Operation in Moderate Inversion (MI)
❑Operation is MI is becoming increasingly popular
❑We can reap WI benefits
▪High gm/ID and high gm/gds
❑Some degradation in speed is OK
▪Short channel MOSFETs are already very fast
❑But no simple model exists…
The gm/ID Design Methodology Demystified 34

35. www.master-micro.com
Why Do We Need the Models?
❑Models are necessary to “roughly” understand trends
❑Models are necessary to help designer’s intuition
❑Simple models help intuition, but are not accurate
❑Accurate models provides NO intuition and are intractable
❑But do we really need an accurate model?
▪We can calculate sizing using charts or lookup tables (LUTs)
The gm/ID Design Methodology Demystified 35

36. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
The gm/ID Design Methodology Demystified 36

37. www.master-micro.com
The Design Problem
❑MOSFET is a function of five variables
❑Three voltages
▪VGS
▪VDS
▪VSB
❑Two sizing parameters
▪L
▪W
The gm/ID Design Methodology Demystified 37VGS
VSB
VDS
W
L

38. www.master-micro.com
VSB
❑VSB causes body effect
▪Increasing VSB increases VTH
❑For devices in a dedicated well the body can be
tied to the source
▪But extra area, extra well capacitance, coupling
between S and D, and maybe extra noise
❑Usually, VSB is not a designer degree-of-freedom
(DOF)
▪It is imposed by the circuit topology
The gm/ID Design Methodology Demystified 38VP
M1M2
M3 M4
Vout
Vin1 Vin2
IB

39. www.master-micro.com
VDS
❑Ideally, VDS should not affect ID
▪MOSFET is a VCCS for VDS > VDsat
❑But practically, increasing VDS increases ID
▪CLM and DIBL
❑VDS effect modeled by ??????
&#3627408476;=&#3627408457;
&#3627408436;/??????
&#3627408439;=1/&#3627409158;??????
&#3627408439;
❑&#3627408457;
&#3627408436;increases as we increase VDS
▪??????
&#3627408476;increases as we go deeper into saturation
❑&#3627408457;
&#3627408436;increases as we increase L
▪But need VDS = VDsat+ margin to notice the
difference
❑But what is VDsat?
The gm/ID Design Methodology Demystified 39

40. www.master-micro.com
VDsat
❑The definition of VDsatis a bit vague
▪ID keeps increasing due to CLM/DIBL
▪At edge of saturation (VDS = VDsat) ??????
&#3627408476;is
quite low
❑For a square-law device VDsat= Vov
❑In simulation models VDsatis a bit complex
parameter
▪And again, it is vague and not really
meaningful
The gm/ID Design Methodology Demystified 40

41. www.master-micro.com
VDsatand V*
❑For the square-law
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
2
&#3627408457;
&#3627408476;&#3627408483;
→&#3627408457;
&#3627408476;&#3627408483;=
2
&#3627408468;
&#3627408474;/??????
&#3627408439;
❑We define a new parameter inspired by Vov
&#3627408457;
∗
=
2
&#3627408468;
&#3627408474;/??????
&#3627408439;
❑V* is computed from simulation data
▪It is valid in all regions (WI, MI, and SI)
❑V* is always larger than VDsat
▪It can be used as an estimate for saturation
▪It guarantees biasing a little deeper into
saturation
The gm/ID Design Methodology Demystified 41

42. www.master-micro.com
VDS
❑VDS is set to V* + VDsat_margin
❑It is desirable to make the margin large
▪But this will come at the expense of
headroom, swing, input range, etc.
❑Low supply makes the problem more difficult
The gm/ID Design Methodology Demystified 42 IREF Vout
Iout
M1 M2
M3M4
VB

43. www.master-micro.com
VGS
❑VGS is the primary voltage controlling the
device behavior
❑VGS is tightly coupled to ID
▪MOSFET is a VCCS
❑In analog ICs, we usually set the bias current
(ID) rather than setting the bias voltage (VGS)
▪Current mirror biasing
❑Replace VGS by ID in the DOFs list
The gm/ID Design Methodology Demystified 43VP
M1M2
M3 M4
Vout
Vin1 Vin2
IB

44. www.master-micro.com
L
❑Shorter L allows smaller area and higher speed
❑But analog designers usually tend to use relatively long L
The gm/ID Design Methodology Demystified 44
Use shorter L if you want Use longer L if you want
➢Smaller area
➢Smaller capacitance
➢High speed(high &#3627408467;
&#3627408455;=
&#3627408468;
??????
2??????&#3627408438;
????????????
)
➢High gain(high &#3627408457;
&#3627408436;)
▪Must have large VDsat_marginto be
effective (beware of exceptions due to
feedback)
➢Less random mismatch
▪Longer L implies larger area (beware of
exceptions due to non-uniform doping
profile)
➢Low flicker noise
▪Longer L implies larger area

45. www.master-micro.com
Longer L: Beware of Exceptions
❑What really matters is the DC loop gain, not the OTA open-loop gain
&#3627408447;??????=&#3627409149;&#3627408436;
????????????=
&#3627408438;
&#3627408441;
&#3627408438;
&#3627408441;+&#3627408438;
&#3627408454;+&#3627408438;
??????&#3627408475;
&#3627408436;
????????????
❑Increasing L of input pair may increase &#3627408436;
????????????but will give an overall reduction of LG
The gm/ID Design Methodology Demystified 45CF
CS
CS
CL
CF
Vsig
+
Vout
CL
_
+
_
Vin
+
_ M1M2 Vin-Vin+

46. www.master-micro.com
W
❑Choosing W is one of the most difficult tasks
❑The choice of W is affected by
▪How much gm/ID do you want (inversion level: WI, MI, SI)?
▪How much L do you use?
▪How much ID do you force?
❑The search-range of W can range from sub-1um to 1000um
(laid-out as multi-fingers)
▪The meaningful search range depends on gm/ID (inversion
level), L, and ID
❑Assume you selected a specific W
▪Changing L changes the gm/ID (the TE)
▪Changing ID changes the gm/ID (the TE)
The gm/ID Design Methodology Demystified 46M1M2 Vin-Vin+

47. www.master-micro.com
The Old Fix: Vov
❑To solve this problem, designers used to replace W by Vovin the DOFs
❑Vovused to give an indication for the TE (how much inversion do we have)
❑Given ID, L, and Vov: They used to use the square law to calculate W
??????
&#3627408439;=
&#3627409159;
&#3627408475;&#3627408438;
&#3627408476;??????
2
&#3627408510;
&#3627408447;
&#3627408457;
&#3627408476;&#3627408483;
2
❑This fix doesn’t work any more
▪The square law and Vovare not accurate in SI
▪They are completely invalid in MI and WI
▪They are not related to circuit specs anymore
•No direct relation to gain, speed, and noise
The gm/ID Design Methodology Demystified 47M1M2 Vin-Vin+

48. www.master-micro.com
The New Fix: The gm/ID Design Methodology
❑What we care most about is the gm/ID, i.e., the Transistor Efficiency (TE)
▪The gm/ID captures the relation between the basic function of the transistor (the
transconductance) and the most valuable resource (the power consumption)
❑Replace W by gm/ID in the DOFs
❑“Orthogonal” control of TE!
❑Think gm/ID!
The gm/ID Design Methodology Demystified 48

49. www.master-micro.com
Think gm/ID!
❑The gm/ID is an “orthogonal” DOF to control the TE (and consequently the inversion
level: WI, MI, SI)
▪When ID and/or L change: gm/ID (the TE) is kept unchanged
▪We simply lookup the new W that guarantees this
❑The gm/ID is directly related to circuit specs
▪It defines gain, speed, and noise
❑The search-range of gm/ID is limited
▪Typically: 5 to 25
▪The range of gm/ID values doesn’t differ much
•From one device to another
•And from one technology to another
The gm/ID Design Methodology Demystified 49

50. www.master-micro.com
Think gm/ID!
The gm/ID Design Methodology Demystified 50
Use small gm/ID if you wantUse large gm/ID if you want
➢Strong-inversion (SI) biasing
➢Small gm (for a given ID)
▪Devices whose gm do
NOT contribute to gain
(Ex: active loads)
➢Small area
➢Small capacitance
➢High speed
➢Large &#3627408457;
&#3627408436;(large ro)
▪The gate has better
control on channel (VDS
effect is less)
➢Moderate inversion (MI) or weak-inversion (WI)biasing
➢Large gm (for a given ID)
▪Devices whose gm do contribute to gain (Ex: input stage and
cascode devices)
➢High efficiency
▪Low power consumption (low ID) for a given speed or noise
spec (gm spec)
➢Less random mismatch
▪Large gm/ID implies larger W (larger area) (beware of
exceptions due to non-uniform doping profile)
➢Low flicker noise
▪Large gm/ID implies larger W (larger area)
➢Large input rangeand/or output swing
▪Large gm/ID implies small V*

51. www.master-micro.com
Think gm/ID!
The gm/ID Design Methodology Demystified 51
Use small gm/ID if you wantUse large gm/ID if you want
➢Strong-inversion (SI) biasing
➢Small gm (for a given ID)
▪Devices whose gm do
NOT contribute to gain
(Ex: active loads)
➢Small area
➢Small capacitance
➢High speed
➢Large &#3627408457;
&#3627408436;(large ro)
▪The gate has better
control on channel (VDS
effect is less)
➢Moderate inversion (MI) or weak-inversion (WI)biasing
➢Large gm (for a given ID)
▪Devices whose gm do contribute to gain (Ex: input stage and
cascode devices)
➢High efficiency
▪Low power consumption (low ID) for a given speed or noise
spec (gm spec)
➢Less random mismatch
▪Large gm/ID implies larger W (larger area) (beware of
exceptions due to non-uniform doping profile)
➢Low flicker noise
▪Large gm/ID implies larger W (larger area)
➢Large input rangeand/or output swing
▪Large gm/ID implies small V*
The best compromise is usually in MI
&#3627408520;
&#3627408526;
&#3627408496;
&#3627408491;
≈&#3627409359;&#3627409358;→&#3627409360;&#3627409358;

52. www.master-micro.com
gm/ID and Gain
&#3627408468;
&#3627408474;??????
&#3627408476;=
&#3627408468;
&#3627408474;
??????
&#3627408439;
⋅&#3627408457;
&#3627408436;
❑For high intrinsic gain go for high gm/ID
❑But beware that &#3627408457;
&#3627408436;(and consequently ??????
&#3627408476;) decreases as you go in WI
▪The gate has less control in WI
▪The effect of VDS on ID increases
The gm/ID Design Methodology Demystified 52

53. www.master-micro.com
gm/ID and Gain
|&#3627408436;
&#3627408483;|=&#3627408468;
&#3627408474;1??????
&#3627408476;1||??????
&#3627408476;2=
&#3627408468;
&#3627408474;1
&#3627408468;
&#3627408465;&#3627408480;1+&#3627408468;
&#3627408465;&#3627408480;2
=
&#3627408468;
&#3627408474;/??????
&#3627408439;1
1
&#3627408457;
&#3627408436;1
+
1
&#3627408457;
&#3627408436;2
❑From gain perspective
▪A large gm/ID may be good for M1
▪But a small gm/ID is better for M2 (higher &#3627408457;
&#3627408436;2)
❑Generally, from gain perspective
▪Use large gm/ID for transistors whose &#3627408468;
&#3627408474;contribute to the gain
•Ex: input stage and cascode devices
▪Use small gm/ID for transistors whose &#3627408468;
&#3627408474;do not contribute to gain
•Ex: active loads
The gm/ID Design Methodology Demystified 53vin
vout
M2
VB
M1

54. www.master-micro.com
gm/ID and Thermal Noise
??????
&#3627408475;,??????&#3627408475;
2
&#3627408467;≈
4??????&#3627408455;&#3627409150;
&#3627408468;
&#3627408474;1
1+
&#3627408468;
&#3627408474;2
&#3627408468;
&#3627408474;1
❑From noise perspective
▪A large gm/ID is good for M1
▪But a small gm/ID is better for M2 (higher &#3627408457;
&#3627408436;2)
❑Generally, from noise perspective
▪Use large gm/ID for transistors whose &#3627408468;
&#3627408474;contribute to gain
•Ex: input stage and cascode devices
▪Use small gm/Id for transistors whose &#3627408468;
&#3627408474;do not contribute to gain
•Ex: active loads
The gm/ID Design Methodology Demystified 54vin
vout
M2
VB
M1

55. www.master-micro.com
From gm/ID to W
❑The problem is that you cannot plugin gm/ID in the
simulator
▪Side note: you can directly plugin gm/ID in the
Analog Designer’s Toolbox (ADT) ☺
❑The good news is that ID is always proportional to
W:??????
&#3627408439;∝&#3627408458;
▪This holds for both long and short channel
devices
The gm/ID Design Methodology Demystified 55
▪This holds for all operating regions (WI, MI, SI)
▪Simply, the wider the street (the channel) the more cars (electrons) can pass
❑The exception is narrow-width devices
▪But they are seldom used in analog as they will have excessive mismatch and excessive
flicker noise

56. www.master-micro.com
From gm/ID to W
❑Assume a reference device with Width = W
❑For a given L, there is one-to-one
correspondence between VGS and ID
❑And there is one-to-one correspondence
between gm/ID and VGS
▪Points to the left of the max gm/ID are
discarded
❑Thus, there is one-to-one correspondence
between gm/ID and ID
❑Similarly, we can plot any other parameter vs
gm/ID
The gm/ID Design Methodology Demystified 56

57. www.master-micro.com
From gm/ID to W
??????
&#3627408439;∝&#3627408458;
❑Apply cross multiplication
The gm/ID Design Methodology Demystified 57
Ref Device ID
(from chart or
look-up table)
W
(reference
device width)
Design ProblemIDx
(defined in
problem DOFs)
Wx= ?
&#3627408458;
??????=&#3627408458;×
??????
&#3627408439;??????
??????
&#3627408439;

58. www.master-micro.com
Recapping MOSFET DOFs
The gm/ID Design Methodology Demystified 58
OriginalThe Old-School The gm/ID Methodology
W Vov
(square law)
gm/ID
(use charts or LUTs to get W)
L L
(get aroughestimate for&#3627408457;
&#3627408436;=1/&#3627409158;)
L
(use charts or LUTs)
VGS ID
(current mirror biasing)
ID
(current mirror biasing)
VDS VDS = Vov+ VDsat_margin
(get aroughestimate forVDsat_margin)
VDS = VDsat+ VDsat_margin
(taken into account by using charts or LUTs)
VSB Forced by topology
(use simple model or ignore)
Forced by topology
(taken into account by using charts or LUTs)

59. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
The gm/ID Design Methodology Demystified 59

60. www.master-micro.com
Implications of &#3627408496;
&#3627408491;∝&#3627408510;
❑Almost all MOSFET parameters are also proportional to W (given other DOFs are constant)
▪gm, gds, gmb
▪cgs, cgd, cgb, csb, cdb
▪Also drain-current thermal noise density (STH) and flicker noise density (SFL)!
❑Result #1: Store these parameters for the reference device
▪Calculate the parameters of any other device by cross-multiplication!
❑Result #2: Ratios of these parameters are width independent!
&#3627408468;
&#3627408474;
??????
&#3627408439;
,&#3627408467;
&#3627408455;=
&#3627408468;
&#3627408474;
2??????&#3627408438;
&#3627408468;&#3627408468;
,
&#3627408468;
&#3627408474;
&#3627408458;
,&#3627408468;
&#3627408474;??????
&#3627408476;=
&#3627408468;
&#3627408474;
&#3627408468;
&#3627408465;&#3627408480;
,&#3627408457;
&#3627408436;=
??????
&#3627408439;
&#3627408468;
&#3627408465;&#3627408480;
,…
The gm/ID Design Methodology Demystified 60
Ref Device ID W gm …
Design ProblemIDx Wx gmx …

61. www.master-micro.com
Building The Design Charts
❑MOSFET is a function of five variables
❑Three voltages
▪VGS: Sweep (primary variable)
▪VDS: Set to fixed value
▪VSB: Set to fixed value
❑Two sizing parameters
▪L: Step (secondary variable)
▪W: Set to a reference value (e.g., 10um)
❑Run DC and noise sweeps and store large
signal and small signal parameters in 2D arrays
❑Plot in parametric charts
▪X-axis is VGS or gm/ID (or any ratio)
▪L is a parameter
The gm/ID Design Methodology Demystified 61VGS
VSB
VDS
W
L

62. www.master-micro.com
Building The Lookup Table (LUT)
❑MOSFET is a function of five variables
❑Three voltages: VGS,
▪VGS: Sweep (primary variable)
▪VDS: Step (parametric sweep)
▪VSB: Step (parametric sweep)
❑Two sizing parameters
▪L: Sweep (secondary variable)
▪W: Set to a reference value (e.g., 10um)
❑Run DC and noise sweeps and store large and small
signal parameters in 4D arrays
▪4D LUT for every parameter
The gm/ID Design Methodology Demystified 62ID gm
gds gmb
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
L VGS
VSB
VDS
W
L

63. www.master-micro.com
Extracting Design Charts
❑4D LUT for every parameter
❑Select specific VDS and VSB to plot 2D parametric
charts
❑Ex: gm/gdsvs VGS @ VSB = 0 V and VDS = 0.9 V
The gm/ID Design Methodology Demystified 63ID gm
gds gmb
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
L VGS
VSB
VDS
W
L

64. www.master-micro.com
Extracting Design Charts
❑4D LUT for every parameter
❑Select specific VDS and VSB to plot 2D parametric
charts
❑Ex: gm/gdsvs VGS @ VSB = 0 V and VDS = 0.9 V
▪Repeat at several values of L
The gm/ID Design Methodology Demystified 64ID gm
gds gmb
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
L VGS
VSB
VDS
W
L

65. www.master-micro.comThe gm/ID Design Methodology Demystified 65
Building the LUTs

66. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
▪Design Example #1
▪Design Example #2
The gm/ID Design Methodology Demystified 66

67. www.master-micro.com
Design Example #1
The gm/ID Design Methodology Demystified 67
❑Four DOFs (four unknowns): IB, gm/ID, L, VDS
❑Only two equations (DC gain and GBW)
❑We need to assume two DOFs
▪Assume VDS = VDD/2
▪Assume a reasonable IB (if not given as a spec)
❑How to get a reasonable estimate for current?
❑How to know if a current spec makes sense?
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB ?
gm/ID ?
L ?vin
vout
CL
IB

68. www.master-micro.com
Think gm/ID!
The gm/ID Design Methodology Demystified 68
❑How to get a reasonable estimate for current?
❑How to know if a current spec makes sense?
❑Remember:
▪&#3627408468;
&#3627408474;controls speed
▪We pay current to buy &#3627408468;
&#3627408474;
❑Start by getting an estimate for &#3627408468;
&#3627408474;
▪gm/ID has a well-known reasonable range
▪You can now get the reasonable current range
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB ?
gm/ID ?
L ?vin
vout
CL
IB

69. www.master-micro.com
gm Spec and Current Range
??????&#3627408437;&#3627408458;=&#3627408467;
&#3627408482;=??????
&#3627408474;&#3627408453;
&#3627408476;&#3627408482;&#3627408481;×
1
2??????&#3627408453;
&#3627408476;&#3627408482;&#3627408481;&#3627408438;
&#3627408476;&#3627408482;&#3627408481;
≈
&#3627408468;
&#3627408474;
2??????&#3627408438;
??????
&#3627408468;
&#3627408474;=2??????&#3627408438;
??????×&#3627408467;
&#3627408482;=1.257&#3627408474;&#3627408454;
❑Let
&#3627408468;
&#3627408474;
??????
&#3627408439;
=5&#3627408454;??????→25(&#3627408458;??????)
❑Then
??????
&#3627408439;≈50&#3627409159;&#3627408436;&#3627408458;??????→250&#3627409159;&#3627408436;(&#3627408454;??????)
The gm/ID Design Methodology Demystified 69
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB ?
gm/ID ?
L ?vin
vout
CL
IB

70. www.master-micro.com
Pick gm/ID
❑Let
&#3627408468;
&#3627408474;
??????
&#3627408439;
=15(&#3627408448;??????)
❑Then
??????
&#3627408439;≈83.8&#3627409159;&#3627408436;→80&#3627409159;&#3627408436;
&#3627408468;
&#3627408474;
??????
&#3627408439;
=
1.257&#3627408474;
0.08&#3627408474;
=15.71
The gm/ID Design Methodology Demystified 70
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB 80 uA
gm/ID 15.71
L ?vin
vout
CL
IB

71. www.master-micro.com
Pick L
|&#3627408436;
&#3627408483;|=&#3627408468;
&#3627408474;??????
&#3627408476;=
&#3627408468;
&#3627408474;
&#3627408468;
&#3627408465;&#3627408480;
|&#3627408436;
&#3627408483;|=
&#3627408468;
&#3627408474;
??????
&#3627408439;
⋅??????
&#3627408439;??????
&#3627408476;=
&#3627408468;
&#3627408474;
??????
&#3627408439;
⋅&#3627408457;
&#3627408436;
❑The higher the L the higher the &#3627408457;
&#3627408436;
❑You may expect |&#3627408436;
&#3627408483;|vs gm/ID to be a straight line with
slope = &#3627408457;
&#3627408436;
❑But &#3627408457;
&#3627408436;depends on gm/ID
▪The design charts take care of all dependencies
The gm/ID Design Methodology Demystified 71
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB 80 uA
gm/ID 15.71
L ?vin
vout
CL
IB

72. www.master-micro.comThe gm/ID Design Methodology Demystified 72
Pick L

73. www.master-micro.com
Pick L
|&#3627408436;
&#3627408483;|=&#3627408468;
&#3627408474;??????
&#3627408476;=
&#3627408468;
&#3627408474;
&#3627408468;
&#3627408465;&#3627408480;
>50
The gm/ID Design Methodology Demystified 73
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB 80 uA
gm/ID 15.71
L 0.22 umvin
vout
CL
IB

74. www.master-micro.com
Lookup W
The gm/ID Design Methodology Demystified 74
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB 80 uA
gm/ID 15.71
L 0.22 um
LUT ID W
Design ProblemIdx Wxvin
vout
CL
IB
&#3627408458;
??????=&#3627408458;×
??????
&#3627408439;??????
??????
&#3627408439;
=&#3627408458;×
80&#3627409159;&#3627408436;
??????
&#3627408439;

75. www.master-micro.comThe gm/ID Design Methodology Demystified 75
Lookup W

76. www.master-micro.com
&#3627408458;
??????=&#3627408458;×
??????
&#3627408439;??????
??????
&#3627408439;
=&#3627408458;×
80&#3627409159;&#3627408436;
??????
&#3627408439;
=10.05&#3627409159;&#3627408474;
Lookup W
LUT ID W
Design ProblemIdx Wx
The gm/ID Design Methodology Demystified 76
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB 80 uA
gm/ID 15.71
L 0.22 umvin
vout
CL
IB

77. www.master-micro.com
Results: Testbench #1
❑How to set the high impedance node?
The gm/ID Design Methodology Demystified 77
Spec ADT Simulation
DC Gain51.4 51.44
GBW 200 MHz 196.8 MHzvin
vout
CL
IB

78. www.master-micro.com
Testbench #2
❑How to set the high impedance node?
❑But need accurate value of VGS: Look-up VGS
The gm/ID Design Methodology Demystified 78vin
vout
CL
IB

79. www.master-micro.comThe gm/ID Design Methodology Demystified 79
Lookup VGS

80. www.master-micro.com
Results: Testbench #2
The gm/ID Design Methodology Demystified 80
Spec ADT Simulation
DC Gain51.4 51.44
GBW 200 MHz196.3 MHzvin
vout
CL
IB

81. www.master-micro.com
gm Spec Revisited
??????&#3627408437;&#3627408458;=&#3627408467;
&#3627408482;≈
&#3627408468;
&#3627408474;
2??????&#3627408438;
??????+&#3627408438;
&#3627408465;&#3627408465;
&#3627408468;
&#3627408474;=2??????1??????+&#3627408438;
&#3627408465;&#3627408465;×200&#3627408448;=?
❑Assuming the same current
▪Need higher gm/ID
▪But higher gm/ID means larger W and
larger &#3627408438;
&#3627408465;&#3627408465;
▪Need help from ADT!
The gm/ID Design Methodology Demystified 81
Spec Constraint
DC Gain 50
GBW 200 MHz
CL 1 pF
DOF Value
IB 80 uA
gm/ID ?
L 0.22 umvin
vout
CL
IB

82. www.master-micro.comThe gm/ID Design Methodology Demystified 82
Revisiting gm/ID

83. www.master-micro.com
Final Design
The gm/ID Design Methodology Demystified 83
Spec ADT Simulation
DC Gain 51.5 51.53
GBW 200 MHz 199.8 MHzvin
vout
CL
IB
DOF Value
IB 80 uA
gm/ID 15.95
L 0.22 um

84. www.master-micro.com
Outline
❑Why gm/ID?
❑The BJT Story
❑The MOSFET Story
❑The MOSFET Design Problem
❑The Look-up Tables (LUTs)
❑Design Examples
▪Design Example #1
▪Design Example #2
The gm/ID Design Methodology Demystified 84

85. www.master-micro.com
Design Example #2
The gm/ID Design Methodology Demystified 85
❑Use relatively short L and relatively large gm/ID for M1
❑Use relatively long L and relatively small gm/ID for M2
❑If we start with the previous design as a reference point for M1
▪We will need higher M1(L) to compensate for ??????
&#3627408476;2
▪We will need higher M1(gm/ID) to compensate for added parasitics
Spec Constraint
DC Gain 50
GBW 200 MHz
IB < 100 uA
ΣW*L < 200 um
2
CL 1 pF
DOF Value
IB ?
M1(gm/ID)?
M1(L) ?
M2(gm/ID)?
M2(L) ?vin
M2
VB
M1
vout
CL

86. www.master-micro.comThe gm/ID Design Methodology Demystified 86
Design DB Generation

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Design Xplore

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Design Tuning: Pick L

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Design Tuning: Pick gm/ID

90. www.master-micro.comThe gm/ID Design Methodology Demystified 90
Live Tuning and More!

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Thank you!

92. www.master-micro.com
References (1/3)
❑P. Jespersand B. Murmann, Systematic Design of Analog CMOS Circuits Using Pre-Computed Lookup Tables,
Cambridge University Press, 2017.
❑B. Murmann, Gm/ID Starter Kit. [Online]. Available: https://web.stanford.edu/~murmann/gmid
The gm/ID Design Methodology Demystified 92

93. www.master-micro.com
References (2/3)
❑A. A. Youssef, B. Murmannand H. Omran, "Analog IC Design Using Precomputed Lookup Tables: Challenges
and Solutions," in IEEE Access, vol. 8, pp. 134640-134652, 2020.
The gm/ID Design Methodology Demystified 93

94. www.master-micro.com
References (3/3)
❑https://www.master-micro.com/mastering-microelectronics/courses/analog-ic-design
The gm/ID Design Methodology Demystified 94

95. www.master-micro.com
Q & A
“If you can't describe what you are doing as a process, you don't know what you're doing.”
W. Edwards Deming
Why ADT? 95
Productive!
Systematic!
Fun!
Optimized!

96. Lecture 13
gm/ID Design Methodology
Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
Dr. Hesham A. Omran
Analog IC Design
ًليِلَ ق الَِّإ ِمْلِعْلا
َ
نِم
ْ
م
ُ
تيِتوُأ ا
َ
م
َ
و
22 August 2022 24 مرحم1444

97. Outline
❑MOSFET figures-of-merit (FoM)
❑SPICE vs square-law
❑&#3627408457;
∗
and &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
❑Subthreshold operation (weak inversion)
❑Gm/ID design methodology
13: gm/ID Design 2

98. Outline
❑MOSFET figures-of-merit (FoM)
❑SPICE vs square-law
❑&#3627408457;
∗
and &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
❑Subthreshold operation (weak inversion)
❑Gm/ID design methodology
13: gm/ID Design 3

99. MOSFET Figures-of-Merit (FoM)
❑Intrinsic gain: gm*ro
❑Intrinsic frequency (transit frequency): gm/Cgg
❑Current (transconductance) efficiency: gm/ID
13: gm/ID Design 4

100. Intrinsic Gain
??????
&#3627408476;&#3627408482;&#3627408481;=−&#3627408468;
&#3627408474;??????
??????&#3627408475;&#3627408479;
&#3627408476;
|??????
??????|=
??????
&#3627408476;&#3627408482;&#3627408481;
??????
??????&#3627408475;
=&#3627408468;
&#3627408474;&#3627408479;
&#3627408476;
❑&#3627408468;
&#3627408474;&#3627408479;
&#3627408476;is the max gain that can be obtained from a single
transistor
&#3627408468;
&#3627408474;&#3627408479;
&#3627408476;=
2??????
??????
&#3627408457;
&#3627408476;&#3627408483;
⋅
1
&#3627409158;??????
??????
=
2
&#3627409158;&#3627408457;
&#3627408476;&#3627408483;
=
2&#3627408457;
??????
&#3627408457;
&#3627408476;&#3627408483;
❑For higher gain
▪Lower &#3627408457;
&#3627408476;&#3627408483;(or equivalently lower ??????
??????): weak inversion and
subthreshold operation
▪Longer ??????(i.e., smaller &#3627409158;)
▪Both come at the expense of speed
13: gm/ID Design 5vin
vout

101. Intrinsic Frequency
❑&#3627408467;
&#3627408455;is the frequency at which the MOSFET s.c.current gain
drops to one (i.e., unity-gain frequency)
??????
&#3627408476;&#3627408482;&#3627408481;=&#3627408468;
&#3627408474;??????
??????&#3627408480;=&#3627408468;
&#3627408474;
??????
??????&#3627408475;
&#3627408480;??????
????????????
@ ??????
&#3627408476;&#3627408482;&#3627408481;=??????
??????&#3627408475;
&#3627408467;
&#3627408455;=
&#3627408468;
&#3627408474;
2????????????
????????????
≈
1
2??????
⋅&#3627409159;??????
&#3627408476;??????
&#3627408458;
??????
&#3627408457;
&#3627408476;&#3627408483;⋅
1
2
3
&#3627408458;????????????
&#3627408476;??????
≈
3&#3627409159;&#3627408457;
&#3627408476;&#3627408483;
4????????????
2
13: gm/ID Design 6iout
iin

102. Intrinsic Frequency (Speed)
❑&#3627408467;
&#3627408455;is the frequency at which the MOSFET s.c.current gain
drops to one (i.e., unity-gain frequency)
&#3627408467;
&#3627408455;≈
3&#3627409159;&#3627408457;
&#3627408476;&#3627408483;
4????????????
2
❑For higher speed
▪Higher &#3627408457;
&#3627408476;&#3627408483;(or equivalently higher ??????
??????): strong inversion
and higher power consumption
▪Shorter ??????(technology scaling helps!)
▪Just opposite to higher gain!
▪Analog design is all about trade-offs!
❑After velocity sat, &#3627408468;
&#3627408474;and &#3627408467;
&#3627408455;saturate and become
independent of &#3627408457;
&#3627408476;&#3627408483;
13: gm/ID Design 7iout
iin

103. gm/ID
❑gm/ID is the transconductance per unit current (a measure of energy efficiency)
▪How much transconductance (or GBW) can we get from each micro-amp of current
&#3627408468;
&#3627408474;
??????
??????
=
2
&#3627408457;
&#3627408476;&#3627408483;
❑For higher efficiency
▪Lower &#3627408457;
&#3627408476;&#3627408483;(or equivalently lower ??????
??????): weak inversion and subthreshold operation
▪Comes at the expense of speed
13: gm/ID Design 8

104. Outline
❑MOSFET figures-of-merit (FoM)
❑SPICE vs square-law
❑&#3627408457;
∗
and &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
❑Subthreshold operation (weak inversion)
❑Gm/ID design methodology
13: gm/ID Design 9

105. SPICE vs Square-Law: &#3627408520;
&#3627408526;&#3627408531;
&#3627408528;
❑Square-law expects infinite &#3627408468;
&#3627408474;&#3627408479;
&#3627408476;at &#3627408457;
&#3627408476;&#3627408483;=0
&#3627408468;
&#3627408474;&#3627408479;
&#3627408476;=
2
&#3627409158;&#3627408457;
&#3627408476;&#3627408483;
=
2&#3627408457;
??????
&#3627408457;
&#3627408476;&#3627408483;
13: gm/ID Design 10

106. SPICE vs Square-Law: &#3627408519;
&#3627408507;
❑Square-law expects &#3627408467;
&#3627408455;increases linearly with &#3627408457;
&#3627408476;&#3627408483;
&#3627408467;
&#3627408455;=
&#3627408468;
&#3627408474;
2????????????
????????????
≈
3&#3627409159;&#3627408457;
&#3627408476;&#3627408483;
4????????????
2
13: gm/ID Design 11

107. SPICE vs Square-Law: &#3627408520;
&#3627408526;/??????
&#3627408491;
❑Square-law expects infinite &#3627408468;
&#3627408474;/??????
??????at &#3627408457;
&#3627408476;&#3627408483;=0
&#3627408468;
&#3627408474;
??????
??????
=
2
&#3627408457;
&#3627408476;&#3627408483;
13: gm/ID Design 12

108. SPICE vs Square-Law: The Sweet-Spot
❑Global maximum in MI: Sweet-spot
▪Best compromise between efficiency and speed
13: gm/ID Design 13

109. SPICE vs Square-Law: Conclusions
❑Square-law fails to describe SI accurately
▪Short channel effects (e.g., velocity sat.) are not considered
❑Square-law fails to describe MI and WI completely
▪A completely different approach is required
13: gm/ID Design 14

110. Outline
❑MOSFET figures-of-merit (FoM)
❑SPICE vs square-law
❑&#3627408457;
∗
and &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
❑Subthreshold operation (weak inversion)
❑Gm/ID design methodology
13: gm/ID Design 15

111. V-star &#3627408509;
∗
❑We used &#3627408468;
&#3627408474;=
2??????
??????
??????????????????
which is based on the square-law
❑For a real MOSFET &#3627408457;
&#3627408476;&#3627408483;≠
2????????????
????????????
❑Let’s define a new parameter called V-star &#3627408457;
∗
which is calculated from actual simulation
data using the formula
&#3627408457;
∗
=
2??????
??????
&#3627408468;
&#3627408474;
↔&#3627408468;
&#3627408474;=
2??????
??????
&#3627408457;
∗
❑For a square-law device, &#3627408457;
∗
=&#3627408457;
&#3627408476;&#3627408483;, however, for a real MOSFET they are not equal.
13: gm/ID Design 16

112. Figures-of-Merit Revisited
❑Redefine the figures-of-merit in terms of &#3627408457;
∗
&#3627408468;
&#3627408474;&#3627408479;
&#3627408476;=
2??????
??????
&#3627408457;
∗
⋅
1
&#3627409158;??????
??????
=
2
&#3627409158;&#3627408457;
∗
=
2&#3627408457;
??????
&#3627408457;
∗
&#3627408467;
&#3627408455;=
&#3627408468;
&#3627408474;
2????????????
????????????
=
1
2??????
⋅
2??????
??????
&#3627408457;
∗
⋅
1
??????
????????????
&#3627408468;
&#3627408474;
??????
??????
=
2
&#3627408457;
∗
❑Does &#3627408457;
∗
continue to decrease as &#3627408457;
&#3627408476;&#3627408483;goes towards weak inversion?
13: gm/ID Design 17

113. &#3627408509;
∗
vs &#3627408509;
&#3627408528;??????
❑SI: &#3627408509;
∗
>&#3627408509;
&#3627408528;??????→&#3627408468;
&#3627408474;=
2??????
??????
??????
∗
is less than square-law expectations
❑WI: &#3627408509;
∗
≈&#3627408464;&#3627408476;&#3627408475;&#3627408480;&#3627408481;??????&#3627408475;&#3627408481;→Why?
13: gm/ID Design 18

114. Drain Saturation Voltage (&#3627408457;
&#3627408491;&#3627408480;&#3627408462;&#3627408481;)
❑In generalMOSFET is in saturation if &#3627408457;
??????&#3627408454;>&#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
❑The definition of &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;is a bit vague
▪??????
??????keeps increasing if &#3627408457;
??????&#3627408454;>&#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;due to CLM/DIBL
▪&#3627408479;
&#3627408476;is quite low at edge of saturation (&#3627408457;
??????&#3627408454;=&#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;)
•&#3627408479;
&#3627408476;increases by multiple folds by biasing the MOSFET deeper into saturation
▪For a square-law device: &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;=&#3627408457;
&#3627408476;&#3627408483;
•In actual model &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;is a bit complex parameter
▪&#3627408457;
∗
is usually larger than &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
•As an approximation we can use &#3627408457;
??????&#3627408454;>&#3627408457;
∗
as sat. condition
•Guarantees biasing the MOSFET a bit deeper into saturation
13: gm/ID Design 19

115. &#3627408509;
∗
vs &#3627408509;
&#3627408491;&#3627408532;??????&#3627408533;vs &#3627408509;
&#3627408528;??????
❑&#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;<&#3627408457;
&#3627408476;&#3627408483;in SI but &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;>&#3627408457;
&#3627408476;&#3627408483;in WI
❑&#3627408457;
∗
always >&#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
13: gm/ID Design 20

116. Is &#3627408509;
&#3627408491;&#3627408532;??????&#3627408533;really meaningful?
❑&#3627408479;
&#3627408476;=
??????
??????
????????????
is quite low at &#3627408457;
??????&#3627408454;=&#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;→Longer ??????doesn’t help!
❑&#3627408479;
&#3627408476;increases order of magnitude by going deeper into saturation
▪Longer ??????helps only when&#3627408457;
??????&#3627408454;is large
13: gm/ID Design 21

117. Outline
❑MOSFET figures-of-merit (FoM)
❑SPICE vs square-law
❑&#3627408457;
∗
and &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
❑Subthreshold operation (weak inversion)
❑Gm/ID design methodology
13: gm/ID Design 22

118. Subthreshold Operation (Weak Inversion)
❑MOSFET behaves as a BJT (npnfor an NMOS) with its base coupled to the gate through
capacitive divider
▪Subthreshold current depends exponentially on &#3627408457;
??????&#3627408454;
▪For &#3627408457;
??????&#3627408454;>&#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;(saturation):
??????
??????≈??????
0
&#3627408458;
??????
&#3627408466;
??????
&#3627408442;&#3627408454;−??????
&#3627408455;&#3627408443;
&#3627408475;??????
&#3627408455;
&#3627408475;=
??????
&#3627408476;??????+??????
&#3627408465;&#3627408466;&#3627408477;
??????
&#3627408476;??????
≈1.2→1.5
13: gm/ID Design 23S
G
D
B
Cox
Cdep

119. Subthreshold Slope &#3627408506;
??????
??????=??????
0
&#3627408458;
??????
&#3627408466;
??????
&#3627408442;&#3627408454;−??????
&#3627408455;&#3627408443;
&#3627408475;??????
&#3627408455;
log??????
??????=log??????
0
&#3627408458;
??????
&#3627408466;
−??????&#3627408455;&#3627408443;
&#3627408475;??????&#3627408455;+
&#3627408457;
??????&#3627408454;
&#3627408475;&#3627408457;
&#3627408455;
log&#3627408466;
??????=
??????log??????
??????
??????&#3627408457;
??????&#3627408454;
−1
=
&#3627408475;&#3627408457;
&#3627408455;
log&#3627408466;
=&#3627408475;&#3627408457;
&#3627408455;ln10=&#3627408475;×60&#3627408474;&#3627408457;/&#3627408465;&#3627408466;&#3627408464;??????&#3627408465;&#3627408466;
❑Example: ??????=0.2886−02074≈81&#3627408474;&#3627408457;/&#3627408465;&#3627408466;&#3627408464;??????&#3627408465;&#3627408466;→&#3627408475;≈1.35
13: gm/ID Design 24S
G
D
B
Cox
Cdep

120. &#3627408509;
∗
in Weak Inversion
??????
??????=??????
??????&#3627408476;
&#3627408458;
??????
&#3627408466;
??????
&#3627408442;&#3627408454;
&#3627408475;??????
&#3627408455;
&#3627408468;
&#3627408474;=
????????????
??????
??????&#3627408457;
??????&#3627408454;
=
??????
??????
&#3627408475;&#3627408457;
&#3627408455;
=
2??????
??????
&#3627408457;
∗
&#3627408509;
∗
=??????&#3627408527;&#3627408509;
&#3627408507;
❑At the boundary between exponential weak inversion (WI) and quadratic strong inversion
(SI): a.k.a. the onset of strong inversion
&#3627408457;
∗
=&#3627408457;
&#3627408476;&#3627408483;
&#3627408457;
&#3627408476;&#3627408483;=2&#3627408475;&#3627408457;
&#3627408455;≈1.2→1.5×52&#3627408474;&#3627408457;≈60→80&#3627408474;&#3627408457;
❑The region between WI (exponential behavior) and SI (square-law behavior) is referred to
as moderate inversion (MI)
▪No simple models for this region (a.k.a. near-threshold operation)
13: gm/ID Design 25

121. Subthreshold Intrinsic Gain
&#3627408468;
&#3627408474;&#3627408479;
&#3627408476;=
2??????
??????
&#3627408457;
∗
⋅
1
&#3627409158;??????
??????
=
2
&#3627409158;&#3627408457;
∗
=
1
&#3627409158;&#3627408475;&#3627408457;
&#3627408455;
=
&#3627408457;
??????
&#3627408475;&#3627408457;
&#3627408455;
❑Independent of &#3627408457;
&#3627408476;&#3627408483;
❑Gain does not improve as we go deeper in subthreshold
13: gm/ID Design 26

122. Subthreshold Current Efficiency
&#3627408468;
&#3627408474;
??????
??????
=
2
&#3627408457;
∗
=
1
&#3627408475;&#3627408457;
&#3627408455;
❑Independent of &#3627408457;
&#3627408476;&#3627408483;
❑Efficiency does not improve as we go deeper in subthreshold
13: gm/ID Design 27

123. Subthreshold Intrinsic Speed
&#3627408467;
&#3627408455;=
&#3627408468;
&#3627408474;
2????????????
????????????
≈
1
2??????
⋅
2??????
??????
&#3627408457;
∗
⋅
1
??????
????????????
≈
??????
??????
2??????&#3627408475;&#3627408457;
&#3627408455;??????
????????????
❑Speed &#3627408467;
&#3627408455;continues to degrade as we go deeper in subthreshold
▪??????
??????decreases exponentially
13: gm/ID Design 28

124. Near-Threshold (MI) Biasing
❑Operating the MOSFET in the near-threshold (moderate inversion) region is becoming
increasingly popular.
▪We already reap most of WI benefits
•Higher gain
•Higher efficiency
•Some degradation in speed (&#3627408467;
&#3627408455;is already very high for short ??????)
❑Going deeper into WI is seldom useful
▪Minor/no benefit in gain
▪Minor/no benefit in efficiency
▪Exponential degradation in speed
▪Exponential increase in area and parasitics
▪But may be useful if we intentionally need very low ??????
??????(ultra low power applications)
13: gm/ID Design 29

125. MOSFET Capacitance in WI vs SI
❑For SI: ??????
??????&#3627408463;≈0, ??????
??????&#3627408480;≫??????
??????&#3627408465;
❑For WI: ??????
??????&#3627408463;↑, ??????
??????&#3627408480;≈??????
??????&#3627408465;
▪For long channel ??????
??????&#3627408463;in WI is more significant
▪For short channel, source and drain still hide the bulk even in WI
13: gm/ID Design 30
??????=100&#3627408475;&#3627408474;??????=1&#3627409159;&#3627408474;
[Jespers& Murmann, 2018]

126. Outline
❑MOSFET figures-of-merit (FoM)
❑SPICE vs square-law
❑&#3627408457;
∗
and &#3627408457;
??????&#3627408480;&#3627408462;&#3627408481;
❑Subthreshold operation (weak inversion)
❑Gm/ID design methodology
13: gm/ID Design 31

127. Don’t be a SPICE Monkey!
❑In absence of a clear methodology for hand analysis, many designers tend to converge
toward a “SPICE monkey” design methodology.
▪No hand calculations, iterate in SPICE until the circuit “somehow” meets the
specifications
▪Typically results in sub-optimal designs, uninformed design decisions, etc.
❑A SPICE monkey is someone who does not use hand analysis to figure out how to design a
circuit, but rather plugs stuff into SPICE and uses whatever value works.
13: gm/ID Design 32[Murmann, EE214B, Stanford]

128. gm/ID Design Methodology
❑Traditionally, square-law was used in hand analysis to obtain initial design point
▪But short channel and moderate/weak inversion devices do not obey the square law
▪Square law is seldom used in nowadays designs
❑The popular approach nowadays is using gm/ID (or equivalently V*) design methodology
❑Perform DC sweeps for both PMOS and NMOS to generate design charts vs gm/ID
▪Or use look-up tables (LUTs) and access them using any programming language
(MATLAB, Python, etc.)
❑Use these charts (LUTs) to design your circuit to meet required specs
13: gm/ID Design 33

129. The Design Problem
❑MOSFET is a function of five variables
▪3 (voltages) + 2 (sizing)
❑Strictly: the designer needs to specify 5 DOF for every device in the circuit
▪(VGS, VDS, VSB, W, L)
❑For analog IC design, MOS is usually biased in saturation (essentially a VCCS)
▪VGS is the primary voltage controlling the device behavior
▪VDS is of secondary importance: set to VDSAT + margin
▪VSB is of tertiary importance: usually imposed by circuit topology
❑Practically: the designer worries about 3 DOF
▪(VGS, W, L)
❑We usually set the device current (using current mirrors) rather than the device voltage
▪(ID, W, L)
13: gm/ID Design 34

130. DOFs in Conventional Design Flow
❑While tweaking a circuit in the simulator, the designer plays with 3 DOFs
▪(ID, W, L)
▪Sweeping any DOF (ID, W, L) changes the bias point (inversion level) of the device
▪The “search-range” of W can be quite large (depends on both ID and L)
❑The old fix:
▪Switch to (ID, Vov, L) instead of (ID, W, L)
▪But short channel and moderate/weak inversion devices do not obey the square law
❑The new fix:
▪Switch to (ID, V*, L)
13: gm/ID Design 35

131. DOFs in gm/ID Design Methodology
❑V* or gm/ID design methodology enables “orthogonal” DOFs
▪(ID, V*, L) or (ID, gm/ID, L)
▪gm/ID sets the inversion level independent of ID and L
▪When ID and/or L changes: Look up the new W in the LUTs (gm/ID kept unchanged)
▪Search-range of gm/ID is limited (typically 3 to 30)
▪gm/ID can be replaced by JD = ID/W for deep subthreshold design
13: gm/ID Design 36

132. gm/ID Design Methodology
❑&#3627408457;
&#3627408476;&#3627408483;has a vague physical meaning and does not help the designer’s intuition any more
❑On the contrary
▪gm/ID is a key MOSFET FoM
▪gm/ID captures the relation between the basic function of the transistor (the
transconductance) and the most valuable resource (the power consumption)
▪The range of gm/ID values doesn’t differ much from one device to another and from
one technology to another
▪gm/ID can be a thought as a normalized measure for the device inversion level
❑Conclusion: use gm/ID as your primary design variable
▪Plot everything vs gm/ID
13: gm/ID Design 37

133. Quiz
❑Assume &#3627408475;=1.5and &#3627408457;
&#3627408476;&#3627408483;<0.5&#3627408457;.
❑Assume square-law is valid in strong inversion.
❑Calculate gm/ID range.
❑Calculate the gm/ID at the sweet spot (&#3627408457;
∗
=200&#3627408474;&#3627408457;).
13: gm/ID Design 38

134. Quiz
❑Assume &#3627408475;=1.5and &#3627408457;
&#3627408476;&#3627408483;<0.5&#3627408457;.
❑Assume square-law is valid in strong inversion.
❑Calculate gm/ID range.
❑Calculate the gm/ID at the sweet spot (&#3627408457;
∗
=200&#3627408474;&#3627408457;).
❑&#3627408457;
&#3627408474;&#3627408462;??????
∗
=&#3627408457;
&#3627408476;&#3627408483;,&#3627408474;&#3627408462;??????=0.5&#3627408457;
❑&#3627408457;
&#3627408474;??????&#3627408475;
∗
=2&#3627408475;&#3627408457;
&#3627408455;=78&#3627408474;
❑
??????&#3627408474;
????????????
=
2
??????
∗
=4→25
13: gm/ID Design 39

135. The Lookup Table (LUT)
❑MOSFET is a function of five variables
▪3 (voltages) + 2 (sizing)
❑All MOSFET parameters are proportional to width
▪Narrow-width effects ignored (not common in
analog IC design)
▪Use normalized quantities (cross multiplication)
❑Degrees of freedom (DOFs) reduced to 4
▪VGS, VDS, VSB, and L
❑Simulate a reference device
▪Sweep the 4 DOFs
▪Construct a 4D LUT for every parameter
❑May ignore VDS and VSB dependence to plot 2D
parametric charts
13: gm/ID Design 40ID gm
gds gmb
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
VSB
VDS
VGS
L

136. gm/ID Charts: &#3627408520;
&#3627408526;&#3627408531;
&#3627408528;
13: gm/ID Design 41

137. gm/ID Charts: &#3627408509;
??????
13: gm/ID Design 42

138. gm/ID Charts: ??????
&#3627408491;/&#3627408510;
13: gm/ID Design 43

139. gm/ID Charts: &#3627408519;
&#3627408507;
13: gm/ID Design 44

140. gm/ID Charts: &#3627408490;
????????????/&#3627408490;
&#3627408520;&#3627408520;
13: gm/ID Design 45

141. gm/ID Charts: &#3627408520;
&#3627408526;/??????
&#3627408491;⋅&#3627408519;
&#3627408507;
13: gm/ID Design 46

142. Analog Design Trade-offs
❑There are always tradeoffs between gain, speed, and energy efficiency.
❑The design knobs to control the tradeoffs: gm/ID and L.
❑Choice of gm/ID
▪Large gm/ID: high efficiency (low power), large swing (low V*), high gain (low V*)
▪Small gm/ID: high speed, small area
❑Choice of ??????
▪Long ??????: high &#3627408479;
&#3627408476;, good matching, low flicker noise (more later)
▪Short ??????: high speed, small area
❑Finding the best compromise for design tradeoffs given required specs is your job as a
designer.
13: gm/ID Design 47

143. 13: gm/ID Design 48
Thank you!

144. References (1/3)
❑P. Jespersand B. Murmann, Systematic Design of Analog CMOS Circuits Using Pre-Computed Lookup Tables,
Cambridge University Press, 2017.
13: gm/ID Design 49

145. References (2/3)
❑M. N. Sabry, H. Omran and M. Dessouky, "Systematic design and optimization of operational
transconductance amplifier using gm/ID design methodology," Microelectronics Journal, vol. 75, pp. 87-96,
May 2018.
13: gm/ID Design 50

146. References (3/3)
❑B. Murmann, Gm/ID Starter Kit. [Online]. Available:
https://web.stanford.edu/~murmann/gmid
❑B. Murmann, EE214 Course Reader, Stanford University.
❑B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2
nd
ed., 2017.
❑T. C. Carusone, D. Johns, and K. W. Martin, “Analog Integrated Circuit Design,” 2
nd
ed.,
Wiley, 2012.
5113: gm/ID Design