JHDL

seminar

1. Just Another Hardware Description Language(JHDL) Name : Subhadeep Banerjee Roll No :

2. CONTENT INTRODUCTION WHAT IS JHDL NAMING OF JHDL FEATURES OF JHDL RELATIONSHIP OF JHDL JHDL DESIGN FLOW JHDL BITS IMPLEMENTATION JHDL TOOLS ADVANTAGES OF JHDL DISADVANTAGES OF JHDL CONCLUSION AND FUTUR USE REFERENCES

3. Introduction JHDL ( Just Another Hardware Description Language) is a low level structural hardware description language. Primarily on building circuits via an Object Oriented approach that bundles collections of gates into Java objects. The JHDL libraries were created in a layered fashion.

4. What is JHdl JHDL is a java based design language, it’s object oriented language. The Primary distinction of JHDL is the creation of a single integrated API . JHDL is a structural HDL(Hardware Depreciation Language). The key feature of JHDL is it’s ability to operate in either simulation or hardware mode.

5. Naming Originally, the J in "JHDL" stood for "Java". However, to prevent trademark issues, the name has been change to stand for Just Another Hardware Description Language .

6. Features The JHDL language features include: Structural hardware design Flexible module generators Table generated finite state machines A graphical "Workbench" toolkit

7. Features The integrated JHDL Workbench environment is designed to allow developers to graphically test and trace their circuit designs. This tool includes : A graphical schematic viewer A multiclock cycle based simulator A command line interface A complete list of all wires and gates A complete status of all values passing through the circuit

8. Relationship of open source constituents of jhdl bits

9. Jhdl design flow

10. Jhdl bits implementation

11. JHDL Tools Waveform Viewer Schematic Viewer Module Generator Libraries Hierarchy Browser Circuit Simulator

12. ADVANTAGES Easy to use . Has built in documentation capabilities. Is portable. Has rich set of GUI API that are integral to the language.

13. DISADVANTAGES The net interaction with router must be improved to decrease memory usage and reduce routing time . Improve execution time . Improve robustness. Provide more flexible interface between JHDL and the router.

14. CONCLUSION AND FUTURE USE A major goal has been to retain the properties and philosophies of J bits . It was essential to provide the ability to reconfigure the device through JHDL Bits design flow. It allows partitioning of design . ThedeveloperswouldinvestigateusingJHDLBitsinanembeddedsystem,usingsmallsubsetofJHDLrewritteninlanguageotherthanJavatoreducememoryusage . In current version of JHDL Bits, placement is performed in a greedy sub-optimal manner .

15. REFERENCES Official JHDL website (http://www.jhdl.org/) BYU's Configurable Computing Laboratory (http://ccl.ee.byu.edu) Cosmic Horizon JHDL (http://www.alanfeldstein.com/products/software/jhdl/) 1. Brent E. Nelson, "The Mythical CCM: In Search of Usable (and Reusable) FPGA Based General Computing Machines (http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.65)," asap, pp.514, IEEE 17th International Conference on Application specific Systems, Architectures and Processors (ASAP'06), 2006 Retrieved from "https:// en.wikipedia.org/w/index.php?title=JHDL & oldie=698345445 " Categories: Hardware description languages.