Joel Birch - Agilent Technologies - Digital Back to Basics Seminar - 2008

Presentation by Joel Birch for Agilent about logic analyzer basics explaining when to use a logic analyzer and how to use if, for example state vs timing analysis.

1. Logic Analyzer Basics
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 1
September 23, 2008
presented by:
Joel Birch

2. Introduction
The goal of this session is to help you learn about…
•What a logic analyzer is
•When to use a logic analyzer versus an oscilloscope
•The difference between a timing analyzer and a state analyzer
•What a trigger is
•What support is available for hot applications such as…
FPGAs, DDR memory, MIPI-DPHY, DigRF…and more
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 2
Trends in digital debug
•More digital content in designs
•Technology discontinuities require
new measurement methods

3. Agenda
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 3
•Determining when to use a logic analyzer or an oscilloscope
•Overview of a logic analyzer and measurement components
–Connect (Probing)
–Acquire
•Timing Analyzer
•State Analyzer
•Triggering
–View and Analyze
–Application Support & New Measurement Methods
•Conclusion
DDR1, 2 & 3

4. How to Determine What’s Right for your Application:
Oscilloscope or Logic Analyzer?
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 4

5. When to Use an Oscilloscope
•Parametric measurements
•Precise time vs voltage relationships
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 5
Droop
Ringing
Overshoot
Valid Logic 1
Valid Logic 0
Pulse Width
Rise Time
Fall Time

6. When to Use a Logic Analyzer
•Cause and effect timing relationships
•Many channels simultaneously
•Multiple bus correlation measurements
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 6
1
2
0
1
2
3
X/Y
X1
X2
Y0
Y1
Y2
Y3

7. Using a Logic Analyzer vs an Oscilloscope
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 7
Use a LogicAnalyzer to… Use an Oscilloscope to…
See many signals at once See 2to 4 signals at once
Look at signals the same way your
hardware does (Statemode)
Look at the analogcharacteristics of a
signal
Trigger on a patternof highs and lows on
several lines and see the result
Verify timing relationships across several
or hundreds of signals (Timing mode)
Get precisetime interval information

8. A Logic Analyzer is a Tool That
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 8
Connect Acquire
View &
Analyze
Gives you insight into the operation of a digitalcircuit by
Connecting to the DUT
(Device Under Test)

9. A Logic Analyzer is a Tool That…
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 9
Connect Acquire
View &
Analyze
Gives you insight into the operation of a digitalcircuit by
Connecting to the DUT
(Device Under Test)
Capturing and storing
digital data

10. A Logic Analyzer is a Tool That
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 10
Connect Acquire
View &
Analyze
Gives you insight into the operation of a digitalcircuit by
Connecting to the DUT
(Device Under Test)
Capturing and storing
digital data
Analyzing the stored data
and displaying the results

11. What Can A Logic Analyzer Do For Me?
•Capture and display digital activity
•Record a circuit’s logic levels over time and let you examine the record
•Show whether or not a particular event happens (trigger)
•Provide a precise measure of the time between events
•Inverse-assemble a microprocessor’s logic levels to tell you what code was
running
•Analyze complex buses and protocols
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 11

12. Probing
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 12
Connect Acquire
View &
Analyze
Connecting to the DUT
(Device Under Test)

13. Mechanical Probing Considerations
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 13
Designed-in
(connector & connectorless solutions)
Afterthought
(flying leads)

14. Mechanical Probing Considerations
•What can I fit on my board?
–Footprint size
–Low profile
•Usable
–Easy to attach
–Reliable, repeatable
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 14

15. Electrical Considerations
•Signal routing
•Low loading
–System tolerance
–Non-intrusive to DUT
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 15

16. Logic Analyzer Basics Webcast
Agilent TechnologiesPage 16
19851996 2003
“3M” 40-pin
Single-Ended
17 Channels
“Mictor”
Single-Ended
34 Channels
3pf loading
600Mb/s
Soft Touch
Connectorless
Single-Ended
Differential
34 Channels
<0.7pf loading
>2500Mb/s
Flying Leads
Single-Ended
Differential
Accessories
0.9pf loading
1500Mb/s
1973
First
Logic Analyzer
2000 2004
½ Size Soft Touch
Connectorless
Single-Ended
17 Channels
<0.7pf loading
>2500Mb/s
“Samtec”
Single-Ended
Differential
34 Channels
1.5pf loading
1500Mb/s
Soft Touch Pro
Connectorless
Single-Ended
Differential
34 Channels
<0.7pf loading
>2.5 Gb/s
Industry Standard
Footprint
Physical
probes
Virtual
probeATC2
FPGA
Dynamic
Probe
Probing Performance, Accuracy, Connectivity
Consistent Leadership in Logic Analyzer Probing
DDR2
BGA
Probe
2007
DDR BGA
probe
September 23, 2008

17. FPGA Dynamic Probe for Xilinx and Altera
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 17
ATC2Insert core with
Xilinx/Altera
design tools
FPGA
PC Board
FPGA Dynamic Probe SW
application supported by
16900/16800/1680/1690
Probe core output
JTAG
Control access to
new signals via
JTAG
Parallel

18. Acquire
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 18
Connect Acquire
View &
Analyze
Timing Analysis
(Logic Timing)
State Analysis
(Logic Events)

19. Understanding Logic Analyzer Specifications
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 19
. . .
.
.
.
External
(state)
Internal
(timing)
•>•CLK
From target
Channel Count (Width):
Number of signals sampled
Memory Depth:
Max Number of samples
per signal stored per trace
Max State Clock Rate:
Fastest external clocking supported
Max Timing Rate:
Fastest internal sampling clock speed
Sample mode selection
(State or timing)

20. Logic Analyzer Setup
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 20
Assign bus/signal names
Assign voltage
threshold
Assign channels
to buses/signals

21. Timing Mode (Asynchronous)
•Tells when the event happened
•Displays single edge timing relationships
•Enables triggering across multiple signals/buses
•Analogous to an oscilloscope with 1-bit resolution
•Useful for hardware debug
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 21
Asynchronous Sampling is
internal to the logic analyzer

22. Timing Mode: How It Works
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 22
V
Internal
Analyzer
Clock
Input
Threshold
Comparator
Output
(0 or 1)
V
Latch
VOutput
Internal
Analyzer
Clock
Input
Output
V
V
VThreshold

23. Timing Mode: Review Results in Waveform Display
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 23
View and measure timing relationships between buses & signals

24. High Speed Timing Zoom
•Simultaneous capture of state and timing through the same probe
•Characterize hardware with 250 ps resolution (4 GHz timing with 64K
depth)
•Provides a window of visibility around the trigger
•Very useful at high speeds
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 24

25. Transitional Storage
•Use memory efficiently
•Only stores transitions
•Two memory locations per transition
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 25
Signal being
acquired
Sampling
points
Transitional
storage
Memory
Full
200ns 10s 200ns

26. State Mode (Synchronous)
•Useful for determining whathappened –sequence of operations
•Trace values on a bus
•Track functional problems and code flow
•Useful for software debug and hardware/software integration
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 26
Synchronous Sampling clock
comes from device under test (DUT)

27. State Mode: Data Valid Window
Definition: Period of time in which data is stable
–Setup time: the time data is stable prior to the clock edge
–Hold time: the time data is stable following the clock edge
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 27
Data is transitioning
Data is stable

28. State Mode Setup/Hold Example
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 28
Setup
Time
Hold
Time
DUT
Clock
D Flip
Flop

29. State Mode: State Domain
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 29
DATA
CLOCK
AA 0C 61 B3
ClockData
1
2
3
AA
0C
B3

30. State Mode: Eye Finder
•Immediate confirmation and confidence in sampled data
–Automatic placement of the sample position in the data valid region
–Easy to modify manually
–Quick overview of target signal skew
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 30
Sampling point

31. State Mode = Synchronous Measurement
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 31
DUT
Input
Threshold
Comparator
Output
(0 or 1)V
Latch
VOutput
External DUT
Clock

32. State Mode: State Listing
•Trace values on a bus
•Track functional problems and code flow
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 32
STAT
SYMB
OPCOD
MEMWR
MEMWR
OPCOD
MEMRD
MEMRD
OPCOD
MEMRD
DATA
HEX
15
04
37
C3
00
08
22
D3
ADDR
HEX
0436
0BB6
0BB5
0024
0025
0026
0008
0009
Label>
Base>
-0003
-0002
-0001
+0000
+0001
+0002
+0003
+0004
ADDR 16
DATA 8
STAT 8
Circuit Measurement

33. State Mode: Listing Display with DDR Decoder
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 33

34. Triggering
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 34
Connect Acquire
View &
Analyze

35. What is a Trigger?
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 35
18
22
3Beginning
End
•Trigger
•Post-store
Trigger
Post-store
3
4
5
67
8
9
10
17
14
13
12
11
18
22
16
15
21
20
19
Ring Model
Pre-Store
Linear Model
A Trigger is an event that, when detected, allows the logic
analyzer to fill its trace memory and complete the measurement

36. Triggering –The Conveyor Belt Analogy
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 36
One Sample
Acquired Samples
Memory Depth
Trigger Position
Stop
= One box
= Boxes on the belt
= Number of boxes that will fit on the belt
= Position of special box when Stop button
is pressed
Trace Memory
Depth
Newest Sample Oldest Sample
Trigger Sample
A Trigger is an event that, when detected, allows the logic
analyzer to fill its trace memory and complete the measurement

37. Trigger Position
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 37
•Post-store
Trigger PositionUse of Trigger
Beginning Observe bootup sequence
or code execution
Center (Default)View time shortly
before/after event
End Trace cause of system
halt, Root cause analysis
(uncorrelated symptoms)
0 –100% Variable,custom selection
Trigger position = location of trigger event in trace memory

38. Defining Trigger Events
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 38
Measurement
Channel Input
Acquisition Buffer Display Buffer
Trigger Enable
Function
Logic Analyzer
Control
Trigger
Event
1 0 0 0 1
0 0 0 1 0
0 0 1 0 1
1 0 0 0 1
0 0 0 1 0
0 0 1 0 1
D
4 ... D
0
D
4 ... D
0

39. Defining Simple Trigger Events
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 39
Trigger on
Bus values
Trigger on
Signal values

40. Defining Advanced Trigger Events
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 40

41. The Complete Measurement
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 41
Comparator
Latch
Clock Signal
Trigger
Event
Acquisition
Buffer
Display
Buffer
Trigger Enable Function
Logic Analyzer
Control
D
6 ....D
0 D
6 ...D
0

42. View and Analyze
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 42
Connect Acquire
View &
Analyze
Analyzing the stored data
and displaying the results

43. Standard Viewing Displays
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 43
Waveform
Accumulate, Overlay, Import Scope Traces
Listing
Processor Pneumonics, Souce code

44. View Scope
•View time-correlated analog and
digital data, integrated on a single
waveform display
•Analyze analog characteristics of
digital anomalies
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 44

45. Eye Diagrams: Eye Scan
•Provides signal integrity
validation
measurements of entire
high-speed buses.
•Uses high resolution
comparators to scan
across specified time
and voltage range
•Provides up to 5mV and
10ps resolution
•Can be used as a tool of
“first attack” to reveal
tough signal integrity
problems.
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 45

46. Protocol Analysis: Packet Viewer
•Display data at the protocol
level
•Protocol trigger macro
allows easy trigger setup,
eliminates manual
configuration of complex
measurements
•Time correlate protocol
activity to other system
buses
•Protocol support includes
–Rapid IO
–PCIE Express
–USB
–Serial ATA
–Proprietary/Custom Protocols
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 46

47. Digital Vector Signal Analysis
•Perform in-depth time,
frequency and
modulation domain
analysis on your digital
baseband and IF signals
•View a signal as it
changes from a train of
perfect symbols to a
signal with filtering, pre-
distortion, re-sampling, or
other potential sources
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 47

48. Summary
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 48

49. Timing vs State Analysis
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 49
Timing Analysis State Analysis
When the event happened What sequenceof operations
executed
Edge relationships Monitor execution of processor
Hardwaredebug Software and system integration

50. Viewing and Analysis Tools
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 50
Eye Scan
Waveform
System Performance
Listing & IA
Source Code
View Scope
Packet Decode
Digital VSA

51. Support for Leading Applications
September 23, 2008Page 51
Logic Analyzer Basics Webcast
Agilent Technologies
Agilent Provides a Wide Range of Application Support
for FPGAs, Processors, Buses, and Protocols
FPGA Dynamic Probe for
Xilinx and Altera
BGA probes, Midbus probes
and Interposers for
DDR memory
MIPI D-PHY and DigRF
Stimulus and Acquisition
SATA Packet Analysis Probe

52. Q&A
Logic Analyzer Basics Webcast
Agilent Technologies
September 23, 2008Page 52