L01 Introduction to Digital System Design.pdf

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1. Introduction to Digital
System Design
Saba Zia
Assistant Professor
Electrical Engineering Department
Linking: CLO1, PLO3
Taxonomy: C6

2. Agenda
•FPGA Overview
•FPGA Architecture
•Hardware Parameters and Digital Platforms
•Ways to Program FPGA
•Design Examples

3. Behind These Attractive Systems

4. Interconnects
FPGA Internal Architecture
Configurable
Logic Blocks
Dedicated Blocks
Input and Output Blocks
Switching Matrix

5. Configurable Logic Block
(CLB)
LUT
D
S/R
Q
Carry
Chain
Carry
out
Carry
In
LUT
D
S/R
Q
Carry
Chain
Carry out
Carry In
SLICE
SLICE

6. FPGA Vs Microcontroller/DSP/ASIC
•Comparison with Microcontroller/Digital Signal Processor (DSP)
•FPGA is better than microcontroller/DSP in terms of
•Frequency (1000 times better than traditional DSP)
•Execution (Sequential/Parallel)
•Microcontroller is better in terms of
•Power
•Cost (For only low end controllers)
6
Low
Power
High
Speed
Chip
Size
Scalable
Reliable
Design
Time
Design
Cost

7. FPGA Vs Microcontroller/DSP/ASIC
•Comparison with ASIC
•FPGA is better than ASIC in terms of
•Reconfigurability
•Fabrication Cost
•Design Time
•ASIC is better than FPGA in terms of
•Low Power Consumption
•Speed
•Chip Size
7
Low
Power
High
Speed
Chip
Size
Scalable
Reliable
Design
Time
Design
Cost

8. Ways to Program FPGA
•Hardware Descriptive Language (HDL) such
a
s Verilog or VHDL
•Xilinx ISE/Vivado De sign Suite
•Intel Q
Prime Design
•C Programming
•VivadoH
•Intel HLS Compiler
•Open CL, Sy etc
•Simulink/MATLAB
•System Generator for DSP
•HDL Coder

9. ISE/Vivado/QuartusDesign Flow
module add(in`,in2,out)
endmodule
Simulation
Synthesis

10. Levels of Abstraction in Coding Style
•Transistor Level Modeling
•Gate Level Modeling
•Dataflow Modeling
•Behavioral Modeling
•Register Transfer Level (RTL) Modeling

11. Design Example- Multimedia Automation
•Requirement:
Turn on
Multimedia only
if Light and Fan
is turned on
Light (L) Fan (F) Multimedia
(M)
0 0 0
0 1 0
1 0 0
1 1 1
L
M
F

25. DigilentBasys3 Artix7 Board
Simulation
Synthesis

37. High Level Synthesis (HLS Flow)
C, C++
C Libraries
HLS Libraries
Verilog/ VHDL/
SystemC
VivadoIP Core
System Generator for
DSP

47. System Generator Design Flow
MATLAB Code Simulink Model
HDL
Hardware Co-
Simulation

49. Summary
•The kind of technology needed in high throughput systems
•Reconfigurable/Programmable FPGA Architecture
•Comparison of FPGA, Microcontrollers and ASICs
•Major FPGA Vendors
•FPGA programming using HDL
•Generating HDL codes via High Level Synthesis (HLS) tools
•Transforming Simulink model to HDL code