L12 ujt based triggering circuit

Part of Lecture series on EE321N, Power Electronics-I delivered by me during Fifth Semester of B.Tech. Electrical Engg., 2012
Z H College of Engg. & Technology, Aligarh Muslim University, Aligarh
Please comment and feel free to ask anything related. Thanks!

1. EE-321 N
Lecture-12
UJT (Unijunction Transistor)
&
UJT Based Triggering Circuit

2. Introduction
•Three terminal single junction latching device*
•Different from either diode (due to 3 terminals)
or the transistor (can’t amplify)
•Wide range of applications like oscillators, trigger
circuits, sawtooth generators, phase control
•Overcomes the limitations of previous trigger
circuits like power dissipation & high
dependability on the SCR chatacteristics
•Other variants include CUJT & PUT
31-Oct-12 EE-321N, Lec-12 2

3. Structure & Symbol E
B
2
B
1
B
1
A
B
2
E
R
B2
R
B1
n-type
p-type
Eta-point
Basic Structure Symbol
31-Oct-12 3 EE-321N, Lec-12

4. Equivalent Circuit R
B2
V
BB
+
-
E
B
1
R
B1
V
BB
A
+
-
V
e
I
e
B
2
Eta-point
V
1
V
D
Equivalent Circuit of UJT
31-Oct-12 4 EE-321N, Lec-12

5. Characteristics
31-Oct-12 5 EE-321N, Lec-12 V
e
V
BB
R load line
V
p
V
v
I
e
I
v
I
p
0
Peak Point
Cutoff
region
Negative Resistance
Region
Saturation
region
Valley Point

6. Device Description & Operation
•Consists of a lightly doped n-type Si base to
which heavily doped p-type emitter is
embedded
•At the two ends, there are ohmic contacts
designated as Base 1 & Base 2
•Thus the 3 terminals are: E, B
1 & B
2
•An interbase resistance R
BB = R
B1 + R
B2|
IE = 0
(~5-10 kΩ) exists between the two bases
31-Oct-12 EE-321N, Lec-12 6

7. Contd...
•Equivalent circuit consists of a pn junction
diode and the interbase resistance divided
into two parts R
B1 &
R
B2
•When a voltage V
BB is applied between the
bases, the potential of point A w. r. t. B
1 is
31-Oct-12 EE-321N, Lec-12 7 11
1
12
BB
AB BB BB BB
B B BB
RR
V V V V
R R R
  


8. Contd...
•Where,  is known as intrinsic stand off ratio
& ranges from 0.5-0.8
•When V
E < V
1, the equivalent diode is R. B.
This is the OFF state of the device & is shown
as very low current region on the V
E-I
E curve
•When V
E > V
1 + V
D, the diode becomes F. B.
this is the ON state of the device
•V
p = V
1 + V
D = V
BB + V
D is known as the peak
point voltage
31-Oct-12 EE-321N, Lec-12 8

9. Contd...
•Due to the flow of I
E through R
B1, number of
charge carriers in R
B1 is increased which reduces
its resistance, which in turn decrease V
1
•This causes diode to become more & more
F. B. & I
E increases further leading to a
regenerative action
•V
E decreases with increase in I
E & the device is
said to exhibit negative resistance
•Eventually, valley point will be reached after
which there will be no further decrease of R
B1
•After valley point, device will reach into
saturation state

31-Oct-12 EE-321N, Lec-12 9

10. UJT Relaxation Oscillator
31-Oct-12 EE-321N, Lec-12 10 R
R
2
V
BB
R
1
C
E
B
2
B
1V
e
v
o
V
e
V
p
V
V
V
o
t
t
Capacitor
charging

1
=RC


T
V +V
BB
V
P

21
=R C
Capacitor
discharging
V
v

11. Contd...
•The –ve resistance region of the UJT can be
used to advantage in relaxation oscillator
which can provide triggering pulses for SCR
•In the above ckt, R
1 & R
2 are chosen to be
much smaller than the interbase resistances
•The charging resistance R should be such that
its load line passes through the device
characteristics in the negative resistance
region
31-Oct-12 EE-321N, Lec-12 11

12. Contd...
•When a source voltage V
BB is applied to it, C
begins to charge through R exponentially towards
V
BB according to the equation

•When v
C reaches the peak point voltage, E-B
1
junction breaks down & the UJT turns ON. Now C
discharges rapidly through R
1
•
2 << 
1
•UJT turns OFF when the voltage decays to valley
voltage V
v
31-Oct-12 EE-321N, Lec-12 12  
/
1
t RC
C BB
v V e



13. Expression for Time Period of
Oscillation
•The time T required for C to charge from initial
voltage V
v to peak-point voltage V
p thru R can
be obtained as:

•Assuming
or
31-Oct-12 EE-321N, Lec-12 13  
/
1
t RC
p BB D v BB
V V V V V e

      
/
, 1
t RC
Dv
V V e

   11
ln
1
T RC
f 





14. Contd...
•If T is taken as the time pd. of the O/P pulse
duration (neglecting small discharge time),
then firing angle is given by


•Design considerations include selection of R
1,
R
2 & R

31-Oct-12 EE-321N, Lec-12 14 1
ln
1
T RC  






15. Resistance Values
31-Oct-12 EE-321N, Lec-12 15 max min
;
BB p BB v
pv
VV VV
RR
II
 
 1
GT
12
BB
BB
VR
V
R R R

 4
2
10
BB
R
V


16. Further Resources
1.Video lectures on “Basic Electronics & Lab”,
Prof. T. S. Natarajan, Lec-34 UJT
Available on www.nptel.iitm.ac.in,
www.youtube.com/iit
2.Boylestad & Nashelsky, “Electronic Devices &
Circuit Theory”, 7/e, PHI
31-Oct-12 16 EE-321N, Lec-12

17. Synchronized Circuit
31-Oct-12 EE-321N, Lec-12 17 R
C
+
-
D1 D3
D4 D2
V
dc
R
1
V
Z
+
-
Z
i
1
v
c
+
-
R
2
G
1
C
1
G
2
C
2
Pulse Transformer
E
B
2
B
1
To SCR
Gates