Lec- .pptx

this is a ppt of vlsi subjecty

1. Logic Gates Realization Using NMOS Design style

2. Introduction: We know that D-NMOSFET as a load Pull-up Network is used as load which is always ‘ON’.it is obtained by D-NMOSFET and when =0V It is always ON and act as a constant current source between supply and output node Pull-down network is used to evaluate the logic circuit. It is implemented by E-NMOSFET. NOTE: Derive the nmos transistor topology with following rules ( i ).Product terms in the Boolean function are implemented with series connected nmos transistors. (ii).Sum terms are mapped to nmos transistors connected in parallel.  

3. Cont …. 2 input NAND Gate(Y= ) The symbol representation of NAND Gate as shown in Below figure Schematic diagram  

4. Cont …. (2).2 input NOR Gate(Y= ) The Symbol representation of NOR Gate as shown in Below figure Schematic diagram  

5. Cont …. (3).2 input AND Gate(Y=A.B) Schematic diagram

6. Cont …. ( 4).2 input OR Gate(Y=A+B) Schematic diagram

7. Cont …. (5).2 input EX-OR Gate(Y=A B) Schematic diagram A=0 , =1,B=0 , =1 A=0 , =1,B=1 , = A=1 , =0,B=0 , =1 A=1 , =0,B=1 , =0