lecture 5_DC and Transient Response_VLSI.ppt

DC and Transient Response

1. Lecture 5:
DC &
Transient
Response

2. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 2
Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation

3. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 3
Pass Transistors
We have assumed source is grounded
What if source > 0?
–e.g. pass transistor passing V
DD
V
g = V
DD
–If V
s > V
DD-V
t, V
gs < V
t
–Hence transistor would turn itself off
nMOS pass transistors pull no higher than V
DD-V
tn
–Called a degraded “1”
–Approach degraded value slowly (low I
ds)
pMOS pass transistors pull no lower than V
tp
Transmission gates are needed to pass both 0 and 1

V
DD
V
DD

4. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 4
Pass Transistor Ckts
VDD
VDD
Vs = VDD-Vtn
VSS
Vs = |Vtp|
VDD
VDD-VtnVDD-Vtn
VDD-Vtn
VDD
VDD VDD VDD
VDD
VDD-Vtn
VDD-2Vtn

5. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 5
DC Response
DC Response: V
out vs. V
in for a gate
Ex: Inverter
–When V
in = 0 -> V
out = V
DD
–When V
in = V
DD -> V
out = 0
–In between, V
out depends on
transistor size and current
–By KCL, must settle such that
I
dsn = |I
dsp|
–We could solve equations
–But graphical solution gives more insight
I
dsn
I
dsp
V
out
V
DD
V
in

6. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 6
Transistor Operation
Current depends on region of transistor behavior
For what V
in and V
out are nMOS and pMOS in
–Cutoff?
–Linear?
–Saturation?

7. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 7
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
in
< V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
< V
gsn
– V
tn
V
out
< V
in
- V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
– V
tn
V
out
> V
in
- V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn = V
in
V
dsn = V
out

8. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 8
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
– V
tp
V
out
> V
in
- V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
– V
tp
V
out
< V
in
- V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp = V
in
- V
DD
V
dsp = V
out
- V
DD
V
tp < 0

9. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 9
I-V Characteristics
Make pMOS is wider than nMOS such that 
n
= 
p
Vgsn5
Vgsn4
Vgsn3
Vgsn2
Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0

10. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 10
Current vs. V
out
, V
in
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD

11. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 11
Load Line Analysis
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
For a given V
in
:
–Plot I
dsn, I
dsp vs. V
out
–V
out must be where |currents| are equal in
I
dsn
I
dsp
V
out
V
DD
V
in

12. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 12
Load Line Analysis
V
in = 0
V
in0
V
in0
I
dsn
, |I
dsp
|
V
out
V
DD
V
in1
V
in1I
dsn
, |I
dsp
|
V
out
V
DD
V
in2
V
in2
I
dsn
, |I
dsp
|
V
out
V
DD
V
in3
V
in3
I
dsn
, |I
dsp
|
V
out
V
DD
V
in4
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
Vin5
Idsn, |Idsp|
Vout
VDD
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
V
in
= 00.2V
DD
0.4V
DD
0.6V
DD
0.8V
DD
V
DD

13. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 13
DC Transfer Curve
Transcribe points onto V
in
vs. V
out
plot
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
V
in0
V
in1
V
in2
V
in3
V
in4V
in5

14. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 14
Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A Cutoff Linear
B SaturationLinear
C SaturationSaturation
D Linear Saturation
E Linear Cutoff
Vout
VDD
Vin

15. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 15
Beta Ratio
If 
p
/ 
n
 1, switching point will move from V
DD
/2
Called skewed gate
Other gates: collapse into equivalent inverter
V
out
0
V
in
V
DD
V
DD
0.5
1
2
10
p
n



0.1
p
n




16. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 16
Noise Margins
How much noise can a gate input see before it does
not recognize the input?
Indeterminate
Region
NM
L
NM
H
Input CharacteristicsOutput Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range

17. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 17
V
DD
V
in
V
out
V
OH
V
DD
V
OL
V
IL
V
IH
V
tn
Unity Gain Points
Slope = -1
V
DD
-
|V
tp
|

p
/
n
> 1
V
in
V
out
0
Logic Levels
To maximize noise margins, select logic levels at
–unity gain point of DC transfer characteristic
V
DD
V
in
V
out
V
DD

p
/
n
> 1
V
in
V
out
0

18. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 18
Transient Response
DC analysis tells us V
out
if V
in
is constant
Transient analysis tells us V
out(t) if V
in(t) changes
–Requires solving differential equations
Input is usually considered to be a step or ramp
–From 0 to V
DD
or vice versa

19. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 19
Inverter Step Response
Ex: find step response of inverter driving load cap
0
0
( )
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
 



 
0
2
2
0
(
2
)
( )
( )
DD t DD t
DD
out
out
out ot D t
n
u
ds
D t
I
t t
V V V V
V
V
V t
V V t
t
VV V





   

 
     
 
V
out
(t)
V
in
(t)
t
0
t
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

20. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 20
Delay Definitions
t
pdr: rising propagation delay
–From input to rising output
crossing V
DD
/2
t
pdf
: falling propagation delay
–From input to falling output
crossing V
DD/2
t
pd: average propagation delay
–t
pd = (t
pdr + t
pdf)/2
t
r: rise time
–From output crossing 0.2 V
DD

to 0.8 V
DD
t
f: fall time
–From output crossing 0.8 V
DD
to 0.2 V
DD

21. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 21
Delay Definitions
t
cdr
: rising contamination delay
–From input to rising output crossing V
DD/2
t
cdf: falling contamination delay
–From input to falling output crossing V
DD/2
t
cd: average contamination delay
–t
pd
= (t
cdr
+ t
cdf
)/2

22. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 22
Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
–Uses more accurate I-V models too!
But simulations take time to write, may hide insight
(V)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0 200p 400p 600p 800p 1n
t
pdf
= 66ps t
pdr
= 83ps
V
in
V
out

23. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 23
Delay Estimation
We would like to be able to easily estimate delay
–Not as accurate as simulation
–But easier to ask “What if?”
The step response usually looks like a 1
st
order RC
response with a decaying exponential.
Use RC delay models to estimate delay
–C = total capacitance on output node
–Use effective resistance R
–So that t
pd = RC
Characterize transistors by finding their effective R
–Depends on average current as gate switches

24. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 24
Effective Resistance
Shockley models have limited value
–Not accurate enough for modern transistors
–Too complicated for much hand analysis
Simplification: treat transistor as resistor
–Replace I
ds(V
ds, V
gs) with effective resistance R
•I
ds
= V
ds
/R
–R averaged across switching of digital gate
Too inaccurate to predict current at any given time
–But good enough to predict RC delay

25. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 25
RC Delay Model
Use equivalent circuits for MOS transistors
–Ideal switch + capacitance and ON resistance
–Unit nMOS has resistance R, capacitance C
–Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
kg
s
d
g
s
d
kC
kC
kC
R/k
kg
s
d
g
s
d
kC
kC
kC
2R/k

26. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 26
RC Values
Capacitance
–C = C
g
= C
s
= C
d
= 2 fF/m of gate width in 0.6 m
–Gradually decline to 1 fF/m in 65 nm
Resistance
–R  10 K•m in 0.6 m process
–Improves with shorter channel lengths
–1.25 K•m in 65 nm process
Unit transistors
–May refer to minimum contacted device (4/2 )
–Or maybe 1 m wide device
–Doesn’t matter as long as you are consistent

27. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 27
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
d = 6RC

28. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 28
Delay Model Comparison

29. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 29
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).
3
3
3
2 2 2

30. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 30
2 2 2
3
3
3
2 2 2
3
3
3
3C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
2 2 2
3
3
3
3C
3C
5C
5C
5C
9C
3-input NAND Caps
Annotate the 3-input NAND gate with gate and diffusion
capacitance.

31. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 31
Elmore Delay
ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
R
1
R
2
R
3
R
N
C
1
C
2
C
3
C
N
   
nodes
1 1 1 2 2 1 2
... ...
pd i to source i
i
N N
t R C
RC R R C R R R C
 

       


32. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 32
Example: 3-input NAND
Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
9C
3C
3C3
3
3
222
5hC
Y
n2
n1
h copies
 9 5
pdr
t h RC 
  
 
3 3 3 3 3 3
3 3 9 5
12 5
R R R R R R
pdf
t C C h C
h RC
        
 
 

33. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 33
Delay Components
Delay has two parts
–Parasitic delay
•9 or 12 RC
•Independent of load
–Effort delay
•5h RC
•Proportional to load capacitance

34. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 34
Contamination Delay
Best-case (contamination) delay can be substantially less than
propagation delay.
Ex: If all three inputs fall simultaneously
 
5
9 5 3
3 3
cdr
R
t h C h RC
   
    
    
   
9C
3C
3C3
3
3
222
5hC
Y
n2
n1

35. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 35
7C
3C
3C
3
3
3
222
3C
2C2C
3C3C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
Shared
Contacted
Diffusion
Diffusion Capacitance
We assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
–Reduces output capacitance by 2C
–Merged uncontacted diffusion might help too

36. CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 36
Layout Comparison
Which layout is better?
A
V
DD
GND
B
Y
A
V
DD
GND
B
Y