Lecture20_signal generator and PLL_.pptx

lecture slides on signal generator and PLL

1. Analog Electronics (ECE F341/EEE F341/ INSTR F341 ) Lecture 20 (IC 555 and Ramp generator) Instructor Dr. Apurba Chakraborty Assistant Professor Department of Electrical and Electronics Engineering BITS Pilani , K K Birla Goa Campus Date : 27/2/2024

2. Function Generator Frequency can be selected by capacitor or resistors. Here, current sources are designed as I1= I and I2 = 2I. The current I1 is constantly connected. SR ff acts as switch to make on/off the I2. Assume FF is in a state, when the I2 is disconnected. the capacitor charges by . When the voltage across the capacitor becomes 2/3 VCC switch of I2 closes and draws a 2I current and hence, the capacitor discharges with net current of I. Voltage across the capacitor drops linearly. When the capacitor voltage reaches 1/3VCC, the capacitor again starts charging and I2 is disconnected.  

3.   = => T = ( here charging and discharging happens by same current so. It is symmetric triangular curve.)   = Here, resistor and Vc are controlled externally through pins.  

4. Crystal Oscillator Working: Inverse Piezoelectric effect. If we apply some ac voltage the crystal will oscillate at certain frequency. Crystal: Quartz, Rochelle salt etc Advantage: very stable with time and temperature and very highly selective (high Q factor)

5. It is modelled as Of pF Of the crystal.   Series resonance Parallel resonance  

6. From, frequency plot, we see that between and the crystal reactance is inductive. So can replace the inductor in the colpitt’s oscillator. The resulting circuit will oscillate at the resonance frequency of the crystal inductance L with series equivalent of and + . Since is small compared to the others, this capacitance will dominate the oscillation frequency    

7. Sine wave converter (Triangular to sine wave converter): S No Range Slope (dV0/ dVi ) 1 - V1 V1 1 2 + V1 +V2 or – V2 -V1 R1/(R1+RA) 3 + V2 +V3 or – V3 -V2 (R1||R2/[R1||R2+RA]) 4 + V3 +V4 or – V4 -V3 (R1||R2||R3/[R1||R2||R3 + RA] 5 + V4 or 0 (no effect of input change). Constant output S No Range Slope (dV0/ dVi ) 1 1 2 R1/(R1+RA) 3 (R1||R2/[R1||R2+RA]) 4 (R1||R2||R3/[ R1||R2||R3 + RA ] 5 0 (no effect of input change). Constant output

8. Phase locked loop A phased locked loop is a frequency selective circuit designed to synchronize with an incoming signal and maintain in spite of noise or variation in the incoming signal frequency. The phase detector compares the phase of incoming signal with phase of the VCO output Vo and develops a voltage VD proportional to the difference phase difference . This phase is sent through a low pass filter to suppress the high frequency component and the result called error voltage is applied to the VCO to adjust its output frequency The VCO is designed so that its characteristics is . Here, if the = 0, then VCO will oscillate it’s own oscillating frequency, called free running frequency. is called sensitivity of VCO in rad/s.  

9. Phase detector Phase detector is a multiplier. Output of the PD will have two frequency components One is Fsum = f0+fs Another is f= fo -fs. The low pass filter will suppress the high frequency component and different frequency component will allowed to pass to generate the error signal. The error signal will drive VCO such that f becomes 0 (locked condition).  

10. Locked and capture range Capture range: It is the frequency range , centered about , over witch the loop can acquire lock Lock range: It is the frequency range over witch the loop can track the input once the lock has been established. Capture /pull-in time: the time required for PLL to capture the incoming signal is called capture time.  

11. PLL IC 565

12. Frequency multiplier In the locked condition, the input of two signals of PD will have same frequency Fs=f0/N So, f0= Nfs . To create N=5, the divide by 5 network can be designed as shown here.

13. IC8038

14. IC8038 Source: Internet