ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Lecture on
MOS (Metal Oxide Semiconductor) Structure
In this lecture you will learn:
• The fundamental set of equations governing the behavior of NMOS
structure
• Accumulation, Flatband, Depletion, and Inversion Regimes
• Large signal and small signal models of the NMOS capacitor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
MOS (Metal Oxide Semiconductor Field Effect Transistors (FETs)
100 nm
A 173 nm gate length MOS transistor
(INTEL)
GaAs (Substrate)
Source
AlGaAs
Drain
Gate
InGaAs (Quantum Well)
Silicon MOS FET
High Electron Mobility FET
22 nm gate length MOS transistors
(INTEL)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A N-MOS (or NMOS) Capacitor Structure
SiO
2
P-Si Substrate (or Bulk)
N+ Si Gate or Metal Gate
Gate metal
contact
Metal contact
GB
V
+
_
x
0
x
Doping:
N
a
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in 3D
P-Si substrate (or bulk)
N+ Si gate
L
Gate
Metal
W
N+ Si Gate or
Metal Gate
x
0
x
SiO
2
GB
V
+
_
Doping:
N
a
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor
x
0
o
x
t
SiO
2
P-Si N+ Si
or
Metal
Gate
Assumptions:
1) The potential in the metal gate is
If the gate is N+ Si then
2) The potential deep in the P-Si substrate is
3) The oxide (SiO
2
) is insulating (zero conductivity; no free electrons and holes ) and
is completely free of any charges
4) There cannot be any volume charge density inside the metal gate (it is very
conductive). But there can be a surface charge density on the surface of the metal
gate
5) Dielectric constants:
M
n
M
p
o ox
9.3
o s
7.11
ox
s
Doping:
N
a
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in Equilibrium
x
0
o
x
t
SiO
2
P-Si Gate
x
0
o
x
t
Potential Plot:
x
M
Potential?
0
GB
V
+-
We need to find the potential in equilibrium everywhere
Doping:
N
a
p M B
B
0
B
Assume:
log
a
p
i
N KT
qn
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in Equilibrium: Depletion Region
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
Step 2: Depletion region is created in the substrate near the o xide interface, and a
surface or sheet charge density is created on the metal gate
Step 1: Charges Flow
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
Positive surface charge density (C/cm
2
)
Negative depletion charge density (C/cm
3
)
do
x
a
qN
do a
G
x
qN
Q
Doping:
N
a
Doping:
N
a
Quantum
tunneling
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor in Equilibrium: Charge Densities
x
0
o
x
t
Charge density plot:
a
qN
do a G
x
qN
Q
Depletion region charge
density (C/cm
3
)
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
do
x
do a B
x
qN
Q
Total charge per unit area in
the semiconductor (C/cm
2
)
Positive surface charge density (C/cm
2
)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Electric field in the semiconductor:
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A NMOS Capacitor in Equilibrium: Electric Field
x x
qN
x E
x x E
qN
dx
dE
do
s
a
x
do x
s
a
s
x
0
Linearly varying
x
0
o
x
t
do
x
x
E
do
s
a
x
x
qN
x E
0
Boundary condition:
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Some Electrostatics
Consider an interface between media of different dielectric constants:
1
2
1
E
2
E
Suppose you know , can you find ???
1
E
2
E
Use the principle:The product of the dielectric constant and the normal
component of the electric field on both sides of an interface a re related as
follows:
I
Q E E
1 1 2 2
• Note that is the electric field JUST to the left of the interface and is the
electric field JUST to right of the interface
1
E
2
E
Interface sheet
charge density
(C/cm
2
)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Electric field in the oxide:
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A NMOS Capacitor in Equilibrium: Electric Field
ox
do a
x
x
ox
x
x qN
x E
x E
dx
dE
constant
0
x
0
o
x
t
do
x
x
E
ox
do a
s
do a
ox
x qN
xE
x qN
xE
xE xE
s
0
0
0 0
ox
s
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A NMOS Capacitor in Equilibrium: Potential
ox
s
2
2
x x
qN
x
x x x x
qN
x E
dx
x d
do
s
a
p
p do do
s
a
x
Potential in the semiconductor:
x
0
o
x
t
p
M
do
x
Boundary condition:
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A NMOS Capacitor in Equilibrium: Potential
ox
s
x
x qN x qN
x
x qN
x
x qN
x E
dx
x d
ox
do a
s
do a
p
s
do a
p
ox
do a
x
2
2
0
2
2
Potential in the oxide:
x
0
o
x
t
p
M
do
x
Boundary condition:
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A NMOS Capacitor in Equilibrium: Potential
ox
s
M ox
ox
do a
s
do a
p ox
t
x qN x qN
t x
2
2
Must have:
Therefore:
B
a
s
ox
s
ox
s
do
qN C C
x
2
2
ox
ox
ox
t
C
Oxide capacitance
(per unit area):
x
0
o
x
t
p
M
do
x
p M B
B
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A NMOS Capacitor in Equilibrium: Potential
ox
s
22
22
BOXS
a do a do a do a do
ox
ox s ox s
VV
qN x qN x qN x qN x
t
C
ox
ox
ox
t
C
Oxide capacitance
(per unit area)
Potential drop in the oxide
Potential drop in
the semiconductor
B
x
0
o
x
t
p
M
do
x
O
X
V
S
V
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
-- do
x
A Biased NMOS Capacitor: V
GB
>0
ox
s
x
0
o
x
t
p
d
x
All of the applied bias falls across the depletion region and t he oxide
GB B
V
do
x
d
x
s
da
ox
da
S OX GB Bx qN
C
x qN
V
V
V
2
2
B
Potential drop
in the oxide
Potential drop in
the semiconductor
-----
The depletion region widens
and the oxide field increases
when
V
GB
is positive
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A Biased NMOS Capacitor: V
GB
< 0
ox
s
x
0
o
x
t
p
d
x
All of the applied bias falls across the depletion region and t he oxide
GB B
V
do
x
d
x
s
da
ox
da
S OX GB Bx qN
C
x qN
V
V
V
2
2
B
Potential drop
in the oxide
Potential drop in
the semiconductor
The depletion region shortens and the oxide field decreases
when
V
GB
is negative
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
do
x
A Biased NMOS Capacitor: V
GB
< 0
ox
s
All of the applied bias falls across the depletion region and t he oxide
d
x
GB B
a
s
ox
s
ox
s
d
V
qN C C
x
2
2
ox
da
ox
x qN
E
The depletion region shrinks and the oxide field also decreases for
V
GB
< 0
x
0
o
x
t
p
d
x
GB B
V
do
x
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
A Biased NMOS Capacitor: Flatband Condition
ox
s
x
0
o
x
t
p
When
V
GB
is sufficiently negative, the depletion region thickness shrink s to zero
This value of
V
GB
is called the flatband voltage
V
FB
p M B FB
FB B
a
s
ox
s
ox
s
d
V
V
qN C C
x
0
2
2
Flatband voltage can be found by letting V
GB
equal to V
FB
and setting x
d
equal to 0 :
Potential in flatband
condition:
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
FB GB
V
V
+-
A Biased NMOS Capacitor: Accumulation (V
GB
< V
FB
)
ox
s
x
0
o
x
t
p
Potential:
GB B
V
Charge accumulation (due to holes) on the
semiconductor surface
The entire potential drop for
V
GB
<
V
FB
falls across the oxide:
Oxide Field and Potential:
OX FB GB
OX GB B
V V V
V
V
ox ox OX
Et V
Semiconductor Accumulation Charge:
ox
P
Q
G
Q
ox ox P
EQ
ox
ox ox OX P OX GB FB
ox
PoxGBFB
t
Et V Q V V V
QCVV
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
FB GB
V
V
+-
A Biased NMOS Capacitor: Accumulation (V
GB
< V
FB
)
ox
s
x
0
o
x
t
p
Potential:
GB B
V
x
0
o
x
t
FB GB ox
P
V
V
C
Q
Total charge per unit area in the hole accumulation layer
FB GB ox G
V
V
C
Q
Charge accumulation (due to holes) on the
semiconductor surface
Charge Density:
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Charges
GB
V
B
Q
Depletion Region
Charge (C/cm
2
)
FB
V
GB
V
P
Q
FB
V
Accumulation Layer Charge (C/cm
2
)
GB B
a
s
ox
s
ox
s
d
V
qN C C
x
2
2
da B
x
qN
Q
FB GB ox
P
V
V
C
Q
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
0
GB
V
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
-- do
x
A Biased NMOS Capacitor: V
GB
>0
ox
s
x
0
o
x
t
p
d
x
All of the applied bias falls across the depletion region and t he oxide
GB B
V
do
x
d
x
s
da
ox
da
S OX GB Bx qN
C
x qN
V
V
V
2
2
B
Potential drop
in the oxide
Potential drop in
the semiconductor
-----
The depletion region widens
and the oxide field increases
with
V
GB
for
V
GB
>
V
FB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
d
x
ox
s
ox
p s a s
p s FB GB
s
da
ox
da
FB GB
C
qN
V V
x qN
C
x qN
V
V
2
2
2
GB B
V
x
0
o
x
t
p
d
x
s
da
p Sx qN
x
2
0
2
A Biased NMOS Capacitor: Depletion (V
GB
> V
FB
)
FB GB
V
V
Surface potential
s
Potential drop
in the oxide
Potential drop in
the semiconductor
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Surface Potential
GB
V
s
FB
V
p
ox
p s a s
p s FB GB
C
qN
V V
2
GB FB
V
V
p s
FB GB
V
V
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor
x
0
o
x
t
SiO
2
P-Si Gate
+-
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
d
x
ox
s
FB GB
V
V
ox
p s a s
p s FB GB
C
qN
V V
2
s
da
ox
da
FB GBx qN
C
x qN
V V
2
2
S
OX FB GB
V
V
V
V
Same equation written
in 3 different ways
valid for:
T
N
GB FB
V
V
V
V
OX
V
S
V
OX
V
S
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Electron Density (V
GB
> V
FB
)
• As
V
GB
is increased,
S
also increases
• The electron density in the semiconductor depends on the potential as:
ox
p s a s
p s FB GB
C
qN
V V
2
GB B
V
x
0
o
x
t
p
d
x
S
x
0
KT
x q
a
KT
x q
KT
q
i
KT
x q
i
p p p
eN e en en xn
Electron density is the largest right at the surface of the sem iconductor where
the potential is the highest
KT
q
a
p s
eN xn
0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Threshold Condition
GB B
V
x
0
o
x
t
p
d
x
p S
x
0
• When
V
GB
is increased and the surface potential
S
reaches
-
p
the electron
density at the surface becomes comparable to the hole density in the substrate and
cannot be ignored
• The gate voltage V
GB
at which
S
equals
-
p
is called the threshold voltage
V
TN
:
ox
p a s
p FB TN
C
qN
V
V
2 2
2
KT
q
a
p s
eN xn
0
When:
a
KT
q
a
N eN xn
p s
0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion (V
GB
> V
TN
)
x
0
o
x
t
SiO
2
P-Si Gate
TN GB
V
V
+-
ox
s
Inversion layer charge (due to electrons)
on the semiconductor surface
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
d
x
x
0
o
x
t
a
qN
N da
G
Q
x
qN
Q
d
x
N
Q
• When the gate voltage
V
GB
is increased above
V
TN
the electron density right at
the surface increases (exponentially with the surface potential
S
)
• This surface electron density is called the inversion layer (assumed to be of zero
thickness in this course)
Inversion layer charge density (C/cm
2
)
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
GB B
V
x
0
o
x
t
p
max
d
x
p S
x
0
T
N
B
V
• When the gate voltage
V
GB
is increased above
V
TN
the inversion layer charge
increases so rapidly that the extra applied potential drops ent irely across the oxide, and
the surface potential
S
remains close to -
p
• Consequently, the depletion region thickness (and the depletion region charge) does
not increase when the gate voltage
V
GB
is increased above
V
TN
A Biased NMOS Capacitor: Inversion (V
GB
> V
TN
)
s
da
p
s
da
p S
x qN x qN
2
2
2
2
max
2
s
da
ox
da
FB TN
x qN
C
x qN
V V
2
2
max max
ox
p a s
p FB TN
C
qN
V
V
2 2
2
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Surface Potential
ox
p s a s
p s FB GB
C
qN
V V
2
GB
V
s
FB
V
TN
V
p
p
T
N
GB FB
V
V
V
p s
p s
FB GB
V
V
TN GB
V
V
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si Gate
TN GB
V
V
+-
ox
s
Q
N
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
max
d
x
A Biased NMOS Capacitor: Inversion (V
GB
> V
TN
)
How to calculate the inversion layer charge
Q
N
when
V
GB
>
V
TN
?
Start from:
s
da
ox ox
S ox FB GB
x qN
t E
V V V
V
2
2
max
s
da
S
x qN
V
2
2
max
By Gauss’ law:
max
da N ox oxx
qN
Q
E
TN GB ox N
TN
ox
N
GB
s
da
ox
da
ox
N
FB GB
V V C Q
V
C
Q
V
x qN
C
x qN
C
Q
V
V
2
2
max max
Therefore:
Inversion layer charge increases linearly with
the gate voltage above threshold
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Charges
GB
V
da B
x
qN
Q
Depletion Region
Charge (C/cm
2
)
FB
V
T
N
V
Inversion Layer Charge (C/cm
2
)
GB
V
N
Q
FB
V
TN
V
GB
V
P
Q
FB
V
TN
V
Accumulation Layer Charge (C/cm
2
)
TN GB ox N
V
V
C
Q
FB GB ox
P
V
V
C
Q
B
Q
max Bad
QqNx
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A N-MOS (or NMOS) Capacitor Structure
SiO
2
P-Si Substrate (or Bulk)
N+ Si Gate or Metal Gate
Gate metal
contact
Metal contact
GB
V
+
_
x
0
x
Doping:
N
a
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Charges
GB
V
G
Q
Gate Charge (C/cm
2
)
(Must be equal and opposite
to the total semiconductor
charge)
FB
V
T
N
V
Capacitance of a NMOS Capacitor:
GB
G
dV
dQ
C
C
V
GB
V
TN
V
FB
ox
C
ox
C
Accumulation
Depletion
Inversion
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of aNMOS Capacitor
(1) Accumulation (
V
GB
<
V
FB
):
• The small signal capacitance (per unit area) of the MOS capacitor is defined
as:
where
Q
G
is the charge density (units: C/cm
2
) on the gate
GB
G
dV
dQ
C
ox
FB GB ox G
C C
V
V
C
Q
o
x
C
gb
v
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
(2) Depletion (
V
TN
>
V
GB
>
V
FB
):
GB
d
a
GB
G
da G
dV
dx
qN
dV
dQ
C
x qN Q
FB GB
ox
da
s
da
V V
C
x qN x qN
2
2
Differentiate the equation (derived earlier):
The Small Signal Capacitance of aNMOS Capacitor
GB d a
ox s
d
dV dx qN
C
x
1
To get:
d
s
b
x
C
Define:
b ox
C C C
1 1 1
Finally:
o
x
C
gb
v
b
C
GB B
a
s
ox
s
ox
s
d
V
qN C C
x
2
2
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of aNMOS Capacitor
(3) Inversion (
V
GB
> V
TN
):
ox
GB
N
GB
G
N da G
C
dV
dQ
dV
dQ
C
Q
x
qN
Q
max
T
N
GB o
x
N
V
V
C
Q
x
dmax
does not change with V
GB
above threshold
o
x
C
gb
v
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of aNMOS Capacitor
C
V
GB
V
TN
V
FB
o
x
C
ox
C
Accumulation
Depletion
Inversion
P-Si
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A NMOS Capacitor with a Channel Contact
P-Si Substrate (or Bulk)
Gate
Gate metal
contact
Metal contact
GB
V
+ _
N-Si
CB
V
+
_
Inversion layer
N-Si
• In the presence of an inversion layer, the additional contact s allow one to directly
change the potential of the inversion layer channel w.r.t. to t he bulk (substrate)
SiO
2
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
GB B
V
x
0
o
x
t
p
max
d
x
p S
x
0
• We had said that the surface potential
S
remains fixed at
–
p
when
V
GB
is
increased beyond
V
TN
• But with a non-zero
V
CB
, the surface potential
S
in inversion can be changed to
(–
p
+
V
CB
)
• The new value of the depletion region width is:
Question: How do we now find the inversion layer charge
Q
N
when
V
CB
is not zero?
CB p S
V
x
0
)0 (
max
CB d
V
x
s
da
CB p
s
da
p S
x qN
V
x qN
2
2
2
2
max
2
A Biased NMOS Capacitor: Inversion with V
CB
≠0
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Surface Potential
ox
p s a s
p s FB GB
C
qN
V V
2
GB
V
s
FB
V
p
p
T
N
GB FB
V
V
V
CB p s
V
p s
FB GB
V
V
TN GB
V
V
CB p
V
CB
V
T
N
V
gate
GB
V
+
-
CB
V
+
-
source
drain
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si GateGB
V
+-
ox
s
Q
N
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
max
d
x
A Biased NMOS Capacitor: Inversion with V
CB
≠0 CB
V
+-
How to calculate the inversion layer charge
Q
N
? Same way as before……..
Start from:
s
da
ox ox
S ox FB GB
x qN
t E
V V V
V
2
2
max
s
da
S
x qN
V
2
2
max
By Gauss’ law:
max
da N o
x
o
x
x
qN
Q
E
s
da
ox
da
FB
ox
N
GB
s
da
ox
da
ox
N
FB GB
x qN
C
x qN
V
C
Q
V
x qN
C
x qN
C
Q
V
V
2
2
2
max max
2
max max
Therefore:
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
P-Si GateGB
V
+-
ox
s
Q
N
-
-
-
-
-
-
-
-
-
-
-
-
---
-
-
-
-
-
-
-
-
--
max
d
x
A Biased NMOS Capacitor: Inversion with V
CB
≠0 CB
V
+-
s
da
ox
da
FB
ox
N
GB
x qN
C
x qN
V
C
Q
V
2
2
max max
s
da
ox
da
FB TN
x qN
C
x qN
V
V
2
2
max max
ox
CB p a s
CB p FB
C
V qN
V V
2 2
2
TN GB ox N
V
V
C
Q
Same as before but now
V
TN
depends on
V
CB
ECE 315 – Spring 2005 – Farhan Rana – Cornell University
gate
gate
GB
V
+
-
GB
V
+
-
CB
V
+
-
gate
GB
V
+
-
CB
V
+
-
NMOS Capacitor: Effect of V
CB
(V
GB
> V
TN
)
V
CB
>0
• Inversion charge decreases
• Depletion region expands
V
CB
<0
• Inversion charge increases
• Depletion region shrinks
sourcedrain
sourcedrain source
drain
ECE 315 – Spring 2005 – Farhan Rana – Cornell University