Lecture8b_PMOS_FET_Semiconductor_Devices.pdf

PMOS FET Semiconductor Devices

1. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Lecture 8
MOS (Metal Oxide Semiconductor) Structures
In this lecture you will learn:
• The fundamental set of equations governing the behavior of PMOS
capacitors
• Accumulation, Flatband, Depletion, and Inversion Regimes
• Small signal models of the PMOS capacitor

2. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
MOS (Metal Oxide Semiconductor Field Effect Transistors (FETs)
100 nm
A 173 nm gate length MOS transistor
(INTEL)
GaAs (Substrate)
Source
AlGaAs
Drain
Gate
InGaAs (Quantum Well)
MOS FET
High Electron Mobility FET
22 nm gate length MOS transistors
(INTEL)

3. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A P-MOS (or PMOS) Capacitor
SiO
2
N-Si Substrate (or Bulk)
P+ Si Gate or Metal Gate
Gate metal
contact
Metal contact
GB
V
+
_
x
0
x
Doping:
N
d

4. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor
x
0
o
x
t

SiO
2
N-Si P+ Si
or
Metal
Gate
Assumptions:
1) The potential in the metal gate is
If the gate is P+ Si then
2) The potential deep in the p-Si substrate is
3) The oxide (SiO
2
) is insulating (near zero conductivity; no free electrons and holes)
and is completely free of any charges
4) There cannot be any volume charge density inside the metal gate (it is very
conductive). But there can be a surface charge density on the surface of the metal
gate
5) Dielectric constants:
M

p M



p

o ox


9.3

o s


7.11

ox

s

Doping:
N
d

5. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium
x
0
o
x
t
SiO
2
N-Si Gate
x
0
o
x
t
Potential Plot:

x

n

M

Potential?
0

GB
V
+-
We need to find the potential in equilibrium everywhere
Doping:
N
d
B


n
M
B



 
0

B

Assume:

6. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Depletion Region
x
0
o
x
t

SiO
2
N-Si Gate
0

GB
V
+-
Step 2: Depletion region is created in the substrate and a surf ace or sheet charge
density on the metal gate
Step 1: Charges Flow
x
0
o
x
t

SiO
2
N-Si Gate
0

GB
V
+-
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
Negative surface charge density (C/cm
2
)
Positive depletion charge density (C/cm
3
)
do
x
d
qN


do d
G
x
qN
Q

Doping:
N
d
Doping:
N
d
Tunnel

7. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Charge Densities
x
0
o
x
t

Charge density plot:
d
qN
do d
G
x
qN
Q

Depletion region charge
density (C/cm
3
)
x
0
o
x
t

SiO
2
N-Si Gate
0

GB
V
+-
do
x
do
x
do d B
x
qN
Q

Total charge per unit area in
the semiconductor (C/cm
2
)
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++

8. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Electric field in the semiconductor:
A PMOS Capacitor in Equilibrium: Electric Field
 


do
s
d
x
do x
s
d
s
x
x x
qN
x E
x x E
qN
dx
dE
  
   

 

0
Linearly varying
x
0
o
x
t

do
x

x
E
x
0
o
x
t

SiO
2
N-Si Gate
0

GB
V
+-
do
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++

do
s
d
x
x
qN
x E

 0

9. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Some Electrostatics
Consider an interface between media of different dielectric constants:
1

2

1
E
2
E
Suppose you know , can you find ???
1
E
2
E
Use the principle:The product of the dielectric constant and the normal
component of the electric field on both sides of an interface a re related as
follows:
  
 
I
Q E E
1 1 2 2
 
• Note that is the electric field JUST to the left of the interface and is the
electric field JUST to right of the interface
1
E
2
E
Interface sheet
charge density

10. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
Electric field in the oxide:
A PMOS Capacitor in Equilibrium: Electric Field


ox
do d
x
x
ox
x
x qN
x E
x E
dx
dE



 
 
 constant
0
x
0
o
x
t

do
x

x
E






ox
ox
do d
s
do d
ox
E
x qN
xE
x qN
xE
xE xE
s
   
 
  


 


 
0
0
0 0
x
0
o
x
t

SiO
2
N-Si Gate
0

GB
V
+-
do
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++

11. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Potential


 


2
2
do
s
d
n
n do do
s
d
x
x x
qN
x
x x x x
qN
x E
dx
x d
  
    

 
 


Potential in the semiconductor:
x
0
o
x
t

n

do
x
x
0
o
x
t

SiO
2
N-Si Gate
0

GB
V
+-
do
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
Start integrating the field – beginning
from the substrate (bulk) – to find the
potential

12. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Potential


 

x
x qN x qN
x
x qN
x
x qN
x E
dx
x d
ox
do d
s
do d
n
s
do d
n
ox
do d
x
 
 

 


  
    
2
2
0
2
2
Potential in the oxide:
x
0
o
x
t

n

do
x
x
0
o
x
t

SiO
2
N-Si Gate
0

GB
V
+-
do
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++

13. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Potential

M ox
ox
do d
s
do d
n ox
t
x qN x qN
t x

 
 
    
2
2
Must have:
Therefore:

B
d
s
ox
s
ox
s
do
qN C C
x

  


















 
2
2
ox
ox
ox
t
C


Oxide capacitance
(per unit area)
n
M
B



 
x
0
o
x
t
SiO
2
N-Si Gate
0
GB
V
+-
do
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
x
0
o
x
t
n

M

do
x
B


14. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor in Equilibrium: Potential
s
do d
ox
do d
B
S ox ox S ox Bx qN
C
x qN
V t E V V



2
2
  
    
ox
ox
ox
t
C


Oxide capacitance
(per unit area)
Potential drop in the oxide
Potential drop in
the semiconductor
x
0
o
x
t
SiO
2
N-Si Gate
0
GB
V
+-
do
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
x
0
o
x
t
n

M

do
x
B

n
M
B



 
ox
do d
ox
x qN
E



15. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: V
GB
> 0
x
0
o
x
t
n

d
x
All of the applied bias falls across the depletion region and t he oxide
GB B
V


do
x
s
d d
ox
d d
GB Bx qN
C
x qN
V


2
2
   
B
 Potential drop
in the oxide
Potential drop in
the semiconductor
x
0
o
x
t
SiO
2
N-Si Gate
0
GB
V
+-
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
do
x
ox

s


16. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: V
GB
>0
All of the applied bias falls across the depletion region and t he oxide

GB B
d
s
ox
s
ox
s
d
V
qN C C
x 

















 

  
2
2
ox
da
ox
x qN
E


The depletion region shrinks and the oxide field also decreases for
V
GB
> 0
x
0
o
x
t
SiO
2
N-Si Gate
0
GB
V
+-
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
do
x
ox

s

x
0
o
x
t
n

d
x
GB B
V


do
x

17. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
N-Si Gate
0
GB
V
+-
A Biased PMOS Capacitor: FlatbandCondition
ox

s

x
0
o
x
t
n

When
V
GB
is sufficiently positive, the depletion region thickness shrink s to zero
This value of
V
GB
is called the flatband voltage
V
FB


n
M
B FB
FB B
d
s
ox
s
ox
s
d
V
V
qN C C
x
  

  
   
  

















 0
2
2
Flatband voltage:
Potential in flatband
condition:

18. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
x
0
o
x
t
SiO
2
N-Si Gate
FB GB
V
V

+-
A Biased PMOS Capacitor: Accumulation (V
GB
> V
FB
)
ox

s

x
0
o
x
t
n

Potential:
GB B
V


x
0
o
x
t


FB GB o
x
N
V
V
C
Q
 
Total charge per unit area in the electron
accumulation layer


FB GB ox G
V
V
C
Q
 
Charge accumulation (due to electrons) on
the semiconductor surface
The entire potential drop for
V
GB
>
V
FB
falls across the oxide
Charge Density:

19. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Depletion (V
GB
< V
FB
)
s
d d
ox
d d
FB GB
S ox GB Bx qN
C
x qN
V
V
V V V


2
2
  
   
Potential drop
in the oxide
Potential drop in
the semiconductor
The depletion region widens
and the oxide field also
increases for
V
GB
<
V
FB
x
0
o
x
t
SiO
2
N-Si Gate
FB GB
V
V

+-
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
ox

s

x
0
o
x
t
n

d
x
GB B
V



20. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
 ox
n s d s
n s FB GB
s
d d
ox
d d
FB GB
C
qN
V V
x qN
C
x qN
V
V
  
 

 
    
  
2
2
2
A Biased PMOS Capacitor: Depletion (V
GB
< V
FB
)

s
d d
n Sx qN
x

  
2
0
2
   
x
0
o
x
t
SiO
2
N-Si Gate
FB GB
V
V

+-
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
ox

s

x
0
o
x
t
n

d
x
GB B
V



21. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Hole Density
• As
V
GB
is decreased,

S
also decreases
• The hole density in the semiconductor depends on the potential as:

ox
n s d s
n s FB GB
C
qN
V
V
  
 
 
   
2


 
 KT
x q
d
KT
x q
KT
q
i
KT
x q
i
n n n
eN e en en xp






   

  
Hole density is the largest right at the surface of the semicon ductor where the
potential is the lowest


KT
q
d
n s
eN xp


 
 0


S
x


 0
x
0
o
x
t
n

d
x
GB B
V



22. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Threshold Condition
GB B
V


x
0
o
x
t
n

d
x


n
S
x



  
0
• When
V
GB
is decreased and the surface potential

S
reaches
-
n
the positive hole
charge density at the surface becomes comparable to the positive charge density in
the depletion region and cannot be ignored
• The gate voltage at which

S
equals
-
n
is called the threshold voltage
V
TP
:

ox
n d s
n FB TP
C
qN
V
V
 

2 2
2
  


d
KT
q
d
N eN xp
n s
  
 


0

23. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Inversion (V
GB
< V
TP
)
Inversion layer charge (due to holes) on
the semiconductor surface
x
0
o
x
t

d
q
N

P
d d
G
Q
x
q
N
Q
 
d
x

P
Q
• When the gate voltage
V
GB
is decreased below
V
TP
the hole density right at the
surface increases (exponentially with the decrease in the surface potential

S
)
• This surface hole density is called the inversion layer (assumed to be of zero
thickness in this course)
Inversion layer charge density (C/cm
2
)
x
0
o
x
t

SiO
2
N-Si Gate
T
P
GB
V
V

+-
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
ox

s


24. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
GB B
V


x
0
o
x
t

n

max
d
x


n
S
x



  
0
TP B
V


• When the gate voltage
V
GB
is decreased below
V
TP
the inversion layer charge increases
so rapidly that the extra applied potential drops entirely acro ss the oxide, and the surface
potential

S
remains close to -

n
• Consequently, the depletion region thickness (and the depletion region charge) does
not increase when the gate voltage
V
GB
is decreased below
V
TP
A Biased PMOS Capacitor: Inversion (V
GB
< V
TP
)
s
d d
n
s
d d
n S
x qN x qN 


 
2
2
2
2
max
2
   
s
d d
ox
d d
FB TP
x qN
C
x qN
V V
2
2
max max
   

ox
n d s
n FB TP
C
qN
V
V
 

2 2
2
  

25. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion (V
GB
< V
TP
)
How to calculate the inversion layer charge
Q
P
when
V
GB
<
V
TP
?
Start from:
s
da
ox ox
S ox GB FB
x qN
t E
V V V
V

2

2
max
 
  
s
d d
S
x qN
V

2
2
max

By Gauss’ law:
max
d d
P
ox ox
x
qN
Q
E
  
 
TP GB ox P
TP
ox
P
GB
s
d d
ox
d d
ox
P
GB FB
V V C Q
V
C
Q
V
x qN
C
x qN
C
Q
V
V
  
  
   

2
2
max max
Therefore:
x
0
o
x
t
SiO
2
N-Si Gate
T
P
GB
V
V

+-
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
ox

s

Q
P

26. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Summary of Different Regimes
Flatband (
V
GB
=
V
FB
):
No depletion region in the semiconductor and no accumulation charge
Accumulation (
V
GB
>
V
FB
):
No depletion region in the semiconductor but majority carrier accumulation charge
on the surface of the semiconductor
Depletion (
V
TP
<
V
GB
<
V
FB
):
Depletion region in the semiconductor but no majority carrier accumulation charge
or minority carrier inversion charge on the surface of the semiconductor
Inversion (
V
GB
<
V
TP
):
Depletion region in the semiconductor and minority carrier inversion charge on the
surface of the semiconductor

27. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Charges
GB
V
B
Q
Depletion Region
Charge (C/cm
2
)
FB
V
T
P
V
Inversion Layer Charge (C/cm
2
)
GB
V
P
Q
FB
V
T
P
V





























   
FB GB
d
s
ox
s
ox
s
d d d B
V V
qN C C
qN x qN Q
  
2
2

n d s d d B
qN x qN Q
 
2 2
max
 
0
B
Q


TP GB o
x
P
V V
C
Q
 
0
N
Q
0
N
Q

28. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased PMOS Capacitor: Charges
GB
V
G
Q
Gate Charge
(C/cm
2
)
FB
V
T
P
V
GB
V
N
Q
FB
V
T
P
V
Accumulation Layer Charge (C/cm
2
)


FB GB ox N
V V
C
Q
 
0
N
Q
0
N
Q
B
N
P
G
Q
Q
Q
Q
  

29. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of aPMOS Capacitor
(1) Accumulation (
V
GB
>
V
FB
):
• The small signal capacitance (per unit area) of the MOS capacitor is defined
as:
where
Q
G
is the charge density (units: C/cm
2
) on the gate
GB
G
dV
dQ
C


ox
FB GB ox G
C C
V
V
C
Q
 
 
o
x
C
gb
v

30. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
(2) Depletion (
V
TP
<
V
GB
<
V
FB
):
GB
d
d
GB
G
d d G
dV
dx
qN
dV
dQ
C
x qN Q
 

FB GB
ox
d d
s
d d
V V
C
x qN x qN
  

2
2
Differentiate the equation (derived earlier):
The Small Signal Capacitance of aPMOS Capacitor
GB d d
ox s
d
dV dx qN
C
x








1

To get:
d
s
b
x
C


Define:
b ox
C C C
1 1 1
 
Finally:
o
x
C
gb
v
b
C

31. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of aPMOS Capacitor
(3) Inversion (
V
GB
<
V
TP
):
ox
GB
P
GB
G
P d d G
C
dV
dQ
dV
dQ
C
Q
x
qN
Q

 
 
max


T
P
GB ox
P
V
V
C
Q
 
x
dmax
does not change with
V
GB
in inversion
o
x
C
gb
v

32. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
The Small Signal Capacitance of aPMOS Capacitor
C
V
GB
V
TP
V
FB
ox
C
ox
C
Accumulation
Depletion
Inversion
Gate Charge
(C/cm
2
)
GB
V
G
Q
FB
V
T
P
V
GB
G
dV
dQ
C

33. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A PMOS Capacitor with a Channel Contact
N-Si Substrate (or Bulk)
Gate
Gate metal
contact
Metal contact
GB
V
+
_
CB
V
+
_
Inversion layer
P-Si
• In the presence of an inversion layer, the additional contact s allow one to directly
change the potential of the inversion layer channel w.r.t. to t he bulk (substrate)
SiO
2
P-Si

34. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
GB B
V


x
0
o
x
t
n

max d
x


n
S
x



  
0
• We had said that the surface potential

S
remains fixed at
–

n
when
V
GB
is
decreased below
V
TP
• But with a non-zero
V
CB
, the surface potential

S
in inversion can be changed to
(–

n
+
V
CB
)
• The new value of the depletion region width is:
Question: How do we now find the inversion layer charge
Q
P
when
V
CB
is not zero?


CB n
S
V
x
   



0
)0 (
max

CB d
V
x
s
d d
CB n
s
d d
n s
x qN
V
x qN 


 
2
2
2
2
max
2
    
A Biased PMOS Capacitor: Inversion with V
CB
≠0

35. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion with V
CB
≠0 CB
V
+-
How to calculate the inversion layer charge
Q
P
? Same way as before……..
Start from:
s
d d
ox ox
S ox GB FB
x qN
t E
V V V
V

2

2
max
 
  
s
da
S
x qN
V

2
2
max

By Gauss’ law:
max
d d
P
ox ox
x
qN
Q
E
  

s
d d
ox
d d
FB
ox
P
GB
s
d d
ox
d d
ox
P
GB FB
x qN
C
x qN
V
C
Q
V
x qN
C
x qN
C
Q
V
V


2
2
2
max max
2
max max
   
   
Therefore:
x
0
o
x
t
SiO
2
N-Si Gate
T
P
GB
V
V

+-
max
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
ox

s

Q
P

36. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
A Biased NMOS Capacitor: Inversion with V
CB
≠0
s
da
ox
da
FB
ox
P
GB
x qN
C
x qN
V
C
Q
V

2
2
max max
   
s
d d
ox
d d
FB TP
x qN
C
x qN
V
V

2
2
max max
  

ox
CB n d s
CB n FB
C
V qN
V V

   
 

2 2
2


T
P
GB ox
P
V
V
C
Q
  
Same as before but now
V
TP
depends on
V
CB
CB
V
+-
x
0
o
x
t
SiO
2
N-Si Gate
T
P
GB
V
V

+-
max
d
x
+
+
+
+
+
+
+
+
+
+
+
+
+++
+
+
+
+
+
+
+
+
++
ox

s

Q
P

37. ECE 315 – Spring 2005 – Farhan Rana – Cornell University
gate
gate
GB
V
+
-
GB
V
+
-
CB
V
+
-
gate
GB
V
+
-
CB
V
+
-
V
CB
<0
• Inversion charge decreases
• Depletion region expands
V
CB
>0
• Inversion charge increases
• Depletion region shrinks
sourcedrain
sourcedrain source
drain
PMOS Capacitor: Effect of V
CB
(V
GB
< V
TP
)