logic.deghjkl;jldddghbmedgygshedgyssfjfheueh
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Jun 29, 2024
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About This Presentation
logic
Slide Content
Logic
Sheet #3 Dr. EMAN
Sheet #3 Dr. EMAN
Contents
Logic Implementation from specifications
Logic Implementation using Construction Design: Adders
Logic Implementation Using Decoders
Logic Implementation Using MultiplexersCombinational
Circuit
OutputsInputs
Logic Implementation from specifications
Logic Implementation using Construction Design: Adders
Logic Implementation Using Decoders
Logic Implementation Using MultiplexersCombinational
Circuit
OutputsInputs
This is the Default Solution
Construct The Truth Table
K-map for each output
Implement the Simplified Equations
Any Gates
NAND ONLY
NOR ONLY
Logic Gates
Adders
Multiplexer
Implement Using Pre-Designed Blocks
Decoder
Implement by
Construction
Specifications Logic Implementation from specifications
Construct The Truth Table
K-map for each output
Implement the Simplified Equations
Any Gates
NAND ONLY
NOR ONLY
Logic Gates
Adders
Multiplexer
Implement Using Pre-Designed Blocks
Decoder
Implement by
Construction
Specifications Logic Implementation from specifications
Problem 3
Design a combinational circuit with three inputs and one output. The output is
1 when the value of the inputs is less than 3. The output is 0 otherwise.
DecXYZF
00001
10011
20101
30110
41000
51010
61100
71110
??????= � � + � �
11 1
00 01 11 10
0
0 1 3 2
1 4 5 7 6
Y
Z
XY Z
F
X
Design a combinational circuit with three inputs and one output. The output is
1 when the value of the inputs is less than 3. The output is 0 otherwise.
DecXYZF
00001
10011
20101
30110
41000
51010
61100
71110
??????= � � + � �
11 1
00 01 11 10
0
0 1 3 2
1 4 5 7 6
Y
Z
XY Z
F
X
00 01 11 10
0
0 1 3 2
1 4 5 7 6
Problem 4
Design a combinational circuit with three inputs and one output. The output is
1 when the value of the inputs is even. The output is 0 otherwise.
DecXYZF
00001
10010
20101
30110
41001
51010
61101
71110
??????= �
1
1 1
Y
Z
X 1Z F
0
0 1 3 2
1 4 5 7 6
Problem 4
Design a combinational circuit with three inputs and one output. The output is
1 when the value of the inputs is even. The output is 0 otherwise.
DecXYZF
00001
10010
20101
30110
41001
51010
61101
71110
??????= �
1
1 1
Y
Z
X 1Z F
Design a combinational circuit with three inputs, x, y, z, and three outputs, A, B,
and C. When the binary input is 0, 1, 2, or 3, the binary output is two greater
than the input. When the binary input is 4, 5, 6, or 7, the binary output is three
less than the input.
Problem 5
DecXYZABC
0000010
1001011
2010100
3011101
4100001
5101010
6110011
7111100
A= Σ(2,3,7)
B= Σ(0,1,5,6)
C= Σ(1,3,4,6)
and C. When the binary input is 0, 1, 2, or 3, the binary output is two greater
than the input. When the binary input is 4, 5, 6, or 7, the binary output is three
less than the input.
Problem 5
DecXYZABC
0000010
1001011
2010100
3011101
4100001
5101010
6110011
7111100
A= Σ(2,3,7)
B= Σ(0,1,5,6)
C= Σ(1,3,4,6)
0 1
00
0 1
01
2 3
11
6 7
10
4 5
C= X Z+X Z
1
1
XY
Z
Z
Y
X
1
C= Σ(1,3,4,6)
0 1
00
0 1
01
2 3
11
6 7
10
4 5
B= X Y + Y Z+X Y Z
11
XY
Z
Z
Y
X
1
B= Σ(0,1,5,6)
0 1
00
0 1
01
2 3
11
6 7
10
4 5
A= X Y+Z Y
1
1
XY
Z
Z
Y
X
1
A= Σ(2,3,7)
1
1
00
0 1
01
2 3
11
6 7
10
4 5
C= X Z+X Z
1
1
XY
Z
Z
Y
X
1
C= Σ(1,3,4,6)
0 1
00
0 1
01
2 3
11
6 7
10
4 5
B= X Y + Y Z+X Y Z
11
XY
Z
Z
Y
X
1
B= Σ(0,1,5,6)
0 1
00
0 1
01
2 3
11
6 7
10
4 5
A= X Y+Z Y
1
1
XY
Z
Z
Y
X
1
A= Σ(2,3,7)
1
1
Y Z
B
X
A
C C= X Z+X Z
B= X Y + Y Z+X Y Z
A= X Y+Z Y
B
X
A
C C= X Z+X Z
B= X Y + Y Z+X Y Z
A= X Y+Z Y
Example
Design a 3-bits squarer circuit (b2b1b0)
2
Decb2b1b0S5S4S3S2S1S0
0000000000
1001000001
2010000100
3011001001
4100010000
5101011001
6110100100
7111110001
S0= Σ(1,3,5,7)
S1= 0
S2= Σ(2,6)
S3= Σ(3,5)
S4= Σ(4,5)
S5= Σ(6,7)
Design a 3-bits squarer circuit (b2b1b0)
2
Decb2b1b0S5S4S3S2S1S0
0000000000
1001000001
2010000100
3011001001
4100010000
5101011001
6110100100
7111110001
S0= Σ(1,3,5,7)
S1= 0
S2= Σ(2,6)
S3= Σ(3,5)
S4= Σ(4,5)
S5= Σ(6,7)
0 1
00
0 1
01
2 3
11
6 7
10
4 5
b2b1
b0
b0
b1
b2
11
0 1
00
0 1
01
2 3
11
6 7
10
4 5
1
b2b1
b0
b0
b1
b2
1
0 1
00
0 1
01
2 3
11
6 7
10
4 5
b2b1
b0
b0
b1
b2
1
1
0 1
00
0 1
01
2 3
11
6 7
10
4 5
1
1
b2b1
b0
b0
b1
b2
1
1
0 1
00
0 1
01
2 3
11
6 7
10
4 5
b2b1
b0
b0
b1
b2
S0= Σ(1,3,5,7)
S1= 0
S2= Σ(2,6)
S3= Σ(3,5)
S4= Σ(4,5)
S2= Σ(6,7)
S0= b0
S1= 0
S2= b1 b0’
S3= b2’ b1 b0 + b2 b1’ b0
S4= b2 b1’
S2= b2 b1
S0
11
S2 S3 S4
S5
00
0 1
01
2 3
11
6 7
10
4 5
b2b1
b0
b0
b1
b2
11
0 1
00
0 1
01
2 3
11
6 7
10
4 5
1
b2b1
b0
b0
b1
b2
1
0 1
00
0 1
01
2 3
11
6 7
10
4 5
b2b1
b0
b0
b1
b2
1
1
0 1
00
0 1
01
2 3
11
6 7
10
4 5
1
1
b2b1
b0
b0
b1
b2
1
1
0 1
00
0 1
01
2 3
11
6 7
10
4 5
b2b1
b0
b0
b1
b2
S0= Σ(1,3,5,7)
S1= 0
S2= Σ(2,6)
S3= Σ(3,5)
S4= Σ(4,5)
S2= Σ(6,7)
S0= b0
S1= 0
S2= b1 b0’
S3= b2’ b1 b0 + b2 b1’ b0
S4= b2 b1’
S2= b2 b1
S0
11
S2 S3 S4
S5
b1b0
S3
b2
S0
S1
S2
S4
S5 S0= b0
S1= 0
S2= b1 b0’
S3= b2’ b1 b0 + b2 b1’ b0
S4= b2 b1’
S2= b2 b1
S3
b2
S0
S1
S2
S4
S5 S0= b0
S1= 0
S2= b1 b0’
S3= b2’ b1 b0 + b2 b1’ b0
S4= b2 b1’
S2= b2 b1
Kindly note
In this section, we concentrated only on the
function and usage of the most important blocks.
Therefore, you need to study from the slides each
block details and any other unmentioned blocks.
In this section, we concentrated only on the
function and usage of the most important blocks.
Therefore, you need to study from the slides each
block details and any other unmentioned blocks.
ADDERS
Adders(Half-Adder)
DecABCoS
00000
10101
21001
31110
S=A ⨁ B
C = A BC
S
B
A
DecABCoS
00000
10101
21001
31110
S=A ⨁ B
C = A BC
S
B
A
Adders(Full-Adder)
DecCiABCoS
000000
100101
201001
301110
410001
510110
611010
711111
011
11A1011
3B0011
14S1110
Full-Adder
Get the Equations &
Implement as in the Dr.’s Slides
DecCiABCoS
000000
100101
201001
301110
410001
510110
611010
711111
011
11A1011
3B0011
14S1110
Full-Adder
Get the Equations &
Implement as in the Dr.’s Slides
Example
Design a 4-bit combinational circuit incrementor ( A circuit that adds one to
a 4-bit binary number). The circuit can be designed using four half-adders. BA
Co
S
Half-Adder
A0
S0
Vs
(Logic1)
BA
Co
S
Half-Adder
A1
S1
BA
Co
S
Half-Adder
A2
S2
BA
Co
S
Half-Adder
A3
S3
Cout
Co2Co1Co0
AA3A2A1A0
10001
A+11110
Design a 4-bit combinational circuit incrementor ( A circuit that adds one to
a 4-bit binary number). The circuit can be designed using four half-adders. BA
Co
S
Half-Adder
A0
S0
Vs
(Logic1)
BA
Co
S
Half-Adder
A1
S1
BA
Co
S
Half-Adder
A2
S2
BA
Co
S
Half-Adder
A3
S3
Cout
Co2Co1Co0
AA3A2A1A0
10001
A+11110
Example
Designacombinationalcircuitusingaminimumnumberoffulladdersto
decrementa4-bitnumberby2.Assume6-bitresult.Drawalogicdiagram
usingtheblockdiagramofafulladderasthebuildingblock.
Designacombinationalcircuitusingaminimumnumberoffulladdersto
decrementa4-bitnumberby2.Assume6-bitresult.Drawalogicdiagram
usingtheblockdiagramofafulladderasthebuildingblock.
Example
Designacombinationalcircuitusingfulladderstomultiplya4-bit
unsignednumberby2.Drawalogicdiagramusingtheblockdiagramofa
fulladderasthebuildingblock.
Designacombinationalcircuitusingfulladderstomultiplya4-bit
unsignednumberby2.Drawalogicdiagramusingtheblockdiagramofa
fulladderasthebuildingblock.
Problem 6
Theadder–subtractorcircuitdescribedatthelecturehasthefollowingvalues
formodeinputManddatainputsAandB.MAB
(a)001110110
(b)010001001
(c)111001000
(d)101011010
(e)100000001
Ineachcase,determinethevaluesofthefourSUMoutputs,andthecarryC
Theadder–subtractorcircuitdescribedatthelecturehasthefollowingvalues
formodeinputManddatainputsAandB.MAB
(a)001110110
(b)010001001
(c)111001000
(d)101011010
(e)100000001
Ineachcase,determinethevaluesofthefourSUMoutputs,andthecarryC
0 0111 0110
Binary Multiplier 2X2
4x4 Magnitude Comparator
DECODERS
Decoder
•A (m x 2
m
) decoder is a combinational circuit that decodes m bit binary
inputs into 2
m
output line.
•Each output line is numbered with a decimal number.
•When the input code has the same decimal number as an output line; the
output line is set to logic one and other outputs are reset to zero.
•A (m x 2
m
) decoder is a combinational circuit that decodes m bit binary
inputs into 2
m
output line.
•Each output line is numbered with a decimal number.
•When the input code has the same decimal number as an output line; the
output line is set to logic one and other outputs are reset to zero.
DecABCD0D1D2D3D4D5D6D7
000010000000
100101000000
201000100000
301100010000
410000001000
510100000100
611000000010
711100000001
Made Basically From AND gates + Inverters
000010000000
100101000000
201000100000
301100010000
410000001000
510100000100
611000000010
711100000001
Made Basically From AND gates + Inverters
DecABCD0D1D2D3D4D5D6D7
000001111111
100110111111
201011011111
301111101111
410011110111
510111111011
611011111101
711111111110
Made Basically From NAND gates + Inverters
000001111111
100110111111
201011011111
301111101111
410011110111
510111111011
611011111101
711111111110
Made Basically From NAND gates + Inverters
Obtain the Outputs’ minterms
Use (#inputs x 2
#inputs
) active high Decoder
For Each output One OR gate is Needed
According to the minterms, the inputs of each
OR gate are taken from the decoder’s output
1
2
3
4
Logic Implementation Using Active High
Decoders (The Default)
Use (#inputs x 2
#inputs
) active high Decoder
For Each output One OR gate is Needed
According to the minterms, the inputs of each
OR gate are taken from the decoder’s output
1
2
3
4
Logic Implementation Using Active High
Decoders (The Default)
Obtain the Outputs’ minterms
Use (#inputs x 2
#inputs
) active low Decoder
For Each output One NAND gate is Needed
According to the minterms, the inputs of each
NAND gate are taken from the decoder’s output
1
2
3
4
Logic Implementation Using Active Low
decoders
Use (#inputs x 2
#inputs
) active low Decoder
For Each output One NAND gate is Needed
According to the minterms, the inputs of each
NAND gate are taken from the decoder’s output
1
2
3
4
Logic Implementation Using Active Low
decoders
A
B
0
3
2
1
2x4
Decoder
F Logic Implementation Using Decoders
DecABF
0000
1011
2101
3110
1
0
10
0
1
01
11
00
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
B
0
3
2
1
2x4
Decoder
F Logic Implementation Using Decoders
DecABF
0000
1011
2101
3110
1
0
10
0
1
01
11
00
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
0
Problem7
A combinational circuit is specified by the following three Boolean
functions:
F1(A, B, C) = ∑(1, 4, 6)
F2(A, B, C) = ∑ (3, 5)
F3(A, B, C) = ∑ (2, 4, 6, 7)
Implement the circuit with a decoder constructed with AND gates
and OR gatesconnected to the decoder outputs.
A combinational circuit is specified by the following three Boolean
functions:
F1(A, B, C) = ∑(1, 4, 6)
F2(A, B, C) = ∑ (3, 5)
F3(A, B, C) = ∑ (2, 4, 6, 7)
Implement the circuit with a decoder constructed with AND gates
and OR gatesconnected to the decoder outputs.
A
B
C
3x8
Decoder
0
7
6
5
4
3
2
1
F1 F3F2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 F1(A,B,C) = Σ (1,4,6)
F2(A,B,C) = Σ (3,5)
F3(A,B,C) = Σ (2, 4, 6, 7)
B
C
3x8
Decoder
0
7
6
5
4
3
2
1
F1 F3F2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 F1(A,B,C) = Σ (1,4,6)
F2(A,B,C) = Σ (3,5)
F3(A,B,C) = Σ (2, 4, 6, 7)
Example
A combinational circuit is specified by the following three Boolean
functions:
F1(A, B, C) = ∑(1, 4, 6)
F2(A, B, C) = ∑ (3, 5)
F3(A, B, C) = ∑ (2, 4, 6, 7)
Implement the circuit with a decoder constructed with NAND
gates and ANDgatesconnected to the decoder outputs.
A combinational circuit is specified by the following three Boolean
functions:
F1(A, B, C) = ∑(1, 4, 6)
F2(A, B, C) = ∑ (3, 5)
F3(A, B, C) = ∑ (2, 4, 6, 7)
Implement the circuit with a decoder constructed with NAND
gates and ANDgatesconnected to the decoder outputs.
F1(A,B,C) = Σ (1,4,6)
F2(A,B,C) = Σ (3,5)
F3(A,B,C) = Σ (2, 4, 6, 7)A
B
C
3x8
Decoder
0
7
6
5
4
3
2
1
F1 F3F2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
F2(A,B,C) = Σ (3,5)
F3(A,B,C) = Σ (2, 4, 6, 7)A
B
C
3x8
Decoder
0
7
6
5
4
3
2
1
F1 F3F2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Problem 8
Using a decoder and external gates, design the combinational circuit defined
by the following three Boolean functions
F1 = (Y’+X)Z
F2 = Y’Z’+XY’+YZ’
F3 = (X’+Y)Z
Using a decoder and external gates, design the combinational circuit defined
by the following three Boolean functions
F1 = (Y’+X)Z
F2 = Y’Z’+XY’+YZ’
F3 = (X’+Y)Z
EquationTerm XYZDE
C
-Y’Z
0011
F1
1015
X-Z
1015
1117
EquationTerm XYZDEC
-Y’Z’
0000
F2
1004
XY’-
1004
1015
-YZ’
0102
1106
EquationTerm XYZDE
C
-YZ
0113
F3
1117
X’-Z
0011
0113
F1 = Σ(1,5,7)
F2 = Σ(0,2,4,5,6)
F3 = Σ(1,3,7) Z
Y
X
3x8
Decoder
0
7
6
5
4
3
2
1
F1 F2 F3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
2
0
2
1
2
2
C
-Y’Z
0011
F1
1015
X-Z
1015
1117
EquationTerm XYZDEC
-Y’Z’
0000
F2
1004
XY’-
1004
1015
-YZ’
0102
1106
EquationTerm XYZDE
C
-YZ
0113
F3
1117
X’-Z
0011
0113
F1 = Σ(1,5,7)
F2 = Σ(0,2,4,5,6)
F3 = Σ(1,3,7) Z
Y
X
3x8
Decoder
0
7
6
5
4
3
2
1
F1 F2 F3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
2
0
2
1
2
2
Example
ImplementaBCD-to-excess3codeconverterwitha4x10decoderandfour
NANDgates
D0
D1
4x 10
Dec
D2
D3
D4
D5
D6
D7
D8
D9
X1X2X3X4F1F2F3F4
000000011
100010100
200100101
300110110
401000111
501011000
601101001
701111010
810001011
910011100
ImplementaBCD-to-excess3codeconverterwitha4x10decoderandfour
NANDgates
D0
D1
4x 10
Dec
D2
D3
D4
D5
D6
D7
D8
D9
X1X2X3X4F1F2F3F4
000000011
100010100
200100101
300110110
401000111
501011000
601101001
701111010
810001011
910011100
MULTIPLEXER
Multiplexers
•A (2
m
x 1) Multiplexer is a combinational circuit that connect one of 2
m
inputs with the output line according to the value of m selection lines.
•Each input line is numbered with a decimal number.
•To connect the input line number (x)
10(say x=3) with the output, put on
the selection inputs the value of x in binary (011).
•A (2
m
x 1) Multiplexer is a combinational circuit that connect one of 2
m
inputs with the output line according to the value of m selection lines.
•Each input line is numbered with a decimal number.
•To connect the input line number (x)
10(say x=3) with the output, put on
the selection inputs the value of x in binary (011).
DecS2S1S0F
0000I0
1001I1
2010I2
3011I3
4100I4
5101I5
6110I6
7111I7S0
8x1
Mux
0
7
6
5
4
3
2
1
S1
F
S2
I0
I3
I4
I7
I1
I5
I6
I2
111
0000I0
1001I1
2010I2
3011I3
4100I4
5101I5
6110I6
7111I7S0
8x1
Mux
0
7
6
5
4
3
2
1
S1
F
S2
I0
I3
I4
I7
I1
I5
I6
I2
111
Logic Implementation Using Multiplexers
DecABF
0000
1011
2101
3110
1
1
0
0
1
0
10
0
1
01
11
00
DecABF
0000
1011
2101
3110
1
1
0
0
1
0
10
0
1
01
11
00
Question
ImplementthefunctionF(x1,x2,x3,x4)=Σ(0,1,3,4,8,9,15)withan8x1
multiplexerwherethefollowingvariablesareconnectedinthespecified
ordertoselectionliness2,s1,s0respectively:
ImplementthefunctionF(x1,x2,x3,x4)=Σ(0,1,3,4,8,9,15)withan8x1
multiplexerwherethefollowingvariablesareconnectedinthespecified
ordertoselectionliness2,s1,s0respectively:
I0
I1
I2
I3
I4
I5
I6
16 x 1
MUXI7
I8
I9
I10
I11
I12
I13
I14
I15
S3 S2 S1 S0
F(x1,x2,x3,x4) = Σ(0,1,3,4,8,9,15)
X1X2X3X4
F
I1
I2
I3
I4
I5
I6
16 x 1
MUXI7
I8
I9
I10
I11
I12
I13
I14
I15
S3 S2 S1 S0
F(x1,x2,x3,x4) = Σ(0,1,3,4,8,9,15)
X1X2X3X4
F
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F(x1,x2,x3,x4) =
Σ(0,1,3,4,8,9,15)
X1X2X3
X1X2X3X4F
000001
100011
200100
300111
401001
501010
601100
701110
810001
910011
1010100
1110110
1211000
1311010
1411100
1511111
1
000
001
X4
X4’
010
0
011
F
1
0
0
X4
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F(x1,x2,x3,x4) =
Σ(0,1,3,4,8,9,15)
X1X2X3
X1X2X3X4F
000001
100011
200100
300111
401001
501010
601100
701110
810001
910011
1010100
1110110
1211000
1311010
1411100
1511111
1
000
001
X4
X4’
010
0
011
F
1
0
0
X4
F(x1,x2,x3,x4)=Σ(0,1,3,4,8,9,15)Keep x1,x2,x3
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
X1X2X3
F
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
X1X2X3
F
Example
Use8x1MUXstoimplementthecombinationalcircuitwithoutput
functions:
F1(x1,x2,x3,x4)=Σ(2,4,10,11,12,13)
F2(x1,x2,x3,x4)=Σ(4,5,10,11,13)
F3(x1,x2,x3,x4)=Σ(1,2,3,10,11,12)
Use8x1MUXstoimplementthecombinationalcircuitwithoutput
functions:
F1(x1,x2,x3,x4)=Σ(2,4,10,11,12,13)
F2(x1,x2,x3,x4)=Σ(4,5,10,11,13)
F3(x1,x2,x3,x4)=Σ(1,2,3,10,11,12)
F1=Σ(2,4,10,11,12,13)
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
F2=Σ(4,5,10,11,13)
F3= Σ(1,2,3,10,11,12)
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
I0I1I2I3I4I5I6I7
X4’0 2 4 6 8 101214
X4 1 3 5 7 9 111315
F2=Σ(4,5,10,11,13)
F3= Σ(1,2,3,10,11,12)
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F1
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F2
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F3
X1X2X3X1X2X3X1X2X3
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F1
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F2
I0
I1
I2
8 x 1
MUXI3
I4
I5
I6
I7
S2 S1 S0
F3
X1X2X3X1X2X3X1X2X3
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