Low power and efficiency test pattern generator

Low power and efficiency test pattern generator

1. 8 7 6 5 4 3 2 1 contents Abstract Introduction Literature survey Block diagram Software tools Advantages Applications Reference

2. Abstract We are aware that during testing when the device’s normal functioning mode is off, the dissipation of power is approximately 200% more than that of normal functioning mode. In this project 32-bit test pattern generator has been proposed for testing the VLSI design. This 32-bit test pattern generator is implemented with efficient LFSR and with extra combinational circuitry which achieved Low power consumption. The switching activity between the tests vector are reduced, this results in low power consumption.

3. Introduction With the shrinking size of transistor, the complexity of the chips has also increased. The rise in the complexity has given way to the rise in power consumption. The basic principle behind testing methodology is as follows: These testing are being done keeping in mind the aim to minimize the stuck at faults. A circuit is most likely to be effected by stuck at faults. Each of the early approaches that had been adopted to achieve, these two objectives i.e. to Minimize power consumption Generate all set of patterns with minimum possible gates. Together with this the idea of low power consumption has also been obtained with less switching’s.

4. Literature survey Design and Implementation of Low Power Test Pattern Generator Using Low Transitions LFSR . Tejas Thubrikar, Sandeep Kakde, Shweta Gaidhani, Shailesh Kamble and Nikit Shah This paper shows an effective HDL implementation of low power utilization for test pattern generator using the Low Transistion LFSR technique. It also addresses a theory to express a test pattern creation by using Low Transition Linear Feedback Shift Register architecture.

5. An evolution of current microelectronics industry allows us to make complex digital systems on a single microchip. To design such a system is not an easy task anymore because the increasing density raises a whole set of different problems such as size speed power consumption of the chip.

6. From the previous papers ,we understood that Now -a-days the testing of VLSI circuits faces many challenges in terms of area , power , latency and efficiency. In previous papers for an 32-bit test pattern generation the power consumption and switching's are high to resolve this issue we are doing this project. To overcome this issues in our project we are generating the test patterns with low power and with less switching's.

7. Block diagram

8. The block diagram consists of : FSA Bipartite Upper d flip flop Lower d flip flop Dummy d flip flop Random injection circuit And gate Or gate multiplexer

9. FSA: fault sensitivity analysis Inputs: test enable Reset Clock Load seed Seed data Outputs: Clock 1(enable 1) Clock 2(enable 2) Selection line 1 Selection line 2 FSA is an control block which control the outputs FSA will work when reset is “0” and the test enable( Te ) is “1” The enable and selection line values are depended on the previous state We can take 2^n test patterns in maximum. If the state is at the last state then it again return to its initial state. if the reset is logic “1” then also the state in the initial state.

10. Bipartite: Inputs: Clock 1 Clock 2 Reset Outputs: 32 bit data Bipartite consists of combination of 16 bit upper d flip flop and 16 bit lower d flip flop with an dummy d flip flop. It consists of the EXOR gate which take the inputs from the lowest bit of lower d flip flop and the higher bit of the upper d flip flop Low power linear feedback shift register is known as the Bipartite The seed data must be other than the 0 and store the data in the upper and the lower d flip flops. Inputs Outputs A B Y 1 1 1 1 1 1 Inputs Output D Q 1 1 D flip flop Xor gate

11. Dummy flip flop Dummy ff is an single bit storage ff . Dummy ff is used to store states of last bit generated by upper d-ff in clk cycle. It stores n/2-1 d-ff data in it. This is used to send this into n/2 d-ff ,when 2nd half becomes working ,i.e clk1 = 0, clk2=1.

12. Working of design: Clk1 Clk2 UPPER LFSR LOWER LFSR Sel1 Sel2 output 1 Active Inactive 1 1 upper LFSR shifts with 1 bit. Inactive Inactive 1 RI o/p ->upper LFSR 1 Inactive Active 1 1 Lower LFSR changes Inactive Inactive 1 RI o/p ->lower LFSR

13. Random injection circuit Inputs: D flip flop output. Outputs: 32 bit data It generates the output randomly with the reference of the last bit of the lower d flip flop. If the last bit of the d flip flop is logic “0” then the “And” operation is done. If the bit is logic “1” then “OR” operation is done. It sends the randomized data to the output when the selection lines are logic “0” of the multiplexer.

14. Multiplexer As the multiplexer takes the multiple inputs and gives the single output by using the selection lines. Inputs: -Random injection circuit output. -Selection line. Output: - 32-bit test pattern. Based upon selection line the output is given. In this project it works as “when the selection line is “0” then it produces the randomized injection value as the output”. “If the selection line is “1” then it produces the output of the d flip flop”.

15. Comparision between conventional and Low Power LFSR conventional LFSR low power LFSR Transitions 525432 127560 average power 2mW 0.564mW peak power 4mW 2mW power consumption 18 mW 9 mW

16. Software tools Xilinx Vivado : The " linx " represents programmable links that connect programmable logic blocks together. The 'X's at each end represent the programmable logic blocks. Xilinx sells a broad range of FPGAs, complex programmable logic devices (CPLDs), design tools. The Vivado Simulator is a component of the Vivado Design Suite. It is a compiled-language simulator that supports mixed-language, Tcl scripts, encrypted IP and enhanced verification.

17. modelsim Model Sim is a verification and simulation tool for VHDL, Verilog , System Verilog. Model Sim shortens your verification time by including an unprecedented level of verification capabilities in a cost-effective HDL simulation solution. Native support of VHDL, Verilog , System Verilog (design), SVA, PSL, and System C for effective verification of sophisticated design environments. Fast time-to-debug, easy to use, multi-language debug environment.

18. VERILOG HDL The Verilog hardware Start descriptive language is a language that describes the behavior of electronic circuits , most commonly digital circuits . It is used to model electronic systems. This can implement the design using any technology.

19. advantages Implementing an efficient LFSR along with the two algorithms, we are able to reduce the average power of LFSR. By implementing this technique power consumption can be reduced as compared to conventional LFSR technique. Total power consumed in low transition LFSR is 50% less than conventional LFSR. Latency will be improved.

20. SIMULATION

21. RTL Schematic

22. Applications IC design verification: In ICs the process of ensuring that the design intent is mapped into its implementation correctly is termed as verification. Power Optimization:   The application of specific design techniques that reduce the power consumption of an electronic device. BIST Architecture: Built-in self-test, or BIST, is a structural test method that adds logic to an IC which allows the IC to periodically test its own operation.

23. conclusion This project shows an effective HDL implementation of low power utilization for test pattern generator using the Low Power LFSR technique. It also addresses a theory to express a test pattern creation by using Low Transition Linear Feedback Shift Register architecture. By using this technique; power consumption can be reduced as compared to the conventional LFSR technique

24. FUTURE SCOPE Low Power _TPG can be implemented in BIST Architecture. So that it can reduces with area and power consumption compared to normal BIST memory. It can also be improves its latency and provide efficient output.

25. Reference Mohammad Feroz Khan, Devunoori Sandeep , Mohd Khaja Yakoob Hussaini , Vaddepally Ashok, and Lisbeth Priyadharshini , "TPG Applications using LFSR“, Kakatiyaa Institute of Technology and Science, ELSEVIER 2013. R.Ramalakshmi , S.Bibiana Vincy , “DESIGN AND ANALYSIS OF LOW POWER TEST PATTERN GENERATOR USING D FLIP-FLOP” International Conference on Engineering Trends and Science & Humanities (ICETSH-2015) .