Memory read and write

computer organization

1. Memory Read and Write 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 1

2. Memory Address Register (MAR)  is the address register which is used to store the address of the memory location where the operation is being performed. Memory Data Register (MDR)  is the data register which is used to store the data on which the operation is being performed. 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 2

3. Memory Read Operation: Memory read operation transfers the desired word to address lines and activates the read control line.Description of memory read read operation is given below: 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 3

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5. n the above diagram initially, MDR can contain any garbage value and MAR is containing 2003 memory address. After the execution of read instruction, the data of memory location 2003 will be read and the MDR will get updated by the value of the 2003 memory location (3D). 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 5

6. Read Bus Cycle 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 6

7. Processor initiates a read bus cycle by floating the address of the memory location on the address lines. Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines. Processor then sets the Read/Write* signal to high, i.e. read. Now the processor asserts the data strobe signal. This signals to the memory that the processor is ready to read data. The memory subsystem decodes the address and places the data on the data lines. The memory subsystem then asserts the data acknowledge signal. This signals to the processor that valid data can now be latched in. Processor latches in the data and negates the data strobe. This signals to the memory that the data has been latched by the processor. Processor also negates the address strobe signal. Memory subsystem now negates the data acknowledgement signal. This signals the end of the read bus cycle 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 7

8. Memory Write Operation: Memory write operation transfers the address of the desired word to the address lines, transfers the data bits to be stored in memory to the data input lines. Then it activates the write control line. Description of the write operation is given below: 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 8

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10. In the above diagram, the MAR contains 2003 and MDR contains 3D. After the execution of write instruction 3D will be written at 2003 memory location. 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 10

11. Write Bus Cycle 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 11

12. Processor initiates a write bus cycle by floating the address of the memory location on the address lines. Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines. Processor then sets the Read/Write* signal to low, i.e. write. The processor then places the data on the data lines. Now the processor asserts the data strobe signal. This signals to the memory that the processor has valid data for the memory write operation. The memory subsystem decodes the address and writes the data into the addressed memory location. The memory subsystem then asserts the data acknowledge signal. This signals to the processor that data has been written to the memory. Then the processor negates the data strobe, signaling that the data is no longer valid. Processor also negates the address strobe signal. Memory subsystem now negates the data acknowledgement signal, signaling an end to the write bus cycle. 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 12

13. Thank you 12/1/2020 Minu Mary P J,Christ College Autonomous ,Irinjalakkuda 13