Memory Reference Instructions

Memory reference instructions used in computer architecture is well demonstrated with examples. It will probably help you understand each referencing instructions.

1. Memory Reference Instructions Presented by: Rabin BK BSc.CSIT 3 r d Semester

2. CONTENTS Introduction to Memory Reference Instructions Some terminologies Memory Reference Instructions References

3. There are seven different memory-reference instructions Actual execution of the instruction in the bus system requires a sequence of microoperations as data in memory cannot be processed directly Microoperations are needed for the data to be read from memory to a register to operate them on logic circuits Introduction to Memory Reference Instructions Symbol Operation Decoder AND D ADD D 1 LDA D 2 STA D 3 BUN D 4 BSA D 5 ISZ D 6

4. Effective address ( EA ) Any operand to an instruction which references memory Basically enclosed inside a square brackets Calculated as: EA = Base + (Index*Scale) + Displacement Displacement — An 8-, 16-, or 32-bit value. Base — The value in a general-purpose register Index — The value in a general-purpose register Scale factor — A value of 2, 4, or 8 that is multiplied by the index value DR → Data Register AR → Address Register IR → Instruction Register PC → Program Counter AC → Accumulator SC → Sequence Counter Some terminologies

5. AND to AC Performs the AND logic operations on pairs of bits in AC and the memory word specified by the effective address Two timing signals are needed In T 4 transfering operand from memory into DR In T 5 transfering result of AND logic operation between the contents of DR and AC In T 5 SC is cleared to 0 and control is transfered to T to start a new instruction cycle Example: D T 4 : DR ←M[AR] D T 5 : AC ←AC∧ DR, SC←0 Instructions

6. ADD to AC Adds the contents of memory word specified by the effective address to the value of AC Sum is transferred into AC and the output carry C out is transferred to the E (extended accumulator) flip flop Two timing signals are needed but decoder D 1 instead of D Example: D 1 T 4 : DR ←M[AR] D 1 T 5 : AC ←AC+DR , E← C out SC←0 Instructions cont...

7. LDA:Load to AC T ranfers the memory word specified by the effective address to AC Necessary to read the memory word into DR first and transfer the contents of DR into AC there is no direct path from bus into AC to maintain one clock cycle as well Example: D 2 T 4 : DR ←M[AR] D 2 T 5 : AC ←DR SC←0 Instructions cont...

8. STA:Store AC Stores the content of AC into the memory word specified by the effective address The output of AC is applied to the bus and the data input of memory is connected to the bus Example: D 3 T 4 : M[ AR ] ←AC , SC←0 Instructions cont...

9. BUN:Branch Unconditionally PC is incremented at time T 1 to prepare it for the address of the next instruction in the program sequence BUN transfers the program to the instruction specified by the effective address Allows the programmer to specify an instruction out of sequence and we say that the program branches (jumps) unconditionally Example: D 4 T 4 : PC ←AR SC←0 ( resetting SC transfers control to T 4 ) Instructions cont...

10. BSA:Branch and Save Return Address Useful for branching to a portion of the program called a subroutine or procedure When executed, it stores the address of the next instruction in sequence (which is available in PC ) into a memory location specified by the effective address ( Effective address + 1 ) is then transferred to PC to serve as the address of the first instruction in the subroutine The return to the original program is accomplished by the BUN instruction placed at the end of the subroutine Example: D 5 T 4 : M[ AR ] ←PC, AR ← AR+1 D 5 T 5 : PC ← AR, SC←0 Instructions cont...

11. ISZ:Increment and Skip if Zero Increments the word specified by the effective address If the incremented value is equal to 0 , PC is incremented by 1 When a negative number(in 2's compelement) stored in memory word is repeatedy incremented by 1 it eventually reaches zero At this time PC is incremented by one in order to skip the next instruction in the program It is necessary to read the word into DR , increment DR and s tore the word back into memory since it is not possible to increment a word inside the memory Example: D 6 T 4 : DR ← M[ AR ] D 6 T 5 : DR ←DR+1 D 6 T 6 : M[ AR ] ← DR, if ( DR=0 ) then ( PC←PC+1 ) , SC←0 Instructions cont...

12. R eferences Dasgupta, S., Computer Architecture: A Modern Synthersis , Vol. 2 New York: John Wiley, 1989 M.Morris Mano, Computer System Architecture, Pearson, Third Edition https://www.tortall.net/projects/yasm/manual/html/nasm-effaddr.html http://faculty.cs.niu.edu/~berezin/463/notes/addrmode.html https://everything2.com/title/Effective+address

13. Queries