Metastability

This PPT for Metastability Calculation of your Design.

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Metastability

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It is a Periodic Event, causes state of memory element to change.
It can be of rising edge, falling edge, high level, low level.
Clock

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Timing requirements of edge triggered flip-flops
There is a timing
"window" around the
clocking event
during which the input
must remain stable
and unchanged
in order
to be recognized
ts-set up time
Minimum time before the clocking event by which the
input must be stable
th-hold time
Minimum time after the clocking event during which
the input must remain stable

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Metastability
•In non-synchronous systems, if the asynchronous input
signals violate a flip flop's timing requirements, the
output of the flip flops can become metastable.
Synchronous
system
Async in
CLK

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HIGH LOW
LOW HIGH
LOW HIGH
HIGH LOW
Bistable element

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Metastability
Metastability is inherent in any bistable circuit
Two stable points, one metastable point

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Another look at metastability
The likelihood that a flip-flop enters a metastable state and
the time required to return to a stable state varies
depending on the process technology used to manufacture
the device and on the ambient conditions. Generally, flip-
flops will quickly return to a stable state

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•Inputs must be synchronized with the system clock
before being applied to a synchronous system.
Avoiding Metastability
How?

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A simple synchronizer
•But there is a problem ?
•the synchronizer output may become metastable when setup and
hold time are not met.
As shown in above figure, a D flip-flop samples the asynchronous
input at each of the system clock and produces a synchronous
output that is valid during the next clock period.

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Only one synchronizer per input
In this design, the two flip-flops will not see clock and input at precisely
same time because of physical delays in the circuit. Therefore when
asynchronous input transitions occur near the clock edge, there is a small
window of time during which one flip-flop may sample the input as 1 and the
other may sample it as 0.

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An asynchronous input driving two synchronizers through
combinational logic.
The different paths through the combinational logic will inevitably have
different delays, the likelihood of an inconsistent result is even more
greater. The proper way to use an asynchronous signal as a state
machine input is as shown in next figure.

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Better Way To Synchronize Asynchronous Input In
State Machine.
All of the excitation (Combinational) logic sees the same synchronized input
signal, SYNCIN.

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Synchronizer failure and Metastability resolution time
•Synchronizer failureis said to occur if the system uses
synchronizer output while the output is still in
metastable state.
•One way to get a flip-flop out of a metastable state is
to wait long enough so the flip-flop comes out
of metastability on its own.

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Metastability resolution time
•It is the maximum time that the output can remain metastable
without causing synchronizer(and system) failure.
For the above synchronizer the
Metastability resolution time
tr = tclk-tsu

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If there is any combinational ckt then
tr=tclk-tsu-tcomb

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Recommended synchronizer design

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MTBF(Mean Time Between synchronizer Failure)
Theoretical results suggests and experimental research
has confirmed ,that when asynchronous inputs change
during the decision window , the duration of
metastability is governed by the Exponential Formula

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Example
•For a typical 74LS74 flipflop,for which To=0.4 ns anT(twoe)=1.5ns.
•Tsu=20 ns; and the clock period is 100ns (10 MHz);
•tr(resolution time)=tclk-tsu=100-20=80 ns;
•If the synchronizer input changes 100,000 times per second,the
•MTBF(80 ns)=exp(80/1.5)/0.4.(10)
7
.(10)
5
=3.6. 10
11 seconds
= about 100 centuries between
failures.
•With clk period of 62.5 ns MTBF=3.1 s !!!!!!!!!!

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THANK YOU