microprocessor 8086 - Microprocessors Architecture of 8086
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Mar 09, 2025
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About This Presentation
microprocessor 8086
Slide Content
ةيملاسلإا ةيرمسلأا ةعماجلا
ةسدنهلا ةيلك
ةينورتكللااو ةيئابرهكلا ةسدنهلا مسق
Microprocessors
Architecture of 8086
Part 3
دادعإ :شوكبلا حاتفم يحتف
27/05/2024
ةسدنهلا ةيلك
ةينورتكللااو ةيئابرهكلا ةسدنهلا مسق
Microprocessors
Architecture of 8086
Part 3
دادعإ :شوكبلا حاتفم يحتف
27/05/2024
Quiz 6
Answer the following questions:
1.Determine the physical address when DS = 2345H and IP = 1000H. Write the starting and
ending address of the data segment.
2. Draw the block diagram of 8086.
2
Answer the following questions:
1.Determine the physical address when DS = 2345H and IP = 1000H. Write the starting and
ending address of the data segment.
2. Draw the block diagram of 8086.
2
Quiz 6
3
1.Determine the physical address when DS = 2345H and IP = 1000H. Write the starting and ending
address of the data segment.
Solution:
➢The content of the DS is left shifted by 4 bits and the base address becomes 23450 H.
➢To determine the physical address, the content of IP will be added with base address.
➢Hence physical address = 23450 + 1000 = 24450H.
➢The starting of data segment memory = 24450H.
➢As each segment memory consists of 64K memory locations, the end address will be computed
after addition of 64K with the starting of code segment memory.
➢The ending address of code segment = 24450 + FFFF = 3444FH.
3
1.Determine the physical address when DS = 2345H and IP = 1000H. Write the starting and ending
address of the data segment.
Solution:
➢The content of the DS is left shifted by 4 bits and the base address becomes 23450 H.
➢To determine the physical address, the content of IP will be added with base address.
➢Hence physical address = 23450 + 1000 = 24450H.
➢The starting of data segment memory = 24450H.
➢As each segment memory consists of 64K memory locations, the end address will be computed
after addition of 64K with the starting of code segment memory.
➢The ending address of code segment = 24450 + FFFF = 3444FH.
Quiz 6
2. Draw the block diagram of 8086.
4
2. Draw the block diagram of 8086.
4
Outline
5
In this chapter we discuss:
➢The block diagram of microprocessor 8086.
➢Logical and physical addresses advantages of segmented memory.
➢The Pin Configuration Of 8086.
➢Memory Organization Of 8086
5
In this chapter we discuss:
➢The block diagram of microprocessor 8086.
➢Logical and physical addresses advantages of segmented memory.
➢The Pin Configuration Of 8086.
➢Memory Organization Of 8086
3.2 The 8086 Microprocessor
6
The block diagram of 8086 can be represented either as shown in Figure 2.1 or in Figure 2.2.
6
The block diagram of 8086 can be represented either as shown in Figure 2.1 or in Figure 2.2.
3.4 Pin Configuration Of 8086
7
➢The 8086 microprocessor is a 40 pin IC which operates
on +5 V power supply and three clock rates: 5, 8, and 10
MHz.
➢The 8086 operates in both single processor and multiple
processor configurations to achieve high performance
levels.
➢During single processor mode, which is known as
minimum mode, eight of its pins, from pin number 24 to
32 are having different definitions as that of multiple
processor mode, known as maximum mode.
➢The pin diagram of 8086 is shown in Figure 2.5
7
➢The 8086 microprocessor is a 40 pin IC which operates
on +5 V power supply and three clock rates: 5, 8, and 10
MHz.
➢The 8086 operates in both single processor and multiple
processor configurations to achieve high performance
levels.
➢During single processor mode, which is known as
minimum mode, eight of its pins, from pin number 24 to
32 are having different definitions as that of multiple
processor mode, known as maximum mode.
➢The pin diagram of 8086 is shown in Figure 2.5
3.4 Pin Configuration Of 8086
8
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum
Mode
1.��
�−��
�� (address/data bus):
➢These lines are multiplexed address/data lines. During the �
� state
of every machine cycle, these lines carry the address and for the
rest of the T states (�
� , �
� , �
?????? , �
� ), these lines carry the data.
➢Here �
� , �
� , �
� and �
� are clock states of a machine cycle. �
?????? is a
wait state.
➢The lines are active high and float to a tristate during interrupt
acknowledge and local bus hold acknowledge cycles.
➢The �
� line along with ���
−
defines whether the microprocessor
will access the lower byte or the higher byte or the word.
8
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum
Mode
1.��
�−��
�� (address/data bus):
➢These lines are multiplexed address/data lines. During the �
� state
of every machine cycle, these lines carry the address and for the
rest of the T states (�
� , �
� , �
?????? , �
� ), these lines carry the data.
➢Here �
� , �
� , �
� and �
� are clock states of a machine cycle. �
?????? is a
wait state.
➢The lines are active high and float to a tristate during interrupt
acknowledge and local bus hold acknowledge cycles.
➢The �
� line along with ���
−
defines whether the microprocessor
will access the lower byte or the higher byte or the word.
3.4 Pin Configuration Of 8086
9
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
1.��
�−��
�� (address/data bus):
➢ Float to a tristate: Tristate refers to a third state that a signal line can enter in addition to being high or low.
When a line is in the tristate, it effectively becomes disconnected or floating, meaning it is not being driven to a
specific voltage level by any device.
➢��
�−��
�� lines are active high and float to a tristate during interrupt acknowledge and local bus hold
acknowledge cycles.
➢During interrupt acknowledge and local bus hold acknowledge cycles, these lines enter a tristate mode, where they
become effectively disconnected from any driving source, possibly to allow other devices to take control of the bus or
perform certain operations without interference from these lines.
9
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
1.��
�−��
�� (address/data bus):
➢ Float to a tristate: Tristate refers to a third state that a signal line can enter in addition to being high or low.
When a line is in the tristate, it effectively becomes disconnected or floating, meaning it is not being driven to a
specific voltage level by any device.
➢��
�−��
�� lines are active high and float to a tristate during interrupt acknowledge and local bus hold
acknowledge cycles.
➢During interrupt acknowledge and local bus hold acknowledge cycles, these lines enter a tristate mode, where they
become effectively disconnected from any driving source, possibly to allow other devices to take control of the bus or
perform certain operations without interference from these lines.
3.4 Pin Configuration Of 8086
10
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
2. �
��/ �
�, �
�� / �
�, �
�� / �
�, �
��/ �
� (address and status lines):
➢These are the upper four address lines of the microprocessor. These lines are multiplexed with the status signals �
�,
�
�, �
� and �
�. During �
� state, these acts as address lines for memory operations.
➢For the remaining T states, these lines show the status information:
➢�
� and �
� give the information about the segment which is currently used by the processor. These lines are
encoded as shown in Table 2.2.
➢The status signal �
� keeps the value of Interrupt Enable Flag
(IF). The status of the IF flag bit (�
�) is updated at the
beginning of each CLK cycle.
➢The �
� is always low (logical) during (�
� t?????? �
� ).
10
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
2. �
��/ �
�, �
�� / �
�, �
�� / �
�, �
��/ �
� (address and status lines):
➢These are the upper four address lines of the microprocessor. These lines are multiplexed with the status signals �
�,
�
�, �
� and �
�. During �
� state, these acts as address lines for memory operations.
➢For the remaining T states, these lines show the status information:
➢�
� and �
� give the information about the segment which is currently used by the processor. These lines are
encoded as shown in Table 2.2.
➢The status signal �
� keeps the value of Interrupt Enable Flag
(IF). The status of the IF flag bit (�
�) is updated at the
beginning of each CLK cycle.
➢The �
� is always low (logical) during (�
� t?????? �
� ).
3.4 Pin Configuration Of 8086
11
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
3.���
−
/�
� (bus high enable/status):
➢The ���
−
signal is used to enable the higher or the odd memory bank. During �
� state of every machine cycle,
the bus high enable signal (���
−
) is used to enable data onto the �
�� - �
� data lines which are connected with
the odd memory bank.
➢The ���
−
along with the �
� address line is used to the even or the odd or both the banks. These two signals are
encoded as per Table 2.3.
➢During the rest of the T state state (i.e. �
� , �
� and �
� ), this line sends the status signal �
� , which is a logic 1
and currently not used.
11
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
3.���
−
/�
� (bus high enable/status):
➢The ���
−
signal is used to enable the higher or the odd memory bank. During �
� state of every machine cycle,
the bus high enable signal (���
−
) is used to enable data onto the �
�� - �
� data lines which are connected with
the odd memory bank.
➢The ���
−
along with the �
� address line is used to the even or the odd or both the banks. These two signals are
encoded as per Table 2.3.
➢During the rest of the T state state (i.e. �
� , �
� and �
� ), this line sends the status signal �
� , which is a logic 1
and currently not used.
3.4 Pin Configuration Of 8086
12
3.4.1 Pin Details of 8086 Common to Both Minimum and
Maximum Mode
4. ��
−
(read):
➢It is an active low output signal. It indicates that the
microprocessor is performing a memory or I/O read operation.
➢This signal is used to read devices which are connected to the
8086 local bus.
➢ ��
−
is activated during �
� , �
� and �
� of any read machine
cycle, and remain high in the other T states.
➢��
−
pin floats to its high-impedance state during a hold
acknowledge.
12
3.4.1 Pin Details of 8086 Common to Both Minimum and
Maximum Mode
4. ��
−
(read):
➢It is an active low output signal. It indicates that the
microprocessor is performing a memory or I/O read operation.
➢This signal is used to read devices which are connected to the
8086 local bus.
➢ ��
−
is activated during �
� , �
� and �
� of any read machine
cycle, and remain high in the other T states.
➢��
−
pin floats to its high-impedance state during a hold
acknowledge.
3.4 Pin Configuration Of 8086
13
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
5. READY:
➢The addressed I/O or memory devices send acknowledgment through
this pin and it indicates that the data transfer is completed. The READY
signal from memory or I/O is synchronized by the 8284A clock
generator to provide READY input to 8086. This signal is active HIGH.
➢When READY is HIGH, it indicates that the peripheral is ready to
transfer data.
➢When a peripheral device is ready to receive/transmit the data, it will
send the READY signal to the microprocessor. On receiving this signal
microprocessor, release the data and enter into the wait state till the next
READY signal.
13
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
5. READY:
➢The addressed I/O or memory devices send acknowledgment through
this pin and it indicates that the data transfer is completed. The READY
signal from memory or I/O is synchronized by the 8284A clock
generator to provide READY input to 8086. This signal is active HIGH.
➢When READY is HIGH, it indicates that the peripheral is ready to
transfer data.
➢When a peripheral device is ready to receive/transmit the data, it will
send the READY signal to the microprocessor. On receiving this signal
microprocessor, release the data and enter into the wait state till the next
READY signal.
3.4 Pin Configuration Of 8086
14
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
6. INTR (interrupt request): It is an interrupt request signal. This is an active high level triggered
input signal. INTR is sampled by the processor in the last clock cycle of each instruction. If
microprocessor finds this signal as high, then the processor enter into an interrupt acknowledge
operation after the current instruction has completed execution. It can be internally masked by
software resetting the interrupt enable bit.
7. ����
−
: This is used in conjunction with the WAIT instruction. If the ����
−
input is LOW,
execution continues. Otherwise the processor waits in an idle state. This input is synchronized internally
during each clock cycle on the leading edge of CLK.
14
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
6. INTR (interrupt request): It is an interrupt request signal. This is an active high level triggered
input signal. INTR is sampled by the processor in the last clock cycle of each instruction. If
microprocessor finds this signal as high, then the processor enter into an interrupt acknowledge
operation after the current instruction has completed execution. It can be internally masked by
software resetting the interrupt enable bit.
7. ����
−
: This is used in conjunction with the WAIT instruction. If the ����
−
input is LOW,
execution continues. Otherwise the processor waits in an idle state. This input is synchronized internally
during each clock cycle on the leading edge of CLK.
3.4 Pin Configuration Of 8086
15
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
8. NMI (non-maskable interrupt):
➢ NMI is the non maskable interrupt. This interrupt cannot be masked or denied. It is an edge
triggered input which causes a type 2 interrupt. A transition from LOW TO HIGH initiates the
interrupt at the end of the current instruction. This input is internally synchronized.
➢The non-maskable interrupt input is similar to INTR except that the NMI interrupt does not
check to see whether the IF flag bit is a logic 1. If NMI is activated, this interrupt input uses
interrupt vector 2. (type 2 interrupt will be explained later)
9. RESET: RESET causes the processor to immediately terminate its current operation. The signal
must be active high for at least four clock cycles.
15
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
8. NMI (non-maskable interrupt):
➢ NMI is the non maskable interrupt. This interrupt cannot be masked or denied. It is an edge
triggered input which causes a type 2 interrupt. A transition from LOW TO HIGH initiates the
interrupt at the end of the current instruction. This input is internally synchronized.
➢The non-maskable interrupt input is similar to INTR except that the NMI interrupt does not
check to see whether the IF flag bit is a logic 1. If NMI is activated, this interrupt input uses
interrupt vector 2. (type 2 interrupt will be explained later)
9. RESET: RESET causes the processor to immediately terminate its current operation. The signal
must be active high for at least four clock cycles.
3.4 Pin Configuration Of 8086
16
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
10. CLK (clock): The CLK is an input to the microprocessor and it provides the basic timing to the
microprocessor and bus controller. This signal is generated by the 8284 clock generator.
11. MN/��
−
(minimum/maximum): This signal indicates that in which mode the processor is to
operate. If this pin is high, it means that the microprocessor will be in single processor mode and if it is
low, then the microprocessor will be in multiprocessor operation mode.
12.�
�� : This pin is connected to the +5 V power supply.
13.GND: It is the GROUND pin.
16
3.4.1 Pin Details of 8086 Common to Both Minimum and Maximum Mode
10. CLK (clock): The CLK is an input to the microprocessor and it provides the basic timing to the
microprocessor and bus controller. This signal is generated by the 8284 clock generator.
11. MN/��
−
(minimum/maximum): This signal indicates that in which mode the processor is to
operate. If this pin is high, it means that the microprocessor will be in single processor mode and if it is
low, then the microprocessor will be in multiprocessor operation mode.
12.�
�� : This pin is connected to the +5 V power supply.
13.GND: It is the GROUND pin.
3.4 Pin Configuration Of 8086
17
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in
minimum mode (i.e. MN/��
−
= �
��).
1. M/��
−
(status line): It is an output signal. It is used to
distinguish whether microprocessor is going to access a memory
or an IO. If M/��
−
becomes zero, it means it will be an IO
operation, otherwise a memory operation. M/��
−
pin is at its
high-impedance state during a hold acknowledge.
17
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in
minimum mode (i.e. MN/��
−
= �
��).
1. M/��
−
(status line): It is an output signal. It is used to
distinguish whether microprocessor is going to access a memory
or an IO. If M/��
−
becomes zero, it means it will be an IO
operation, otherwise a memory operation. M/��
−
pin is at its
high-impedance state during a hold acknowledge.
3.4 Pin Configuration Of 8086
18
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
= �
��).
2. ��
−
(write): It is an active low output signal. It indicates that the microprocessor is
performing a write operation either from memory or I/O, depending on the status of the M/��
−
signal. ��
−
is active for �
� , �
� and TW of any write machine cycle.
3. ����
−
(interrupt acknowledge): It is an active low output signal. Microprocessor sends this
signal in response to an interrupt request signal ( INTR input pin ). It is active LOW during �
� ,
�
� and TW of each interrupt acknowledge cycle. The INTA
−
pin is normally used to gate the
interrupt vector number onto the data bus in response to an interrupt request.
18
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
= �
��).
2. ��
−
(write): It is an active low output signal. It indicates that the microprocessor is
performing a write operation either from memory or I/O, depending on the status of the M/��
−
signal. ��
−
is active for �
� , �
� and TW of any write machine cycle.
3. ����
−
(interrupt acknowledge): It is an active low output signal. Microprocessor sends this
signal in response to an interrupt request signal ( INTR input pin ). It is active LOW during �
� ,
�
� and TW of each interrupt acknowledge cycle. The INTA
−
pin is normally used to gate the
interrupt vector number onto the data bus in response to an interrupt request.
3.4 Pin Configuration Of 8086
19
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
=
�
��).
4. ALE (address latch enable): It is an active high output signal. Address latch enable shows
that the 8086 address/data bus contains address information. This address can be a memory
address or an I/O port number. It is a high pulse active during �
� of any machine cycle.
Whenever the processor sends a valid address on the multiplexed lines it also makes the ALE high.
ALE is never floated.
19
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
=
�
��).
4. ALE (address latch enable): It is an active high output signal. Address latch enable shows
that the 8086 address/data bus contains address information. This address can be a memory
address or an I/O port number. It is a high pulse active during �
� of any machine cycle.
Whenever the processor sends a valid address on the multiplexed lines it also makes the ALE high.
ALE is never floated.
3.4 Pin Configuration Of 8086
20
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
= �
��).
5. ��/�
−
(data transmit/receive): It is used to control the direction of data flow through the
transceiver. If it is high, then data will be transmitted, otherwise data will come to the
microprocessor. This signal is used only in minimum mode. It is used to select the direction of the
transceiver 8286.
6. ���
−
(data enable): It is an active low output signal. It is provided as an output enable for the
8286/8287 in a minimum system which uses the transceiver. ���
−
is active during each memory
and I/O access and for ����
−
cycles. For a read or ����
−
cycle, it is active from the middle of �
�
until the middle of �
� , while for a write cycle, it is active from the beginning of �
� until the
middle of �
� .
20
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
= �
��).
5. ��/�
−
(data transmit/receive): It is used to control the direction of data flow through the
transceiver. If it is high, then data will be transmitted, otherwise data will come to the
microprocessor. This signal is used only in minimum mode. It is used to select the direction of the
transceiver 8286.
6. ���
−
(data enable): It is an active low output signal. It is provided as an output enable for the
8286/8287 in a minimum system which uses the transceiver. ���
−
is active during each memory
and I/O access and for ����
−
cycles. For a read or ����
−
cycle, it is active from the middle of �
�
until the middle of �
� , while for a write cycle, it is active from the beginning of �
� until the
middle of �
� .
3.4 Pin Configuration Of 8086
21
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
= �
��).
7. HOLD (hold request):
➢It is an active high input signal. This pin is used by external devices (like Direct memory access controller (DMAC)) to
gain control of the buses. When the HOLD signal is activated by an external device, the microprocessor suspends
current execution after the completion of the current machine cycle and stops using the buses. After releasing the buses,
it sends the HLDA signal as an acknowledgement. This would allow external devices to control the buses.
➢A HOLD signal indicates that another device in a microcomputer system is requesting a local bus hold for using the address
and data bus. Then the master sends a HOLD request to processor through this pin. It is an active HIGH signal.
8. HLDA (Output) Hold Acknowledge: It indicates that the microprocessor has received the Hold request and that it will
relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The microprocessor takes
the buses one-half clock cycles after HLDA, goes low.
21
3.4.2 Pin Details of 8086 - (Minimum Mode):
The following pin function descriptions are for the 8086 in minimum mode (i.e. MN/��
−
= �
��).
7. HOLD (hold request):
➢It is an active high input signal. This pin is used by external devices (like Direct memory access controller (DMAC)) to
gain control of the buses. When the HOLD signal is activated by an external device, the microprocessor suspends
current execution after the completion of the current machine cycle and stops using the buses. After releasing the buses,
it sends the HLDA signal as an acknowledgement. This would allow external devices to control the buses.
➢A HOLD signal indicates that another device in a microcomputer system is requesting a local bus hold for using the address
and data bus. Then the master sends a HOLD request to processor through this pin. It is an active HIGH signal.
8. HLDA (Output) Hold Acknowledge: It indicates that the microprocessor has received the Hold request and that it will
relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The microprocessor takes
the buses one-half clock cycles after HLDA, goes low.
3.4 Pin Configuration Of 8086
22
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
1. �
�
−
, �
�
−
, �
�
−
( Output ) Status Signals: These are three status output signals. These signals are
connected to the bus controller Intel 8288. The bus controller decodes these signals to generate eight
separate memory, I/O access control signals and INTA signal in maximum mode, as depicted in Table
2.4 which shows the logic for status signals.
➢These status signals are active during T
1, T
2, and T
4
and are returned to the passive state (1, 1, 1) during T
3
or during T
W .
22
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
1. �
�
−
, �
�
−
, �
�
−
( Output ) Status Signals: These are three status output signals. These signals are
connected to the bus controller Intel 8288. The bus controller decodes these signals to generate eight
separate memory, I/O access control signals and INTA signal in maximum mode, as depicted in Table
2.4 which shows the logic for status signals.
➢These status signals are active during T
1, T
2, and T
4
and are returned to the passive state (1, 1, 1) during T
3
or during T
W .
3.4 Pin Configuration Of 8086
23
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
2. ��
−
/��
�
−
, ��
−
/��
�
−
(I/O REQUEST/GRANT): These signals are the same as that of HOLD
and HLDA in minimum configuration. These pins are used by other local bus masters to force
the processor to release the local bus at the end of the processor’s current machine cycle. Each
pin is bidirectional with RQ/ ��
�
−
having higher priority than RQ/ ��
�
−
.
23
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
2. ��
−
/��
�
−
, ��
−
/��
�
−
(I/O REQUEST/GRANT): These signals are the same as that of HOLD
and HLDA in minimum configuration. These pins are used by other local bus masters to force
the processor to release the local bus at the end of the processor’s current machine cycle. Each
pin is bidirectional with RQ/ ��
�
−
having higher priority than RQ/ ��
�
−
.
3.4 Pin Configuration Of 8086
24
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
2. ��
−
/��
�
−
, ��
−
/��
�
−
(I/O REQUEST/GRANT ):
The request/grant sequence is as follows:
(a)The local bus master sends a pulse of 1T duration to the processor for the bus request.
(b)During a �
� or �
� clock cycle, the microprocessor 8086 send a pulse of 1T duration to the requesting master
to indicate that the 8086 has allowed the local bus to float and it sends the hold acknowledgement signal.
The microprocessor disconnects all its non - direct memory accesses (DMA) devices from the local bus
during hold acknowledge.
(c)In the last the requesting master sends a pulse of 1T duration to indicate to the 8086 that the hold request is
about to end and that the 8086 can regain the local bus at the next CLK.
24
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
2. ��
−
/��
�
−
, ��
−
/��
�
−
(I/O REQUEST/GRANT ):
The request/grant sequence is as follows:
(a)The local bus master sends a pulse of 1T duration to the processor for the bus request.
(b)During a �
� or �
� clock cycle, the microprocessor 8086 send a pulse of 1T duration to the requesting master
to indicate that the 8086 has allowed the local bus to float and it sends the hold acknowledgement signal.
The microprocessor disconnects all its non - direct memory accesses (DMA) devices from the local bus
during hold acknowledge.
(c)In the last the requesting master sends a pulse of 1T duration to indicate to the 8086 that the hold request is
about to end and that the 8086 can regain the local bus at the next CLK.
3.4 Pin Configuration Of 8086
25
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
3. LOCK
−
: It is an active low output signal. If this signal is active low, then the other bus masters will not be
allowed to take control over the system buses. The LOCK signal is activated by the LOCK instruction and
remains active until the completion of the next instruction.
4. ��
�, ��
� (queue status): ��
� and ��
� provide
status to allow external tracking of the internal 8086
instruction queue. These status signals are interfaced
with the status signals (of the same name) of the math
coprocessor 8087. By these two status signals, the math
coprocessor tracks the queue of 8086. The queue
status signals ��
� and ��
� are encoded in Table 2.5
25
3.4.3 Pin Details of 8086 S - (Maximum Mode)
The following pin function descriptions are for the 8086/8288 system in maximum mode:
3. LOCK
−
: It is an active low output signal. If this signal is active low, then the other bus masters will not be
allowed to take control over the system buses. The LOCK signal is activated by the LOCK instruction and
remains active until the completion of the next instruction.
4. ��
�, ��
� (queue status): ��
� and ��
� provide
status to allow external tracking of the internal 8086
instruction queue. These status signals are interfaced
with the status signals (of the same name) of the math
coprocessor 8087. By these two status signals, the math
coprocessor tracks the queue of 8086. The queue
status signals ��
� and ��
� are encoded in Table 2.5
References
➢Soumitra Kumar Mandal. Microprocessors and Microcontrollers, Architecture, Programming and
Interfacing using 8085, 8086, 8051. New Delhi, 2011.
➢Walter A. Triebel Avtar Singh. The 8088 and 8086 Microprocessors Programming, Interfacing, Hardware.
United Kingdom, Fourth Edition, 2014.
➢ SUNIL MATHUR. MICROPROCESSOR 8086 Architecture, Programming and Interfacing, New Delhi,
2011.
➢ BARRY B. BREY. THE INTEL MICROPROCESSORS 8086/8088, 80186/80188, 80286, 80386, 80486,
Pentium, Pentium Pro Processor, Pentium II, Pentium III, Pentium 4, and Core2 with 64-Bit Extensions
Architecture, Programming, and Interfacing, Eighth Edition, 2009.
26
➢Soumitra Kumar Mandal. Microprocessors and Microcontrollers, Architecture, Programming and
Interfacing using 8085, 8086, 8051. New Delhi, 2011.
➢Walter A. Triebel Avtar Singh. The 8088 and 8086 Microprocessors Programming, Interfacing, Hardware.
United Kingdom, Fourth Edition, 2014.
➢ SUNIL MATHUR. MICROPROCESSOR 8086 Architecture, Programming and Interfacing, New Delhi,
2011.
➢ BARRY B. BREY. THE INTEL MICROPROCESSORS 8086/8088, 80186/80188, 80286, 80386, 80486,
Pentium, Pentium Pro Processor, Pentium II, Pentium III, Pentium 4, and Core2 with 64-Bit Extensions
Architecture, Programming, and Interfacing, Eighth Edition, 2009.
26
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