MICROPROCESSORS AND MICROCONTROLLERS 1.pptx

MICROPROCESSORS AND MICROCONTROLLERS

1. MICROPROCESSORS AND MICROCONTROLLERS Module 1: Introduction to 8086

2. Introduction Intel introduced its first 4-bit microprocessor 4004 in 1971 and its 8-bit microprocessor 8008 in 1972. could not survive as general purpose microprocessors due to their design and performance limitations. First general purpose 8-bit microprocessor 8080 in 1974. Microprocessor 8085 followed 8080, more added features to its architecture, functionally complete microprocessor. Main limitations of the 8-bit microprocessors: low speed, low memory addressing capability, limited number of general purpose registers and a less powerful instruction set. To address this the 8086 was developed in 1978 (16-bit microprocessors) .

3. REGISTER ORGANISATION OF 8086 General Data Registers Used mainly for arithmetic and logic operations Segment Registers Content is the starting address of the segment Pointers and Index Registers Pointers contain offset within the particular segments. The pointers IP, BP and SP usually contain offsets within the code (JP), and stack (BP & SP) segments. Index registers are used as general purpose registers as well as for offset storage in case of indexed, based indexed and relative based indexed addressing modes. Flag Register The 8086 flag register contents indicate the results of computations in the ALU.

4. GENERAL PURPOSE REGISTERS The registers AX,BX,CX and DX are the general purpose 16-bit registers. AX is used as 16-bit accumulator, with the lower 8-bits of AX designated as AL and higher 8-bits as AH. X is used to specify the complete 16-bit register. BX or Base register is used as an offset storage for forming physical addresses in case of certain addressing modes. CX or Count register is used as a default counter in case of string and loop instructions. DX or Data register is used as an implicit operand or destination in case of a few instructions.

5. SEGMENT REGISTERS Code Segment Register (CS) Used for addressing a memory location in the code segment of the memory, where the executable program is stored. Data Segment Register (DS) Points to the data segment of the memory, where the data is resided. Extra Segment Register (ES) Refers to a segment which essentially is another data segment of the memory. Stack Segment Register (SS) Used for addressing stack segment of memory i.e. memory which is used to store stack data.

6. Index registers SI or Source Index Used to store the offset of source data in data segment DI or Destination Index Used to store the offset of destination in data or extra segment The index registers are particularly useful for string manipulations. The index registers are used as general purpose registers as well as for offset storage in case of indexed, based indexed and relative based indexed addressing modes.

7. Pointers The pointers contain offset within the particular segments. The pointers IP, BP and SP usually contain offsets within the code (JP), and stack (BP & SP) segments. IP or Instruction pointer SP or Stack pointer BP or Base pointer

8. Flags 8086 has a 16-bit flag register which is divided into two parts: (a) condition code or status flags (b) machine control flags condition code flag register is the lower byte of the 16-bit flag register along with the overflow flag. The control flag register is the higher byte of the flag register of 8086. It contains three flags: direction flag (D), interrupt flag (I) and trap flag (T)

9. ARCHITECTURE Supports 16-bit ALU, set of 16-bit registers and provides segmented memory addressing capability, rich instruction set, powerful interrupt structure, fetched instruction queue for overlapped fetching and execution etc. Complete architecture of 8086 can be divided into two parts: Bus Interface Unit (BIU) and Execution Unit (EU) The bus interface unit contains the circuit for physical address calculations and a predecoding instruction byte queue (6 bytes long). The execution unit contains the register set of 8086 except segment registers and IP, 16-bit ALU, 16-bit flag register reflects the results of execution by the ALU. The decoding unit decodes the opcode bytes issued from the instruction byte queue. The timing and control unit derives the necessary control signals to execute the instruction opcode received from the queue, depending upon the information made available by the decoding circuit.

10. Function/purpose of BIU: Communication Instruction Pipelining Physical address calculation

11. SIGNAL DESCRIPTIONS OF 8086 The microprocessor 8086 is a 16-bit CPU available in three clock rates, i.e. 5, 8 and 10 MHz, packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configurations to achieve high performance. The 8086 signals can be categorized in three groups Signals having common functions in minimum as well as maximum mode Signals having special functions for minimum mode Signals having special functions for maximum mode

12. Signals having common functions in minimum and maximum mode - : Time multiplexed memory I/O address and data lines. Address remains on the lines during T ₁ state, while the data is available on the data bus during T₂,T₃,Tᵥᵥ and T ₄ . (Tᵥᵥ is a wait state) Lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. A₁₉/S₆,A₁₈/S₅, A₁₇/S₄, A₁₆/S₃: Time multiplexed address and status lines. Most significant address lines for memory operations during T ₁ Low during I/O operations Status of the interrupt enable flag bit (displayed on S ₅ ) is updated at the beginning of each clock cycle.  

13. The S₃ and S₄ together indicate which segment register is presently being used for memory accesses, These lines float to tri-state off ( tristated ) during the local bus hold acknowledge S is always low (logical) The address bits are separated from the status bits using latches controlled by the ALE signal.

14. B̅H̅E/S ₇ -Bus High Enable/Status: Indicate the transfer of data over the higher order ( — ) data bus It goes low for the data transfers over — and is used to derive chip selects of odd address memory bank or peripherals. B̅H̅E is low during T, for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on the higher byte of the data bus. Status information available during T₂,T₃ and T ₄ .  

15. -Read: Read signal, when low, indicates the peripherals that the processor is performing a memory or I/O read operation. READY: Acknowledgement from the slow devices or memory that they have completed the data transfer INTR-Interrupt Request : Determine the availability of the request T̅E̅S̅T: examined by a ‘WAIT” instruction. If it goes low, execution will continue, else, the processor remains in an idle state. NMI-Non-maskable Interrupt : Causes a Type2 interrupt RESET: Causes processor to terminate current activity and start execution from FFFFOH.  

16. CLK-Clock Input: Provides the basic timing for processor operation and bus control Vcc and GND : +5V power supply for the operation of the internal circuit and ground MN/ M̅X: Decides whether the processor is to operate in either minimum (single processor) or maximum (multiprocessor) mode

17. Signals having special functions for minimum mode M/ I̅/̅O -Memory/ lO : When low indicates the CPU is having an I/O operation When high indicates that the CPU is having memory operation I̅N̅T̅A -Interrupt Acknowledge: Used as a read strobe for interrupt acknowledge cycles. ALE-Address Latch Enable : Indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches active high and never tristated DT/ -Data Transmit/Receive: Decide direction of data flow through transreceivers (bidirectional buffers).  

18. D̅E̅N-Data Enable: Indicates the availability of valid data over the address/data lines Enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. HOLD,HLDA-Hold/Hold Acknowledge : When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access Processor issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus (instruction) cycle.

19. Signals having special functions for maximum mode , , -Status Lines: Indicate type of operation, being carried out by processor  

20. L̅O̅C̅K: Indicates that other system bus masters will be prevented from gaining the system bus, while the L̅O̅C̅K signal is low. QS1, QS0-Queue Status: Give information about the status of the code-prefetch queue. RQ/G ,RQ/GT, -Request/Grant: Used by other local bus masters, in maximum mode, to force the processor to release the local bus at the end of the processor’s current bus cycle.