MIPI Test Solutions Overview_Webinar.pdf

MIPI Testing

1. MIPI
®
Physical Layer Test Solutions
Chris Loberg & Keyur Diwan

2. Agenda
MIPI PHY Overview
Measurement Challenges
Transmitter Test Overview
Probing Approaches
Receiver Test Overview
Logic & Protocol Testing
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3. Why MIPI?
Target applications
–Mobile Applications
–Camera
–Display
–Chip-to-chip Interconnect
–Storage
–Memory
Key features
–Low Power
–Low Pin Count
–Minimize interference
–Optional support for optical interconnects (M-PHY)
Key benefits
–High Performance
–High Scalability
–High Bandwidth
–Unprecedented Flexibility
Supported by industry
–Shipping in millions of mobile products
–JEDEC Universal Flash Storage
–Mobile PCI Express
–USB SSIC
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Source: MIPI Alliance Specification Brief, Physical Layers: M-PHY, D-PHY, C-PHY

4. MIPI PHY Overview
Intel MIPI Webinar MIPI Phy Solutions
Source: MIPI Alliance Specification Brief, Physical Layers: M-PHY, D-PHY, C-PHY

5. MIPI Measurement Challenges
Signal access
Complex signaling
Tests specified at RX or TX pin
Terminated and un-terminated modes
Differential and non-differential signaling
Low power (LP) and high-speed (HS) modes
Spec to CTS latency
Switchable termination networks
Receiver stress dependencies
New measurements required
Multi-lane testing
Different encoding schemes
Different clocking architecture
Built-in chip/SoCerror detectors
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6. D-PHY Challenges
D-PHY v2.0 specifies bit rates up to 4.5Gb/s
Separate measurement specs for LP and HS modes.
Receiver stress includes clk-data skew, common mode (CM) and differential mode voltage,
eSpikeand Tmin-rxevents, and CM noise interferer
Error detection using on-chip/SoC error detector
Channel ISI may minimized by TX pre-emphasis
TX and RX input impedance tolerance
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7. M-PHY Challenges
M-PHY v3.1 specifies bit rates up to 5.83Gb/s, with a roadmap to support >10Gb/s signaling in
future versions.
Separate measurement specs for low LP and HS modes.
Multiple bit rates for LP and HS.
Requirement to separate jitter and noise, extrapolate eye openings to 1E-10 for transmitter testing
Receiver stress includes ISI, CM and differential mode voltage, random and sinusoidal jitter
Stress calibration critical to margin and jitter tolerance tests
TX and RX input impedance tolerance –100 Ohms for HS and NT for LP Modes
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8. C-PHY Challenges
C-PHY v1.0 specifies bit rates up to 2.5Gb/s, an aggregate bit rate over three-wire lane of
5.7Gb/s
Separate measurement specs for LP and HS modes.
TX measurements rely on 1
st
triggered edge clock recovery
Receiver stress includes slew rate, channel ISI, CM and differential mode voltage and duty
cycle distortion
TX and RX input impedance tolerance
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9. Transmitter Test Overview
D-PHY
–Clock and data are pseudo-differential
–LP and HS modes
–Measurements specified at TX pin, de-embed channel effects
–55 tests (group 1-6) including CM/differential voltage, rise/fall time, LP-HS entry and exit
M-PHY
–Data is pseudo-differential
–PWM and HS modes
–Measurements specified at TX pin, de-embed channel effects
–38 tests (Group 1-3) including CM/differential mode voltage, rise/fall time, UI, jitter, and eye diagram
C-PHY
–Data is three-wire single-ended, probe A & B & C on different scope channels
–LP and HS modes
–Measurements specified at TX pin, de-embed channel effects
–32 tests (Group 1-3) including CM/differential mode voltage, rise/fall time, CM noise, and eye diagram
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10. D-PHY Transmitter Measurements
Detection of LP-HS transition and timing measurements on that transition
Dynamic switching of terminations between LP and HS mode
Measurements on clock and data lanes verify voltage and timing parameters, separate LP from
HS bits
D-PHY v2.0 adds eye diagram and jitter measurements
Bus Turn Around test –user intervention to enable BTA mode and run tests
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11. M-PHY Transmitter Measurements
Total Jitter, Jitter Separation and
Extrapolated Eye Analysis at 1E-10
Slew Rate Testing
Common Mode AC/DC
measurements
Lane to Lane Skew
Integration with Sig Test for Jitter
Analysis and Correlation (Future)
Power Spectral Density
(Informative Test)
PWM and SYS Mode tests
BER CONTOUR USING DPOJET
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12. C-PHY Transmitter Measurements
1
st
triggered edge recovered from A, B, and C wires
Eye mask placement for optimal eye opening
Jitter and eye diagram rendering performed over entire record length
Rise/fall times specified for different transitions
Embed or de-embed insertion loss and crosstalk from s-parameter file
Acquire user specified # live waveforms, or process captured waveforms
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13. C-PHY Signaling
(1) lane consists of (3) separate V
A, V
B, and V
Csingle-ended signals
Bit encoding by TX, 16-bits 7 symbols three-wire state levels
Differential RX sees three voltages as V
AB, V
BC, and V
CA
Bits decoded by RX, three wire state levels 7 symbols 16-bits
Co-exist on same pins used for D-PHY(high) ¾ V
(low) ¼ V
Strong 1
zero
crossing
Strong 0
(mid) ½ V
Weak 1
Weak 0
+x +z +y +z -z +x -z
VA
VB
VC
VA - VB
VB - VC
VC - VA
UIINST UIINST UIINST UIINST UIINST
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14. Probing Approaches
D-PHY & C-PHY
Tektronix P7300A probes recommended for D-PHY and C-
PHY
–New flex tips are in-expensive, easy to use, and robust
Termination fixtures provide switchable termination for LP
and HS modes. Two versions available: 3-lane board from
UNH/IOL, 4-lane board from Moving Pixel Company.
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15. * –Actual loads show significant non-ideal effects at 1 GHz and above
‡-If Termination Voltage (Vterm)is set to the common-mode voltage, there will be no DC CM current.
Ideal 100Ω2 SE Inputs 2 SE Inputs
w/DC block
Diff Input with
Cterm
Diff Input with
Vterm
Nominal Differential Input Impedance100Ω 100Ω 100Ω 100Ω 100Ω
DC Differential Input Current (200mV
Vdiff)
2mA 2mA 0 2mA 2mA
DC Common-Mode Input Current
(100mVVcm)
0 4mA 0 0 0
‡
DC Common-Mode Input Impedance ∞ 25Ω ∞ ∞ 25Ω
AC Common-Mode Input Impedance Varies with
frequency*
Nominally
constant 25Ω
Nominally constant
25Ωat higher
frequencies
Nominally constant
25Ωat higher
frequencies
Nominallyconstant
25Ω
Probing Approaches
M-PHY
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16. Embedding & De-embedding
S-parameter Application
MIPI parameters specified at the IC pin
–For TX measurements, de-embed to TX pin
–For RX measurements, embed for stress calibration to RX pin
S-parameter files used to represent insertion loss, cross-talk, and reflections
S-parameters converted to embed or de-embed filters
Measurements applied to filtered data
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Before embed After embed

17. Receiver Test Overview
D-PHY
–Calibration for RX to be implemented in v2.0.
–LP and HS modes
–35 tests (group 1-6) including eSPIKE, CM/differential voltage, Jitter Tolerance, Sinusoidal interference
M-PHY
–RX Calibration using Replica Trace, ISI Channel with Sjand Rj
–PWM, SYS and HS modes
–32 tests (Group 1-3) including CM/differential mode voltage, rise/fall time, UI, jitter, and eye diagram
C-PHY
–Data is three-wire single-ended, probe A & B & C on different scope channels
–LP and HS modes
–24 tests (Group 1-3) including eSPIKE, CM/differential voltage, Jitter Tolerance, Interference Tolerance
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18. D-PHY Receiver Measurements
Dynamic Skew, Rj, Sj, ISI
LP, HS, LP-HS modes
Control of protocol parameters, LP and HS
amplitude
User specified test patterns to:
Isolate and stress physical layer interface
Encoded data following encoding rules
Long enough to yield statistically rich behavior
Generated and observe “in system”
Skew control
Rise/fall time for LP
LP voltage up to 1.3v
Common mode noise insertion
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19. M-PHY Receiver Measurements
Stress calibration key to accurate RX
measurements
Stressors include rise/fall time, ISI, Rj, Sj, CM
voltage, and differential eye height.
Jitter tolerance and margin tests at multiple Sj
values
Differential termination enable/disable timing
tests
Test at nominal bit rates +/-2000ppm
Stressed receiver testing
–BERT
–AWG + external error detector
PWM & SYS Mode Testing with iBER
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20. C-PHY Receiver Measurements
Generate tri-level monotonic test signals
Test patterns must match iBERrequirements
16-bit words, 6-wire states, PRBS9/11/18
Stressors include rise/fall time, duty cycle distortion
(DCD), ISI, CM voltage, differential voltage /
differential eye height.
LP-HS sequence dependencies:
LP voltage
LP-HS transition time
# sync words
Pattern payload
Append HS waveforms for sequence-based looping
for compliance and margin testing
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21. Logic & Protocol Testing
D-PHY and C-PHY camera emulation using
standalone pattern generators
D-PHY, M-PHY, and C-PHY packet and logic
analysis available
Time-correlate captures with other buses or
instruments
Generate complex sequence-based test cases
to stress the CSI link
Trigger and debug packet and logic failures if
encountered
Multi-lane real-time monitoring
Video and virtual channel decode
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22. Electrical
D-PHY Test Solutions
Protocol Decode
DSI/CSI-2
Standalone
Decoder
Scope-based
Decoder
Tx
Rx
HS Gear
2.5G
D-PHY 1.2
D-PHY TX
Personality
Automated D-
PHY TX
software
Automated D-
PHY RX
software
D-PHY Siggen
D-PHY 2.0
4.5 G
DSI/CSI-2
Pattern
Generator
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Tektronix Solution Roadmap Partner Solution

23. Electrical
M-PHY Test Solutions
Protocol Decode
LLI
HSI
DigiRFv4
SSIC
MPCIe
UniPro
DSI 2
CSI 3
UFS
Tx
Rx
HS G1
HS G2
HS G3
HS G4
M-PHY TX
personality
Automated M-
PHY TX
software
Automated M-
PHY RX
software
PWM
G0 –G7
SYS
Tektronix Solution Roadmap Partner Solution
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24. C-PHY Test Solutions
Protocol Decode
DSI/CSI-2
Standalone
Decoder
Scope-based
Decoder
Tx
Rx
HS & HS-
LP
2.5 Gb/s
Automated C-
PHY RX
software
C-PHY SigGen
C-PHY 4-lane
Pattern
Generator
Electrical
C-PHY TX
Personality
Automated C-
PHY TX
software
Intel MIPI Webinar MIPI Phy Solutions
Tektronix Solution Roadmap Partner Solution

25. Information & Resources for MIPI
www.tek.com/technology/mipi
Webinars
Application Notes
Methods of Implementation
Product & Software Datasheets
Software Download Trials
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