MOS Device: static and dynamic behavior.ppt

MOS Device: static and dynamic behavior

1. Introduction to
CMOS VLSI
Design
MOS devices: static and
dynamic behavior

2. MOS equations Slide 2CMOS VLSI Design
Outline
DC Response
Logic Levels and Noise Margins
Transient Response
Delay Estimation

3. MOS equations Slide 3CMOS VLSI Design
Activity
1)    

If the width of a transistor increases, the current will
 
increase decrease not change 
2)    

If the length of a transistor increases, the current will
increase decrease not change
3)    

If the supply voltage of a chip increases, the maximum
transistor current will
increase decrease not change
4)    

If the width of a transistor increases, its gate capacitance will
increase decrease not change
5)    

If the length of a transistor increases, its gate capacitance will
increase decrease not change
6)    

If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase decrease not change

4. MOS equations Slide 4CMOS VLSI Design
Activity
1)    

If the width of a transistor increases, the current will
 
increase decrease not change 
2)    

If the length of a transistor increases, the current will
increase decrease not change
3)    

If the supply voltage of a chip increases, the maximum
transistor current will
increase decrease not change
4)    

If the width of a transistor increases, its gate capacitance will
increase decrease not change
5)    

If the length of a transistor increases, its gate capacitance will
increase decrease not change
6)    

If the supply voltage of a chip increases, the gate capacitance
of each transistor will
increase decrease not change

5. MOS equations Slide 5CMOS VLSI Design
DC Response
DC Response: V
out
vs. V
in
for a gate
Ex: Inverter
–When V
in
= 0 -> V
out
= V
DD
–When V
in = V
DD -> V
out = 0
–In between, V
out depends on
transistor size and current
–By KCL, must settle such that
I
dsn = |I
dsp|
–We could solve equations
–But graphical solution gives more insight
I
dsn
I
dsp
V
out
V
DD
V
in

6. MOS equations Slide 6CMOS VLSI Design
Transistor Operation
Current depends on region of transistor behavior
For what V
in
and V
out
are nMOS and pMOS in
–Cutoff?
–Linear?
–Saturation?

7. MOS equations Slide 7CMOS VLSI Design
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
gsn
>
V
dsn
<
V
gsn
>
V
dsn >
I
dsn
I
dsp
V
out
V
DD
V
in

8. MOS equations Slide 8CMOS VLSI Design
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
gsn
> V
tn
V
dsn
< V
gsn
– V
tn
V
gsn
> V
tn
V
dsn > V
gsn – V
tn
I
dsn
I
dsp
V
out
V
DD
V
in

9. MOS equations Slide 9CMOS VLSI Design
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
gsn
> V
tn
V
dsn
< V
gsn
– V
tn
V
gsn
> V
tn
V
dsn > V
gsn – V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn = V
in
V
dsn = V
out

10. MOS equations Slide 10CMOS VLSI Design
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
in
< V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
< V
gsn
– V
tn
V
out
< V
in
- V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
– V
tn
V
out
> V
in
- V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn = V
in
V
dsn = V
out

11. MOS equations Slide 11CMOS VLSI Design
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
gsp
<
V
dsp
>
V
gsp
<
V
dsp
<
I
dsn
I
dsp
V
out
V
DD
V
in

12. MOS equations Slide 12CMOS VLSI Design
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
gsp
< V
tp
V
dsp
> V
gsp
– V
tp
V
gsp
< V
tp
V
dsp
< V
gsp
– V
tp
I
dsn
I
dsp
V
out
V
DD
V
in

13. MOS equations Slide 13CMOS VLSI Design
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
gsp
< V
tp
V
dsp
> V
gsp
– V
tp
V
gsp
< V
tp
V
dsp
< V
gsp
– V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp = V
in
- V
DD
V
dsp = V
out
- V
DD
V
tp < 0

14. MOS equations Slide 14CMOS VLSI Design
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
– V
tp
V
out
> V
in
- V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
– V
tp
V
out
< V
in
- V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp = V
in
- V
DD
V
dsp = V
out
- V
DD
V
tp < 0

15. MOS equations Slide 15CMOS VLSI Design
I-V Characteristics
Make pMOS is wider than nMOS such that 
n = 
p
V
gsn5
V
gsn4
V
gsn3
V
gsn2
V
gsn1
V
gsp5
V
gsp4
V
gsp3
V
gsp2
V
gsp1
V
DD
-V
DD
V
dsn
-V
dsp
-I
dsp
I
dsn
0

16. MOS equations Slide 16CMOS VLSI Design
Current vs. V
out
, V
in
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD

17. MOS equations Slide 17CMOS VLSI Design
Load Line Analysis
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
For a given V
in:
–Plot I
dsn, I
dsp vs. V
out
–V
out must be where |currents| are equal in
I
dsn
I
dsp
V
out
V
DD
V
in

18. MOS equations Slide 18CMOS VLSI Design
Load Line Analysis
V
in0
V
in0
I
dsn
, |I
dsp
|
V
out
V
DD
V
in = 0

19. MOS equations Slide 19CMOS VLSI Design
Load Line Analysis
V
in1
V
in1I
dsn
, |I
dsp
|
V
out
V
DD
V
in = 0.2V
DD

20. MOS equations Slide 20CMOS VLSI Design
Load Line Analysis
V
in2
V
in2
I
dsn
, |I
dsp
|
V
out
V
DD
V
in = 0.4V
DD

21. MOS equations Slide 21CMOS VLSI Design
Load Line Analysis
V
in3
V
in3
I
dsn
, |I
dsp
|
V
out
V
DD
V
in = 0.6V
DD

22. MOS equations Slide 22CMOS VLSI Design
Load Line Analysis
V
in4
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in = 0.8V
DD

23. MOS equations Slide 23CMOS VLSI Design
Load Line Analysis
V
in5
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in = V
DD

24. MOS equations Slide 24CMOS VLSI Design
Load Line Summary
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD

25. MOS equations Slide 25CMOS VLSI Design
DC Transfer Curve
Transcribe points onto V
in vs. V
out plot
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp

26. MOS equations Slide 26CMOS VLSI Design
Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A
B
C
D
E

27. MOS equations Slide 27CMOS VLSI Design
Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A Cutoff Linear
B SaturationLinear
C SaturationSaturation
D Linear Saturation
E Linear Cutoff

28. MOS equations Slide 28CMOS VLSI Design
Beta Ratio
If 
p / 
n  1, switching point will move from V
DD/2
Called skewed gate
Other gates: collapse into equivalent inverter
V
out
0
V
in
V
DD
V
DD
0.5
1
2
10
p
n



0.1
p
n




29. MOS equations Slide 29CMOS VLSI Design
Noise Margins
How much noise can a gate input see before it does
not recognize the input?
Indeterminate
Region
NM
L
NM
H
Input CharacteristicsOutput Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range

30. MOS equations Slide 30CMOS VLSI Design
Logic Levels
To maximize noise margins, select logic levels at
V
DD
V
in
V
out
V
DD

p
/
n
> 1
V
in
V
out
0

31. MOS equations Slide 31CMOS VLSI Design
Logic Levels
To maximize noise margins, select logic levels at
–unity gain point of DC transfer characteristic
V
DD
V
in
V
out
V
OH
V
DD
V
OL
V
IL
V
IH
V
tn
Unity Gain Points
Slope = -1
V
DD
-
|V
tp
|

p
/
n
> 1
V
in
V
out
0

32. MOS equations Slide 32CMOS VLSI Design
Transient Response
DC analysis tells us V
out if V
in is constant
Transient analysis tells us V
out(t) if V
in(t) changes
–Requires solving differential equations
Input is usually considered to be a step or ramp
–From 0 to V
DD or vice versa

33. MOS equations Slide 33CMOS VLSI Design
Inverter Step Response
Ex: find step response of inverter driving load cap
0
( )
(
)
)
(
o
i
ut
n
out
V t t
t
V
t
V
d
d
t



V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

34. MOS equations Slide 34CMOS VLSI Design
Inverter Step Response
Ex: find step response of inverter driving load cap
0
0
()
( )
()
( )
ou
DDin
t
out
u t t V
d
d
t
t t
V t
V
V
t




V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

35. MOS equations Slide 35CMOS VLSI Design
Inverter Step Response
Ex: find step response of inverter driving load cap
0
0
(
( ))
(
(
)
)
DD
Do
i
D
o t
n
ut
u
V t
u t t V
V
d
d
t
t
V
V
t
t
 


V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

36. MOS equations Slide 36CMOS VLSI Design
Inverter Step Response
Ex: find step response of inverter driving load cap
0
0
( )
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
 



0
( )
DD tout
ou
ds
t DD t
n
I t V V
VV V
V
t t

  

 

V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

37. MOS equations Slide 37CMOS VLSI Design
Inverter Step Response
Ex: find step response of inverter driving load cap
0
0
( )
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
 



 
0
2
2
0
2
)
)
(
( )
(
DD DD t
DD
out
out
out out D t
n
t
ds
D
I V
t t
V V V V
V V V V V
t
V t
V t





   

 
    
 
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

38. MOS equations Slide 38CMOS VLSI Design
Inverter Step Response
Ex: find step response of inverter driving load cap
0
0
( )
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
 



 
0
2
2
0
2
)
)
(
( )
(
DD DD t
DD
out
out
out out D t
n
t
ds
D
I V
t t
V V V V
V V V V V
t
V t
V t





   

 
    
 
V
out
(t)
V
in
(t)
t
0
t
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

39. MOS equations Slide 39CMOS VLSI Design
Delay Definitions
t
pdr:
t
pdf
:
t
pd:
t
r
:
t
f: fall time

40. MOS equations Slide 40CMOS VLSI Design
Delay Definitions
t
pdr: rising propagation delay
–From input to rising output crossing V
DD/2
t
pdf: falling propagation delay
–From input to falling output crossing V
DD/2
t
pd: average propagation delay
–t
pd = (t
pdr + t
pdf)/2
t
r: rise time
–From output crossing 0.2 V
DD to 0.8 V
DD
t
f: fall time
–From output crossing 0.8 V
DD to 0.2 V
DD

41. MOS equations Slide 41CMOS VLSI Design
Delay Definitions
t
cdr: rising contamination delay
–From input to rising output crossing V
DD/2
t
cdf: falling contamination delay
–From input to falling output crossing V
DD
/2
t
cd
: average contamination delay
–t
pd
= (t
cdr
+ t
cdf
)/2

42. MOS equations Slide 42CMOS VLSI Design
Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
–Uses more accurate I-V models too!
But simulations take time to write
(V)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0 200p 400p 600p 800p 1n
t
pdf
= 66ps t
pdr
= 83ps
V
in
V
out

43. MOS equations Slide 43CMOS VLSI Design
Delay Estimation
We would like to be able to easily estimate delay
–Not as accurate as simulation
–But easier to ask “What if?”
The step response usually looks like a 1
st
order RC
response with a decaying exponential.
Use RC delay models to estimate delay
–C = total capacitance on output node
–Use effective resistance R
–So that t
pd
= RC
Characterize transistors by finding their effective R
–Depends on average current as gate switches

44. MOS equations Slide 44CMOS VLSI Design
RC Delay Models
Use equivalent circuits for MOS transistors
–Ideal switch + capacitance and ON resistance
–Unit nMOS has resistance R, capacitance C
–Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
kg
s
d
g
s
d
kC
kC
kC
R/k
kg
s
d
g
s
d
kC
kC
kC
2R/k

45. MOS equations Slide 45CMOS VLSI Design
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to
a unit inverter (R).

46. MOS equations Slide 46CMOS VLSI Design
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to
a unit inverter (R).

47. MOS equations Slide 47CMOS VLSI Design
Example: 3-input NAND
Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to
a unit inverter (R).
3
3
222
3

48. MOS equations Slide 48CMOS VLSI Design
3-input NAND Caps
Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
3

49. MOS equations Slide 49CMOS VLSI Design
3-input NAND Caps
Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
3
3C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C

50. MOS equations Slide 50CMOS VLSI Design
3-input NAND Caps
Annotate the 3-input NAND gate with gate and
diffusion capacitance.
9C
3C
3C
3
3
3
222
5C
5C
5C

51. MOS equations Slide 51CMOS VLSI Design
Elmore Delay
ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder
R
1
R
2
R
3
R
N
C
1
C
2
C
3
C
N
   
nodes
1 1 1 2 2 1 2
... ...
pd i to source i
i
N N
t R C
RC R R C R R R C
 

       


52. MOS equations Slide 52CMOS VLSI Design
Example: 2-input NAND
Estimate worst-case rising and falling delay of 2-
input NAND driving h identical gates.
h copies
2
2
22
B
A
x
Y

53. MOS equations Slide 53CMOS VLSI Design
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C
2
2
22
4hC
B
A
x
Y

54. MOS equations Slide 54CMOS VLSI Design
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C
2
2
22
4hC
B
A
x
Y
R
(6+4h)C
Y
pdr
t

55. MOS equations Slide 55CMOS VLSI Design
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C
2
2
22
4hC
B
A
x
Y
R
(6+4h)C
Y  6 4
pdr
t h RC 

56. MOS equations Slide 56CMOS VLSI Design
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C
2
2
22
4hC
B
A
x
Y

57. MOS equations Slide 57CMOS VLSI Design
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C
2
2
22
4hC
B
A
x
Y
pdf
t
(6+4h)C2C
R/2
R/2
x Y

58. MOS equations Slide 58CMOS VLSI Design
Example: 2-input NAND
Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C
2
2
22
4hC
B
A
x
Y
 
 
2 2 2
2 6 4
7 4
R R R
pdf
t C h C
h RC
    
 
 
(6+4h)C2C
R/2
R/2
x Y

59. MOS equations Slide 59CMOS VLSI Design
Delay Components
Delay has two parts
–Parasitic delay
•6 or 7 RC
•Independent of load
–Effort delay
•4h RC
•Proportional to load capacitance

60. MOS equations Slide 60CMOS VLSI Design
Contamination Delay
Best-case (contamination) delay can be substantially
less than propagation delay.
Ex: If both inputs fall simultaneously
6C
2C
2
2
22
4hC
B
A
x
Y
R
(6+4h)C
Y
R
 3 2
cdr
t h RC 

61. MOS equations Slide 61CMOS VLSI Design
7C
3C
3C
3
3
3
222
3C
2C2C
3C3C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
Shared
Contacted
Diffusion
Diffusion Capacitance
we assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
–Reduces output capacitance by 2C
–Merged uncontacted diffusion might help too

62. MOS equations Slide 62CMOS VLSI Design
Layout Comparison
Which layout is better?
A
V
DD
GND
B
Y
A
V
DD
GND
B
Y