MOS Inverters Static Characteristics.pptx

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1. CMOS Digital Integrated Circuits Analysis and Design 1 Unit-2 MOS Inverters : Static Characteristics

2. Introduction Positive logic convention “1” represents high voltage of V DD “0” represents low voltage of The inverter threshold voltage, V th The input voltage, 0<V in < V th output V DD The input voltage, V th <V in <V DD output 2

3. General circuit structure of an nMOS inverter The driver transistor The input voltage V in =V GS The output voltage V out =V DS The source and the substrate are ground, V SB =0 The load device Terminal current I L , terminal voltage V L 3

4. Voltage transfer characteristic (VTC) The VTC describing V out as a function of V in under DC condition Very low voltage level V out =V OH nMOS off, no conducting current, voltage drop across the load is very small, the output voltage is high As V in increases The driver transistor starts conducting, the output voltage starts to decrease The critical voltage point, dV out /dV in =-1 The input low voltage VIL The input high voltage VIH Determining the noise margins Further increase V in Output low voltage V OL , when the input voltage is equal to V OH The inverter threshold voltage V th Define as the point where V in =V out 5

5. Noise immunity and noise margin N ML =V IL -V OL N MH =V OH -V IH The transition region, uncertain region 8

6. 9 Power and area consideration The DC power dissipation The product of its power supply voltage and the amount of current down from the power supply during steady state or in standby mode P DC =V DD I DC =(V DD /2)[I DC (V in =low)+I DC (V in =high)] In deep submicron technologies Subthreshold current is high therefore more power consumption The chip area To reduce the area of the MOS transistor The gate area of the MOS transistor The product of W and L

7. Resistive-load inverter Operation mode V in <V T0 , cut off No current, no voltage drop across the load resistor V out =V DD V T0  V in <V out +V T0 , saturation Initially, V DS >V in -V T0 • With V in ↑ Ð V out ↓ V in  V out +V T0 , linear The output voltage continues to decrease  2 2 in T n R k V  V I    2 out in T out n R k I   2   V  V   V  V 2   10

8. Calculation of V OH , V OL Calculation of V OH – V out =V DD -R L I R – When V in is low  I D =I R =0  V OH =V DD Calculation of V OL – Assume the input voltage is equal to V OH – V in -V T0 ≥ V out  linear region – n L L L R k n R L k R k R R R I 2 V 1 1 2 1 2 L DD T 2 L 2 L DD T 0 0 L DD k n R L  k n R L   2   V DD  V T   V L  V DD  V T   V DD   V   n L       V  2  V  V  V   V  k n   2   V  V  V DD  V OL Using KCL for the output node, i.e. I R  I D  V DD  V out 11

9. 9 Calculation of V IL , and V IH n L out in IH n L n L out L out out in out out n L in L n L L out L in k R k R R dV dV dV dV k R R R dV 3 k R R 2 To determine the unknown variables 1 R dV 2 1 dV k R 2 2 k n R L 1 1 2 k n R L 1 1 dV 2 R V - V k T out L V DD - V out IH T out n in T in T 2 in T out out IL T n in T n in T  2 in T L D D out n 2  V DD V ( V  V )   2       k n   1  V T   V out  V out   2 V    2   V V  V  2 V   V     1   2 V   1    1   k    V  in       2 V  V  V     2     V DD -V out  k n   2   V  V   V  V  V IH is the larger of the two voltage points on the VTC at which the slope is equal to -1 V out  V in - V TO , linear region  2  k R   V T   VDD   V out ( V in  V IL )  V DD  n L   V T  V  V  V  V    1    1   k   V  V   k        V  V By definition, V IL is the smaller of the two input voltage at which the slope of the VTC becomes equal to -1. i.e. dV out /dV in  -1 V out  V in - V T0 , saturation region

10. VTC for different k n R L The term k n R L plays an important role in determining the shape of the voltage transfer characteristic k n R L appears as a critical parameter in expressions for V OL , V IL , and V IH k n R L can be adjusted by circuit designer V OH is determine primarily by the power supply voltage, V DD The adjustment of V OL receives primarily attention than V IL , V IH Larger k n RL  V OL becomes smaller, larger transition slope 18

11. Example 5.1 19

12. L 20 Power consumption The average power consumption When input low, V OL The driver cut-off, no steady-state current flow, DC power consumption is zero When input high, V OH Both driver MOSFET and the load resistor conduct a nonzero current The output voltage V OL , so the current I D =I R =(V DD - V OL )/R L P  V DD  V DD  V OL 2 R DC ( average )

13. Chip area The chip area depend on two parameters The W/L ratio of the driver transistor Gate area WxL The value of the resistor R L Diffused resistor Sheet resistance 20 to 100 Ω / □ Very large length-to-width rations to achieve resistor values on the order if tens to hundreds of k Ω Ploysilicon resistor Doped polysilicon (for gate of the transistor), Rs~20 to 40 Ω / □ Undoped polysilicon, Rs Rs~10M Ω / □ The resistance value can not be controlled very accurately Ð large variation of the VTC Low power static random access memory (SRAM) 21

14. Example 5.2 22

15. Inverters with n-type MOSFET load The resistive-load inverter The large area occupied by the load resistor The main advantage of using a MOSFET as the load device Smaller silicon area occupied by the transistor Better overall performance Enhancement-load nMOS inverter The saturated enhancement-load inverter A single voltage supply A relative simple fabrication process V OH =V DD -V T,load The linear enhancement-type load V OH =V DD Higher noise margins Two separate power supply voltage (drawback) Both type suffer from relatively high stand-by (DC) power dissipation Not used in any large-scale digital applications 23

16. The linear enhancement-type load

17. Depletion-load nMOS inverter

18. 16 Depletion-load nMOS inverter Slightly more complicated Channel implant to adjust the threshold voltage Advantages Sharp VTC transition better noise margins Single power supply Smaller overall layout area Reduce standby (leakage) current The circuit diagram Consisting A nonlinear load resistor, depletion MOSFET, V T0,load <0 A nonideal switch (driver) , enhancement MOSFET, V T0,load >0 – The load transistor GS V =0, always on –  2 The load transistor operates in the linear region 2 2 T , load out T , load out n , load D , load F out F T , load T 0, load  V k For larger output voltage level, V out  V DD  V T,load   2  k n , load  V    V  V I  When the output voltage is small, V out  V DD  V T,load The load transistor is in saturation region V  V  r   2   V  2  ϒ =substrate-bias (or body-effect) coefficient. 2 out DD T , load out DD out n , load D , load k   2 V  V    V  V    V  V  2  I 

19. 17 2 2 2 2 2 2 T , load OL load OL OL T OH driver OH DD OH DD T , load OH n , load D , load  V OH k k k   V T , load  V OL    driver   k load   k  V T   V T  V OL  V OH   V  2   V  V   V  V      V   2 To calculate the output low V OL assume, V in  V OH  V DD  driver  linear region, load  saturation region 2 V  V    V  V    V    V  2   I  Calculation of V OH , V OL , V IL , V iH When V in is smaller than V T  driver  off, load  linear region zero drain current, V OH  V DD

20. 18 Calculation of V OH , V OL , V IL , V IH DD out out DD out DD out load driver dV dV dV k k k out DD T , load out T , load out driver in T T , load out 2 in T load 2 2 2    V  V  V  V    k load  V IL  V T   sbustitute dV out /dV in  - 1        Differential both sides with respect to V in  out    dV      T , load    2  V  V       dV T , load       2  V DD  V out    out  dV T , load   2 V  V      k   V  V   2 V  V    V  V    V    V  2    V  V   Calculation of V IL The driver  saturation region, the load  linear region load dV out dV k k  V out   out   V         V  driver   k load       dV out   dV in   k    V  V         dV in     V out    dV in   dV out   dV out    V    V   V 2 2  F V  V  2 V   sbustitute dV out /dV in  - 1 Differential both sides with respect to V in k driver   2   V 2 2  k driver  Calculation of V IH The driver  linear region, the load  saturation region dV T , load     dV T , load  T , load out IH T out  dV T , load   dV out  T , load out k driver   V out   V in  V T      V  V   2 T , load out 2 load in T out out

21. VTC of depletion load inverters The general shape of the inverter VTC, and ultimately, the noise margins, are determined by The threshold voltage of the driver and the load Set by the fabrication process The driver-to-load ratio k R =(k driver /k load ) Determined by the (W/L) ratios of the driver and the load transistor One important observation A sharp VTC transition and larger noise margins can be obtained with relative small driver-to-load ratios Much small area occupation 31

22. Design of depletion-load inverters The designable parameters in the inverter circuit are The power supply voltage V DD Being determined by other external constrains Determining the output level high V OH =V DD The threshold voltages of the driver and the load Being determined by the fabrication process The (W/L) ratios of the driver and the load transistor • Since the channel doping densities are not equal The channel electron mobilities are not equal K’ n,load ≠ k’ n,driver The actual sizes of the driver and the load transistor are usually determined by other constrains The current-drive capability The steady state power dissipation The transient switching speed R 32 R load R L V  V k k k  W   driver        L  load  L  load  W     L    W   W   driver   driver , k , k  k n  , load  k n  , driver  2  V  V  V  V 2 OH T OL OL  2 T , load OL

23. Power consideration The steady-state DC power consumption Input voltage low The driver off, V out =V OH =V DD No DC power dissipation Input voltage high, V in  V DD and V out =V OL • Assume the input voltage level low 50% operation time and high during the other 50% 33 2 2 DC OH T OL OL driver T , load OL P K    V  V   2 T , load OL  V DD  k load 2 2   2   V  V   V  V 2      V  V   2   K load I DC  V in  V DD

24. Area consideration Figure (a) Sharing a common n+ diffusion region Saving silicon area Depletion mode Threshold voltage adjusted by a donor implant into the channel (W/L) driver >(W/L) load , ratio about 4 Figure (b) Buried contact Reducing area For connecting the gate and the source of the load transistor The polysilicon gate of the depletion mode transistor makes a direct ohmic with the n+ source diffusion The contact window on the intermediate diffusion area can be omitted 34

25. Example 5.3 (1) 35

26. Example 5.3 (2) 36

27. Example 5.3 (3) 37

28. Circuit operation Region A: V in <V T0,n nMOS off, pMOS on Ð I D,n =I D,p =0, V out =V OH =V DD Region B: V in >V T0,n nMOS saturation, the output voltage decreases The critical voltage V IL , (dV out /dV in )=-1 is located within this region As the output further decreases Ð pMOS enter saturation, boundary of region C Region C: If nMOS saturation Ð V DS,n  V GS,n - V T0,n  V out  V in -V T0,n If pMOS saturation Ð V DS,n  V GS,p - V T0,p  V out  V in -V T0,p Both of these conditions for device saturation are illustrated graphically as shaded areas Region D: V out <V in -V T0,p The criical point V IH Region E: V in >V DD +V T0,p V out =V OL =0 47

29. 48 Circuit operation The nMOS and the pMOS transistors an be seen as nearly ideal switches The current drawn from the power supply in both these steady state points region A and region E Nearly equal to zero The only current Ð reverse biased S, D leakage current The CMOS inverter can drive any load Interconnect capacitance Fan-out logic gates Either by supplying current to the load, or by sinking current from the load

30. 30 Calculation of V IL , V IH p R R IL p out DD n n k V k k k  k n       dV in    dV out      V out  V DD    V out  V DD     dV in   dV out  V  V  V    k   V  V   k    V  V    V   V  V   1  k k   V  V   k   2 V  V  V  V  substituting V in  V IL and (dV out /dV in )  - 1 2 2 2 2 nMOS saturation, pMOS linear  2 V out  V T 0, p  V DD  k R V T 0, n where k n IL T . n p out IL T , p DD in DD T 0, p n in T 0, n  V    V  V  2  in DD T , p out DD   V  V  2  k p   2   V in T 0, n   2   V  V   V  V 2  GS , p T 0, p DS , P DS , p 2 p GS , n T 0, n IH n out k V  V  V  V   k        dV out    dV in   dV in    dV out  V  V      V  V    out out k     V  V  V  V    V   V  V  V   V V  V  k   2 V  V  k    V  V  2 V   k   V  V  V  substiting V in  V IH and (dV out /dV in )  - 1 2 k n   2   V 2 2 2 nMOS linear, pMOS saturation out T 0, n DD T , p R out p IH DD T 0, p IH T 0, n p in DD T 0, p n in T 0, n  2 in DD T 0, p 2 p in T , n out  2 GS , p T 0, p k n   2   V  V 2   k p   V GS , n T 0, n DS , n DS , n

31. Threshold voltage The Region C of VTC Completely vertical If the channel length modulation effect is neglected, i.e. if  =0 Exhibits a finite slope If  >0 Fig 5.22 shows the variation of the inversion (switching) threshold voltage V th as function of the transconductance ratio k R 55

32. VTC and power supply current If input voltage is either smaller than V T0,n , or larger than V DD +V T0,p Does not draw any significant current from the power supply Except for small leakage current and subthreshold currents During low-to-high and high-to-low transitions Regions B, C, and D The current being drawn from the power source Reaching its peak value when V in =V th (both saturation mode) 59

33. 35 Example 5.4

34. 36 Supply voltage scaling in CMOS inverters The static characteristics of the CMOS inverter allow significant variation of supply voltage without affecting the functionality of the basic inverter The CMOS inverter will continue to operate correctly with a supply voltage limit value Correct inverter operation will be sustained if at least one of the transistors remains in conduction, for any given voltage The exact shape of the VTC near e limit value is essentially determined by subthreshold conduction properties If the power supply voltage is reduced below the sum of the two threshold The VTC will contain a region in which none of the transistors is conducting The output voltage level is determine by the previous state of the output The VTC exhibits a hysteresis behavior DD T 0, n T 0, p V – V min  V

35. 37 Power and area consideration Power consideration DC power dissipation of the circuit is almost negligible The drain current Source and drain pn junction reverse leakage current In short channel leakage current Subthreshold current However, that the CMOS inverter does conduct a significant amount of current during a switching event Area consideration