MPMC_Slides_Serial_Communication_in_MSP430

Slides for Serial communication in MSP430

1. Serial Communication in MSP430 B.Venkat Sai Koushik B210739EC Group 12

2. Universal Serial Communication Interface(USCI): Multiple serial communication modes are supported by the universal serial communication interface (USCI) modules. Different modes are supported by various USCI modules. Each unique USCI module has a unique letter in its name (USCI_A is distinct from USCI_B, for example). If multiple identical USCI modules are installed on a single device, they are given names that increase in number. One device might have two USCI_A modules, which would be designated as USCI_A0 and USCI_A1. You may find out which USCI modules, if any, are used on a particular device by looking at the data sheet unique to that device.

3. The USCI_Ax modules support: • UART mode • Pulse shaping for IrDA communications • Automatic baud rate detection for LIN communications • SPI mode The USCI_Bx modules support: • I^2C mode • SPI mode

4. BLOCK DIAGRAM OF USCI

5. USCI Introduction: SPI Mode In synchronous mode, the USCI uses the UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE pins to link the MSP430 to an external system. When the UCSYNC bit is set, SPI mode (3-pin or 4-pin) is chosen, and SPI mode is chosen using the UCMODEx bits. SPI mode features include: • 7- or 8-bit data length • LSB-first or MSB-first data transmit and receive • 3-pin and 4-pin SPI operation • Independent transmit and receive shift registers • Separate transmit and receive buffer registers • Continuous transmit and receive operation • Selectable clock polarity and phase control • Programmable clock frequency in master mode • Independent interrupt capability for receive and transmit

6. USCI Operation: SPI Mode Multiple devices use a common clock provided by the master to send and receive serial data in SPI mode. To enable a device to receive and send data, the master controls an additional pin called UCxSTE. Three or four signals are used for SPI data exchange: • UCxSIMO: Slave in, master out – Master mode: UCxSIMO is the data output line. – Slave mode: UCxSIMO is the data input line. • UCxSOMI: Slave out, master in – Master mode: UCxSOMI is the data input line. – Slave mode: UCxSOMI is the data output line. • UCxCLK: USCI SPI clock – Master mode: UCxCLK is an output. – Slave mode: UCxCLK is an input. • UCxSTE: Slave transmit enable

7. SPI Interrupts: One interrupt vector is used for transmission and one interrupt vector is used for reception in the USCI. SPI Transmit Interrupt Operation: The transmitter sets the UCxTXIFG interrupt flag to let UCxTXBUF know it's ready to accept a new character. If both UCxTXIE and GIE are set, an interrupt request is also generated. In the event that a character is written to UCxTXBUF, UCxTXIFG is instantly reset. After a PUC or when UCSWRST = 1, UCxTXIFG is set. After a PUC or when UCSWRST = 1, UCxTXIE is reset.

8. SPI Receive Interrupt Operation: Each time a character is received and loaded into UCxRXBUF, the UCxRXIFG interrupt flag is set. In the event that UCxRXIE and GIE are also set, an interrupt request is generated. When UCSWRST = 1 or a system reset PUC signal occurs, UCxRXIFG and UCxRXIE are reset. When UCxRXBUF is read, the UCxRXIFG is automatically reset. USCI Interrupt Usage: The interrupt vectors shared by USCI_Ax and USCI_Bx are identical. The transmit interrupt flags UCAxTXIFG and UCBxTXIFG share a different interrupt vector from the receive interrupt flags UCAxRXIFG and UCBxRXIFG.

9. Example 1. Shared Receive Interrupt Vectors Software Example USCIA0_RX_USCIB0_RX_ISR BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt? JNZ USCIA0_RX_ISR USCIB0_RX_ISR? ; Read UCB0RXBUF (clears UCB0RXIFG) ... RETI USCIA0_RX_ISR ; Read UCA0RXBUF (clears UCA0RXIFG) ... RETI

10. Example 2. Shared Transmit Interrupt Vectors Software Example USCIA0_TX_USCIB0_TX_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_TX_ISR ; Write UCB0TXBUF (clears UCB0TXIFG) ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF (clears UCA0TXIFG) … RETI

11. UCAxCTL0, UCBxCTL0 Registers 7 6 5 4 3 2 1 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCMODEx UCSYNC rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

12. Description of Pin Register: UCCKPH: Clock phase select 0b = Data is changed on the first UCLK edge and captured on the following edge. 1b = Data is captured on the first UCLK edge and changed on the following edge. UCCKPL: Clock polarity select 0b = The inactive state is low. 1b = The inactive state is high.

13. UCMSB: MSB first select. Controls the direction of the receive and transmit shift register. 0b = LSB first 1b = MSB first UC7BIT: Character length. Selects 7-bit or 8-bit character length. 0b = 8-bit data 1b = 7-bit data

14. UCMST: Master mode select 0b = Slave mode 01b = Master mode UCMODEx: USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00b = 3-pin SPI 01b = 4-pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10b = 4-pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11b = I2C mode

15. UCSYNC: Synchronous mode enable. Must be 1 for SPI mode. 0b = Asynchronous mode 1b = Synchronous mode

16. Thank You