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1. UEC1402 MICROPROCESSOR & MICROCONTROLLER

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3. PROGRAM OUTCOMES Engineering knowledge Problem Analysis Design and Development of Solutions Investigation of Complex problem Modern tool usage Engineer and Society Environment and Sustainability Ethics Individual and team work Communication Project management and Finance Lifelong Learning

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9. 9 Unit 1 to 3 Unit 4 & 5

10. THE 8086 MICROPROCESSOR UNIT 1 10

11. CONTENTS 11

12. Introduction to 8086 cannot be used stand alone since unlike a microcontroller it has no memory or peripherals 12

13. INTRODUCTION Microprocessor is a CPU on a single IC containing millions of very small components including transistors, resistors and diodes which work together. The microprocessor is a programmable device that takes in numbers, performs on them arithmetic or logical operations according to the program stored in memory and then produces other numbers as a result.

14. Little history 2 bit 2002 in early 1970s 4 bit 4004 in 1971 8 bit 8008 in 1972

15. CLASSIFICATION OF MICROPROCESSOR i )Based on size of the data: 4bit,8 bit,16 bit&32 bit. i i)Based on the application of the processor General Purpose Processor Microcontroller Special Purpose Processor

16. BLOCK DIAGRAM

17. ADVANTAGES Small size Low power consumption Reliable, versatile Low cost High speed of operation High processing capacity

18. Introduction 18

19. Overview of Microcomputer System 19

20. General Operation of a Computer 20

21. Microprocessors in Digital System Design 21

22. History of Microprocessors 22 Fair child semiconductors (founded in 1957) invented the first Integrated Circuit in 1959 that marked the microprocessor history. In 1968, Gordan Moore, Robert Noyce and Andrew Grove resigned from the Fair child semiconductors and started their own company: Integrated Electronics (Intel). In 1971, the first microprocessor Intel 4004 was invented.

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26. Generation of Microprocessor 26

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29. UNIT 1 – INTRODUCTION AND ARCHITECTURE OF MICROPROCESSORS Evolution of Microprocessors Von Neumann and Harvard Architectures 8086 Architecture Signal Description Addressing modes Instruction Set Assembler Directives Interrupts Procedure and Macro

30. MICROPORCESSOR - DEFINITION A multipurpose, Programmable electronic device that reads binary instruction from a storage device called memory, accepts binary data as input and processes the data according those instruction and provides results as output.

31. Block Diagram – S imple Microcomputer

32. Terms used in Microprocessor ALU – Arithmetic & Logical Unit Register array – temporary data storage Control Unit – Controls the flow of data on microprocessor, memory and peripherals Memory – used to store bulk of data and address Port – the physical device used to interface the computer buses to external system Bus – group of lines used to carry information (address bus, data bus, control bus)

33. Terms used in Microprocessor Programming system: Machine language Assembly language (Assembler converts the assembly language into machine language) High level language (Compiler converts the high level language into machine language) Bit – a single binary digit Nibble – 4 bits Byte – 8 bits Word – 16 bits Data – the quantity operated by an instruction of a program Address – an identification number in binary for memory locations

34. ADDRESS LABEL PROGRAM COMMENTS MOV CX, 0000H Initialize counter CX MOV AX,[1200] Get the first data in AX reg MOV BX, [1202] Get the second data in BX reg ADD AX,BX Add BX and AX JNC LOOP1 Check for carry INC CX If carry exists, increment the CX LOOP1 MOV [1206],CX Store the carry MOV [1204], AX Store the sum HLT Terminate the program

35. ADDRESS LABEL PROGRAM COMMENTS START MOV AX,[1200] Get the first data MOV BX, [1202] Get the second data MUL BX Multiply both MOV [1206],AX Store the lower order product MOV AX,DX Copy higher order product to DX MOV [1208],AX Store the higher order product STOP HLT Stop the program

36. 8086 ARCHITECTURE

37. 8086 - ARCHITECTURE Features: The Intel 8086 is a 16 bit Microprocessor It has 16 bit data bus It has 20 bit address bus The memory addressing capacity is 1 MB. Its clock frequency is 5 MHz.

38. 8086 - ARCHITECTURE The 8086 processor is divided into two functional parts which works simultaneously : 1. Bus Interface Unit (BIU) 2. Execution Unit (EU)

39. 8086 - ARCHITECTURE Bus Interface Unit – Interfaces the 8086 with the external world. Functions: Sends out addresses for memory locations and I/O ports. Reads/Writes data for memory and I/O Fetches Instructions from memory . When the EU is busy in instruction execution, the BIU continues fetching instructions from memory and stores them in the instruction queue. Blocks: Instruction Queue (6 byte instruction queue ) Segment Registers ( CS,DS,ES & SS) Instruction Pointer

40. BIU – segment registers

41. BUS INTERFACE UNIT

42. 8086 - ARCHITECTURE Instruction Queue: It fetches six bytes of instructions ahead of time from memory. It follows the principle FIFO (First – in – First - out) It does pipelining (Fetching of next instruction while the current instruction is in execution) Segment Registers: 8086 can address 1 MB of memory. This 1 MB is divided into 16 segments each contains 64KB. Only 4 segments activated at a time. They are, Code segment Register – Code segment is the place where executable program is stored. CS register holds the upper 16 bits of the starting address of the code segment. Stack segment Register – A stack is a section of memory set aside to store addresses and data while sub program executes. SS register holds the upper 16 bits of the starting address of the stack segment.

43. 8086 - ARCHITECTURE Data segment Register - DS register holds the upper 16 bits of the starting address of the data segment. Extra segment Register - ES register holds the upper 16 bits of the starting address of the extra segment . Instruction Pointer: IP register holds the next code byte within the code segment (offset address)

44. 8086 - ARCHITECTURE 2. Execution Unit It does the execution of instructions. Tells BIU (addresses) where to fetch instructions or data Decodes & Executes instructions speeds up processing Blocks: General purpose registers Pointer and Index registers Flag register ALU, Decoder and control circuitry

45. EXECUTION UNIT

46. 8086 - ARCHITECTURE General Purpose Registers: AX – 16 bit accumulator BX – a base register in address calculations to address the memory. CX – an implied counter by certain instructions DX – used to hold extra bits in multiplications and division

47. 8086 - ARCHITECTURE Pointer and Index Registers which are used for various purposes such as addressing memory locations, manipulating data, and controlling the execution of instructions Stack Pointer (SP) – a 16 bit register pointing to program stack in stack segment Base Pointer (BP) – a 16 bit register pointing to data in stack segment. Source Index (SI) – used to hold the offset address of data segment Destination Index (DI) - used to hold the offset address of extra segment Index registers are particularly used for string manipulations

48. Pointer Registers - Stack Pointer (SP) - Purpose: Used to point to the top of the stack. - Function: Stores the offset within the stack segment (SS) which points to the current top of the stack. - Usage: In stack operations like push and pop, SP is updated to reflect the new top of the stack. Example: - SS = 1000H - SP = 0050H - Top of Stack = 10050H

49. Pointer Registers - Base Pointer (BP ) - Purpose: Used to access parameters passed via the stack. - Function: Stores the offset within the stack segment (SS) which points to the base of the stack frame. - Usage: Commonly used in subroutines to access function parameters and local variables. Example: - SS = 1000H - BP = 0040H - Base of Stack Frame = 10040H

50. Index Registers - Source Index (SI) - Purpose: Used as a source pointer in string operations . - Function: Stores the offset within the data segment (DS) or extra segment (ES) which points to the source data. - Usage: Used in instructions like MOVSB, MOVSW, CMPSB, and CMPSW to point to the source string. Example: - DS = 2000H - SI = 0030H - Source Address = 20030H

51. Index Registers - Destination Index (DI) - Purpose: Used as a destination pointer in string operations . - Function: Stores the offset within the extra segment (ES) or data segment (DS) which points to the destination data. - Usage: Used in instructions like MOVSB, MOVSW, STOSB, and STOSW to point to the destination string. Example: - ES = 3000H - DI = 0020H - Destination Address = 30020H

52. PHYSICAL ADDRESS CALCULATION

53. EXECUTION UNIT

54. Program status word (PWD) or Flag Register 54 Carry Parity Auxiliary Carry Zero Overflow Direction Interrupt enable Trap Sign 6 are status flags 3 are control flag

55. 8086 – ARCHITECTURE Flag Register

56. PHYSICAL ADDRESS CALCULATION

57. INSTRUCTION SET Instruction: An instruction is a binary pattern designed inside a microprocessor to perform a specific function Opcode: it stands for operational code. It specifies the type of operation to be performed by CPU. Operand: Data on which operation should act. Operands may be register values or memory values. MOV AX,BX

58. INSTRUCTION SET - CLASSIFICATION Data transfer Instructions Arithmetic Instructions Logical Instructions Shift & Rotate Instructions String Instructions Machine/Processor Control Instructions Control transfer/Branching Instructions Flag manipulation Instructions I/O port Instructions Interrupt Instructions

59. 1. DATA TRANSFER INSTRUCTIONS MOV – This instruction transfers data from one register/memory location to another register/memory location. Format : MOV reg1,reg2 MOV reg1,memory MOV memory,reg1 MOV reg /memory, immediate data Eg : MOV AX,BX MOV AX,[1200] MOV [1200],AX MOV AX,[SI] MOV AX,0001

60. 1. DATA TRANSFER INSTRUCTIONS (ii) XCHG – This instruction exchanges the contents of the specified source and destination operands. Format: XCHG reg1,reg2 XCHG reg1,memory XCHG memory,reg1 Eg : XCHG AX,BX XCHG AX,[1200] XCHG [1200],AX

61. 1. DATA TRANSFER INSTRUCTIONS (iii) PUSH – Pushes the contents of the specified register/memory locations on the stack. The stack pointer is decremented by 2 after each execution of the instruction. Format – PUSH reg /memory location Eg – PUSH AX (iv) POP – Pops out the top of the stack to the destination specified in the instruction. The stack pointer is incremented before execution of instruction Format – POP reg /memory Eg – POP AX

62. 1. DATA TRANSFER INSTRUCTIONS (v) LEA – Load Effective Address Format – LEA BX,memory Eg – LEA BX,[1200] (vi) LDS/LES/LSS – Load data segment/extra segment/stack segment Format – LDS BX,memory Eg – LDS BX,[1200]

63. 2. ARITHMETIC INSTRUCTIONS ADD – This instruction adds the source and destination operands and stores the result in destination. Format – ADD reg1,reg2 ( reg1=reg1+reg2) ADD reg1,memory Eg – ADD AX,BX ADD AX,[1200] (ii) ADC – Addition with carry Format – ADC reg1,reg2 (reg1 = reg1+reg2+CF) ADC reg1,memory Eg – ADC AX,BX ADC AX,[1200]

64. 2. ARITHMETIC INSTRUCTIONS (iii) SUB – This instruction subtracts the source and destination operands and stores the result in destination. Format – SUB reg1,reg2 (reg1=reg1-reg2) SUB reg1,memory Eg – SUB AX,BX SUB AX,[1200] (iv) SBB – Subtraction with borrow Format – SBB reg1,reg2 (reg1 = reg1-reg2-CF) SBB reg1,memory Eg – SBB AX,BX SBB AX,[1200]

65. 2. ARITHMETIC INSTRUCTIONS (v) MUL – unsigned multiplication Format – MUL reg ([DX][AX] = AX* reg ) Eg – MUL CL ([AX] = [CL]*[AL]) MUL CX([DX][AX] = [CX]*[AX]) (vi) IMUL – signed multiplication (vii) DIV – unsigned division Format – DIV reg ([DX][AX] = [DX][AX]/ reg ) Eg – DIV BL (quotient [AX] = [AL]/[BL]; Remainder [DX] = [AL]/[BL]) DIV BX ( quotient [AX] = [DX][AX]/[BX]; Remainder [DX] = [DX][AX]/[BX]) (viii) IDIV – signed division

66. 2. ARITHMETIC INSTRUCTIONS (ix) INC – This instruction adds 1 to the content of a specified memory location or a register. Format – INC reg /memory ( reg =reg+1/memory = memory+1) Eg – INC AX (x) DEC – This instruction subtracts 1 to the content of a specified memory location or a register. Format – DEC reg /memory ( reg =reg-1/memory = memory-1) Eg – DEC AX

67. 2. ARITHMETIC INSTRUCTIONS (xi) NEG – The negation instruction calculates the 2’s complement of a number. Format – NEG reg /memory Eg – NEG AL (xii) CMP – Comparison operation is performed by subtraction. But the results would not be stored rather the flags will get affected. Format – CMP reg1,reg2 (reg1-reg2) Eg – CMP AX,BX Condition CF ZF SF AX=BX 1 AX>BX AX<BX 1 1

68. 2. ARITHMETIC INSTRUCTIONS (xiii) DAA – Decimal Adjust after addition Eg – ADD AL,CL DAA

69. 2. ARITHMETIC INSTRUCTIONS (xiii) DAS – Decimal Adjust after subtraction Eg – SUB AL,CL DAS

70. 2. ARITHMETIC INSTRUCTIONS (xix) CBW – Convert Byte to Word Input: AL=08 Output:AX =0008 Input: AL=88 OUTPUT:AX=FF88 (xx) CWD – Convert Word to Double word Input: Ax=1288 Output:DX = 0000;AX=1288 Input: AL=9988 Output:DX = FFFF;AX=9988

71. 3. LOGICAL INSTRUCTIONS NOT – Logical NOT or 1’s complement of a number Format – NOT reg /memory( reg = ~ reg ) Eg – NOT AX (ii) AND – Logical AND between source and destination operands and stores the result in destination. Format – AND reg1,reg2 (reg1 = reg1 AND reg2) Eg – AND AX,BX

72. 3. LOGICAL INSTRUCTIONS (iii) OR – Logical OR between source and destination operands and stores the result in destination. Format – OR reg1,reg2 (reg1 = reg1 OR reg2) Eg – OR AX,BX (iii) XOR – Logical XOR between source and destination operands and stores the result in destination. Format – XOR reg1,reg2 (reg1 = reg1 XOR reg2) Eg – XOR AX,BX

73. 3. LOGICAL INSTRUCTIONS (v) TEST – Logical AND between source and destination operands. But the result would not stored rather the flags get affected Format – TEST reg1,reg2 (reg1 AND reg2) Eg – TEST AX,BX

74. 4.SHIFT and ROTATE INSTRUCTIONS SHIFT – Shift operation can be logical left and right shift and arithmetic right and left shift. SAL/SHL – This instruction shifts each bit in the destination a specified number of bit positions to the left. As a bit is shifted out of the LSB position a zero is placed in LSB. The MSB is shifted into the carry flag. Format – SHL/SAL reg,1 SHL/SAL reg,CL Eg – SAL/SHL AX,1 SAL BL,CL

75. 4.SHIFT and ROTATE INSTRUCTIONS (ii) SAR – Shift Arithmetic Right Format – SAR reg,1 SAR reg,CL Eg – SAR BX,1 SAR BX,CL

76. 4.SHIFT and ROTATE INSTRUCTIONS (iii) SHR – Shift Logical Right Format – SHR reg,1 SHR reg,CL Eg – SHR BX,1 SHR BX,Cl

77. 4.SHIFT and ROTATE INSTRUCTIONS Rotate – rotate the operand by the count specified. ( i ) ROR – Rotate Right Format – ROR reg,1 ROR reg,CL Eg – ROR BX,0001 ROR BX,CL

78. 4.SHIFT and ROTATE INSTRUCTIONS Rotate – rotate the operand by the count specified. (ii) ROL – Rotate Left Format – ROL reg,1 ROL reg,CL Eg – ROL BX,0001 ROL BX,CL

79. 4.SHIFT and ROTATE INSTRUCTIONS (iii) RCL – Rotate Left through Carry Format – RCL reg,1 RCL reg,CL Eg – RCL BX,0001 RCL BX,CL

80. 4.SHIFT and ROTATE INSTRUCTIONS (iv) RCR – Rotate Right through Carry Format – RCR reg,1 RCR reg,CL Eg – RCR BX,0001 RCR BX,CL

81. 5.STRING INSTRUCTIONS MOVSB – Move the string byte from DS:[SI] to ES:[DI] MOVSW – Move the string word from DS:[SI] to ES:[DI] LODSB - Load the string byte from DS:[SI] to AL LODSW - Load the string word from DS:[SI] to AX STOSB – Store the string byte in AL at ES:[DI] STOSW – Store the string word in AX at ES:[DI] CMPSB – Compare the string bytes at DS[SI] and at ES:[DI] CMPSW – Compare the string word at DS[SI] and at ES:[DI]

82. 6. MACHINE/PROCESSOR CONTROL INSTRUCTIONS STC – Set Carry flag CLC – Clear carry flag CMC – Complement Carry flag STD – Set Direction flag CLD – Clear Direction flag STI – Set Interrupt flag CLI – Clear Interrupt flag HLT – Stops the execution NOP – No operation ESC – CPU differentiates 8087 instruction with the ESC instruction. When ESC instruction is decoded bus control is given to 8087 and then CPU deactivates TEST pin and does the process. LOCK – Lock the bus during next instruction WAIT - The processor enters into wait state after execution of the WAIT instruction until TEST pin is low.

83. 7. I/O INSTRUCTIONS IN – It copies a data from the input port to the AL or AX register. Format – IN AL/AX, 8/16 bit port no Eg – IN AL,80 (ii) OUT – It transfers a byte from AL or a word from AX to the port specified in the instruction. Format – OUT 8/16 bit port no,AL /AX Eg – OUT 80,AL

84. 8. FLAG MANIPULATIONINSTRUCTIONS LAHF – This instruction loads the AH register with the lower order byte of the flag register SAHF – This instruction stores the contents of AH register into the lower order byte of the flag register PUSHF – This instruction first decrements the stack pointer by 2. Then the contents of the 16 bit flag register is pushed into the stack addressed by SP. POPF – This instruction moves the contents of the first to locations in stack into flag register and then SP is incremented by 2.

85. 9. CONTROL TRANSFER/BRANCHING INSTRUCTIONS Unconditional Branching: ( i ) JMP – JMP instruction causes the 8086 to fetch its next instruction from the location specified in the instruction rather than from the next location after JMP instruction. Types: Near/ Intrasegment jump Far/Intersegment jump Format – JMP address Eg – JMP 4000 JMP [SI]

86. 9. CONTROL TRANSFER/BRANCHING INSTRUCTIONS Unconditional Branching: (ii) CALL – CALL instruction is used to transfer execution to a subroutine or a procedure Types: Near/ Intrasegment CALL Far/Intersegment CALL Format – CALL address Eg – CALL 4000 Operation (Near CALL)– SP=SP-2 IP loaded into stack IP= IP+address CS remains unchanged

87. 9. CONTROL TRANSFER/BRANCHING INSTRUCTIONS Unconditional Branching: (ii) CALL – CALL instruction is used to transfer execution to a subroutine or a procedure Types: Near/ Intrasegment CALL Far/Intersegment CALL Format – CALL address Eg – CALL 4000 Operation – SP=SP-2 IP loaded into stack IP= IP+address CS remains unchanged

88. 9. CONTROL TRANSFER/BRANCHING INSTRUCTIONS Eg – CALL 4000 Operation (FAR CALL)– SP=SP-2 CS loaded into stack SP=SP-2 IP loaded into stack IP= IP+address CS remains unchanged

89. 9. CONTROL TRANSFER/BRANCHING INSTRUCTIONS Unconditional Branching: (iii) RET – Return instruction will return the execution from a procedure to the next instruction after the CALL instruction in the calling program. Operation – For intrasegment return, IP is loaded from stack SP=SP+2 For intersegment return, IP is loaded from stack SP=SP+2 CS is loaded from stack SP=SP+2

90. 9. CONTROL TRANSFER/BRANCHING INSTRUCTIONS Conditional Jump – It causes the 8086 to branch to a new memory location specified in the instruction if the condition it true. Eg – JC JNC JZ JNZ JE JNE

91. 10. INTERRUPT INSTRUCTIONS Instructions that initiate an interrupt sequence ( i ) INT n – Software interrupt instruction with interrupt type ‘n’ Operation: SP=SP-2 PSW loaded into stack Interrupt flag and Trap flag reset SP=SP-2 CS loaded into stack CS = new address SP=SP-2 IP loaded into stack IP= new offset address

92. 10. INTERRUPT INSTRUCTIONS (ii) IRET – Interrupt Return Operation: IP is loaded from stack SP=SP+2 CS is loaded from stack SP=SP+2 PSW is loaded from stack SP=SP+2

93. ADDRESSING MODE The way in which an operand is specified is called addressing mode ( i ) Immediate addressing mode – Eg : MOV AX,0001 (ii) Register addressing mode – Eg : MOV AX,BX (iii) Direct addressing mode – Eg : MOV AX,[1200] (iv) Register indirect addressing mode – Eg : MOV AX,[SI] (v) Register relative addressing mode – Eg : MOV AX,[BX+7] (vi) Based indexed addressing mode – Eg : MOV AX,[BX+SI] (vii) Relative Based indexed addressing mode - Eg : MOV AX,[BX+SI+7] (viii) Intrasegment direct addressing mode – Eg : JMP 2000 (ix) Intrasegment indirect addressing mode – Eg : JMP [BX] (x) Intrasegment direct addressing mode – Eg : JMP 2000 (xi) Intrasegment indirect addressing mode – Eg : JMP [BX] (xii) String addressing mode – Eg:MOVSB , MOVSW (xiii) I/O addressing mode – Eg : IN AL,08 (xiv) Implied addressing mode – Eg : STC, HLT, STI

94. ASSEMBLER DIRECTIVES An assembler is a program that translates an assembly language program into equivalent machine language program. Assembler directives help the assembler to correctly generate the machine code for the assembly language program. They just give directions to the assembler but are not translated into machine language.

95. ASSEMBLER DIRECTIVES DB : Define Byte Format: Name of the variable DB values Eg : START DB 08 (ii) DW: Define Word Format: Name of the variable DW values Eg : START DB 0808 (iii) DD: Define Double Word Format: Name of the variable DD values Eg : START DB ABCD 0808

96. ASSEMBLER DIRECTIVES (iv) DB : Define Quad word(8 bytes) Format: Name of the variable DQ values Eg : START DB ABCD 1234 0808 2345 (v) DT: Define Ten bytes Format: Name of the variable DT values Eg : START DB 0808 1244 1234 1234 12AB (vi) DD: Define Double Word Format: Name of the variable DD values Eg : START DB ABCD0808

97. ASSEMBLER DIRECTIVES (vii) EQU : Equivalent Format: Name EQU value Eg : X EQU 03 (viii) ASSUME : Assume the name of the logical segment to different segments. Format: ASSUME segment register: name Eg : ASSUME CS:CODE 1, DS:DATA1 (ix) GROUP: To form a logical group of the segments with a similar purpose. Format: NAME GROUP segment, segment… Eg : PROGRAM GROUP Code1, Code2,…

98. ASSEMBLER DIRECTIVES (x) ORG : Origin Format: ORG address Eg : ORG 3000 (xi) END : End of the program Format: END (xii) PROC: Procedure Format: Label PROC NEAR/FAR Eg : PROGRAM PROC NEAR

99. ASSEMBLER DIRECTIVES (xiii) ENDP : END of the procedure Format: Label ENDP Eg : PROGRAM PROC NEAR . . PROGRAM ENDP

100. ASSEMBLER DIRECTIVES ( xiv) MACRO: Macro Format: Label MACRO Eg : CODE MACRO ( xv) ENDM: End of Macro Format : ENDM Eg : CODE MACRO . . . ENDM

101. Procedure Whenever a group of instructions needed to be used several times throughout the program, to avoid writing the sequence of instructions in the program each time, the sequence can be written as a separate sub program called Procedure . Multiple calls Nested Procedure Recursive Procedure

102. PROCEDURE - DEFINITION COST PROC NEAR/FAR . . . COST ENDP

103. MACRO Macro is a segment of code that needs to be written only once. The macro assembler generates the code in the program each time where the macro is “called ” EXAMPLE: CODE MACRO . . . ENDM

104. INTERRUPT INTERRUPT – The process of interrupting the normal execution of the program to carry out the specific task Interrupt Service Routine (ISR) – The program associated with interrupt A Processor can be interrupted By an External signal generated by a peripheral B y an internal sign generated by a special instruction in the program

105. Processing of an Interrupt

106. CLASSIFICATION OF INTERRUPTS Software & Hardware Interrupts Vectored & Non vectored Interrupts Maskable & Non Maskable Interrupts

107. Hardware & Software Interrupts Hardware Interrupt – The interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin of the processor Software Interrupt – The interrupts generated by special instructions. They are used to implement system service/calls

108. Vectored & Non vectored Interrupts Vectored Interrupt - If a program control automatically branches to a specific address when an interrupt signal is accepted by the processor Non vectored Interrupt – the device should supply the address of the ISR to be executed in response to the interrupt.

109. Maskable & Non Maskable Interrupt Maskable Interrupt – the interrupt can be disabled or rejected. Non Maskable Interrupt – the interrupt which cannot be disabled or rejected.

110. Interrupt Vector Table (IVT)

111. 8086 PINS & SIGNALS

112. PINS AND SIGNALS 8086 operates in two modes. ( i ) Minimum mode ( single processor) (ii) Maximum mode ( Multiprocessor) The signals are grouped into three categories. Signals common to both the modes. Signals for Minimum mode alone. Signals for Maximum mode alone.

113. COMMON SIGNALS 113 AD -AD 15 (Bidirectional) Address/Data bus Low order address bus; these are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A -A 15 . When data are transmitted over AD lines the symbol D is used in place of AD, for example D -D 7 , D 8 -D 15 or D -D 15 . A 16 /S 3 , A 17 /S 4 , A 18 /S 5 , A 19 /S 6 High order address bus. These are multiplexed with status signals

114. COMMON SIGNALS 114 BHE (Active Low)/S 7 (Output) Bus High Enable/Status It is used to enable data onto the most significant half of data bus, D 8 -D 15 . if it is ‘1’ data is transferred on D -D 07 . 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S 7 . MN/ MX MINIMUM / MAXIMUM This pin signal indicates what mode the processor is to operate in. RD (Read) (Active Low) The signal is used for read operation. It is an output signal. It is active when low.

115. COMMON SIGNAL S 115 TEST input is tested by the ‘WAIT’ instruction. 8086 will enter a wait state after execution of the WAIT instruction and will resume execution only when the is made low by an active hardware. This is used to synchronize an external activity to the processor internal operation.   READY This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal is active high.

116. COMMON SIGNALS 116 RESET (Input) Causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. CLK The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle. INTR Interrupt Request This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This signal is active high and internally synchronized.

117. MINIMUM/MAXIMUM MODE SIGNALS 117 The 8086 microprocessor can work in two modes of operations : Minimum mode and Maximum mode . In the minimum mode of operation the microprocessor do not associate with any co-processors and can not be used for multiprocessor systems. In the maximum mode the 8086 can work in multi-processor or co-processor configuration. Minimum or maximum mode operations are decided by the pin MN/ MX(Active low). When this pin is high 8086 operates in minimum mode otherwise it operates in Maximum mode.

118. MINIMUM MODE SIGNALS Pins 24 -31 For minimum mode operation, the MN/ is tied to VCC (logic high) 8086 itself generates all the bus control signals   DT/ ( Data Transmit/ Receive ) Output signal from the processor to control the direction of data flow through the data transceivers ( Data Transmit/ Receive ) Output signal from the processor to control the direction of data flow through the data transceivers ( Data Enable ) Output signal from the processor used as out put enable for the transceivers ( Data Enable ) Output signal from the processor used as out put enable for the transceivers ALE ( Address Latch Enable ) Used to demultiplex the address and data lines using external latches M/ Used to differentiate memory access and I/O access. For memory reference instructions, it is high . For IN and OUT instructions, it is low . Used to differentiate memory access and I/O access. For memory reference instructions, it is high . For IN and OUT instructions, it is low . Write control signal; asserted low Whenever processor writes data to memory or I/O port Write control signal; asserted low Whenever processor writes data to memory or I/O port ( Interrupt Acknowledge ) When the interrupt request is accepted by the processor, the output is low on this line. ( Interrupt Acknowledge ) When the interrupt request is accepted by the processor, the output is low on this line. 118

119. MINIMUM MODE SIGNALS HOLD Input signal to the processor form the bus masters as a request to grant the control of the bus. Usually used by the DMA controller to get the control of the bus. HLDA ( Hold Acknowledge ) Acknowledge signal by the processor to the bus master requesting the control of the bus through HOLD. The acknowledge is asserted high, when the processor accepts HOLD. 119 Pins 24 -31 For minimum mode operation, the MN/ is tied to VCC (logic high) 8086 itself generates all the bus control signals  

120. MAXIMUM MODE SIGNALS During maximum mode operation, the MN/ is grounded (logic low) Pins 24 -31 are reassigned   , , Status signals ; used by the 8086 bus controller to generate bus timing and control signals. These are decoded as shown. Status signals ; used by the 8086 bus controller to generate bus timing and control signals. These are decoded as shown. 120

121. MAXIMUM MODE SIGNALS During maximum mode operation, the MN/ is grounded (logic low) Pins 24 -31 are reassigned   , ( Queue Status ) The processor provides the status of queue in these lines. The queue status can be used by external device to track the internal status of the queue in 8086. The output on QS and QS 1 can be interpreted as shown in the table. ( Queue Status ) The processor provides the status of queue in these lines. The queue status can be used by external device to track the internal status of the queue in 8086. The output on QS and QS 1 can be interpreted as shown in the table. 121

122. MAXIMUM MODE SIGNALS During maximum mode operation, the MN/ is grounded (logic low) Pins 24 -31 are reassigned   , ( Bus Request/ Bus Grant ) These requests are used by other local bus masters to force the processor to release the local bus at the end of the processor’s current bus cycle. These pins are bidirectional. The request on will have higher priority than 122 An output signal activated by the LOCK prefix instruction. Remains active until the completion of the instruction prefixed by LOCK. The 8086 output low on the pin while executing an instruction prefixed by LOCK to prevent other bus masters from gaining control of the system bus.

123. Von Neumann and Harvard Architectures VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE It is ancient computer architecture based on stored program computer concept. It is modern computer architecture based on Harvard Mark I relay based model. Same physical memory address is used for instructions and data. Separate physical memory address is used for instructions and data. There is common bus for data and instruction transfer. Separate buses are used for transferring data and instruction. Two clock cycles are required to execute single instruction. An instruction is executed in a single cycle. It is cheaper in cost. It is costly than Von Neumann Architecture. CPU can not access instructions and read/write at the same time. CPU can access instructions and read/write at the same time. It is used in personal computers and small computers. It is used in micro controllers and signal processing.

124. Von Neumann and Harvard Architectures

125. UNIT 2 8086 BUS ARCHITECTURE AND INTERFACING Modes of operation Memory Interfacing and I/O Interfacing Parallel Communication Interface Serial Communication Interface Timer Keyboard and Display Controller DMA Controller Introduction to Mobile Processors

126. Modes of Operation MINIMUM MODE MN/MX is connected to +5V. S ingle Processor all control signals are given out by Microprocessor itself MAXIMUM MODE MN/MX is connected to Gnd Multiprocessor The chip called Bus controller derives the control signals

127. MINIMUM MODE CONFIGURATION

128. MAXIMUM MODE CONFIGURATION

129. 8255 – PROGRAMMABLE PERIPHERAL INTERFACE FEATURES: ( i ) it has 24 I/O pins that are grouped into three 8 bit ports namely A,B,C. (ii) the eight bit ports of port C can be used as individual bits :(C upper) and (C lower). (iii) modes of operation : I/O mode & BSR mode. (iv) the BSR mode is used to set or reset the bits in port C individually. (v) GA – port A & port Cu. GB – port B & port Cl

130. BLOCK DIAGRAM - 8255

131. MODES OF OPERATION

132. BSR MODE

133. I/O MODE CONTROL WORD FORMAT

134. 8251 – SERIAL COMMUNICATION INTERFACE USART – Universal Synchronous Asynchronous Receiver Transmitter It supports both synchronous and asynchronous communication. It allows full duplex communication. It has built in baud rate generator

135. CONTROL WORDS MODE WORD

136. COMMAND WORD

137. STATUS WORD

138. 8237 – DMA CONTROLLER It has 4 independent channels each of which capable of transferring 64KB. Memory address can be incremented or decremented. It can be cascaded to expand any number of DMA channels.

139. DMA – Block Diagram Data Bus Buffer Timing and Control Unit DMA Channels Priority Block Internal Registers Memory Address Register Count Register Base address and Base count register Command register Mode Register Request Register Mask Register Status Register

140. Command Register

141. Mode Register

142. Request Register

143. Mask register

144. Status Register

145. 8253/54 TIMER/COUNTER Generates accurate time delay. Timer or counter operation Counting in binary or BCD.

146. Control Word Register

147. MODES Mode 0 – Interrupt on terminal count Mode 1 - Programmable one shot Mode 2 – Rate generator Mode 3 – square wave generator Mode 4 - Software Triggered Strobe. Mode 5 - Hardware Triggered Strobe.